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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
[yosys.git] / passes / techmap / abc9.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // [[CITE]] ABC
22 // Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
23 // http://www.eecs.berkeley.edu/~alanmi/abc/
24
25 #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
26 #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p"
27 //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2"
28 //#define ABC_COMMAND_LUT "&st; &sweep; &scorr; &dc2; &retime; &dch -f; &if; &mfs; &ps"
29 #define ABC_COMMAND_LUT "&st; &scorr; &dc2; &retime; &dch -f; &if; &ps -l -m"
30 #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}"
31 #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
32
33 #define ABC_FAST_COMMAND_LIB "strash; dretime; map {D}"
34 #define ABC_FAST_COMMAND_CTR "strash; dretime; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
35 #define ABC_FAST_COMMAND_LUT "&st; &retime; &if"
36 #define ABC_FAST_COMMAND_SOP "strash; dretime; cover -I {I} -P {P}"
37 #define ABC_FAST_COMMAND_DFL "strash; dretime; map"
38
39 #include "kernel/register.h"
40 #include "kernel/sigtools.h"
41 #include "kernel/celltypes.h"
42 #include "kernel/cost.h"
43 #include "kernel/log.h"
44 #include <stdlib.h>
45 #include <stdio.h>
46 #include <string.h>
47 #include <cerrno>
48 #include <sstream>
49 #include <climits>
50
51 #ifndef _WIN32
52 # include <unistd.h>
53 # include <dirent.h>
54 #endif
55
56 #include "frontends/aiger/aigerparse.h"
57
58 #ifdef YOSYS_LINK_ABC
59 extern "C" int Abc_RealMain(int argc, char *argv[]);
60 #endif
61
62 USING_YOSYS_NAMESPACE
63 PRIVATE_NAMESPACE_BEGIN
64
65 bool map_mux4;
66 bool map_mux8;
67 bool map_mux16;
68
69 bool markgroups;
70 int map_autoidx;
71 SigMap assign_map;
72 RTLIL::Module *module;
73 std::map<RTLIL::SigBit, int> signal_map;
74 std::map<RTLIL::SigBit, RTLIL::State> signal_init;
75 pool<std::string> enabled_gates;
76 bool recover_init;
77
78 bool clk_polarity, en_polarity;
79 RTLIL::SigSpec clk_sig, en_sig;
80 dict<int, std::string> pi_map, po_map;
81
82 std::string remap_name(RTLIL::IdString abc_name)
83 {
84 std::stringstream sstr;
85 sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1);
86 return sstr.str();
87 }
88
89 void handle_loops(RTLIL::Design *design)
90 {
91 Pass::call(design, "scc -set_attr abc_scc_id {}");
92
93 design->selection_stack.emplace_back(false);
94 RTLIL::Selection& sel = design->selection_stack.back();
95
96 // For every unique SCC found, (arbitrarily) find the first
97 // cell in the component, and select (and mark) all its output
98 // wires
99 pool<RTLIL::Const> ids_seen;
100 for (auto cell : module->cells()) {
101 auto it = cell->attributes.find("\\abc_scc_id");
102 if (it != cell->attributes.end()) {
103 auto r = ids_seen.insert(it->second);
104 if (r.second) {
105 for (const auto &c : cell->connections()) {
106 if (c.second.is_fully_const()) continue;
107 if (cell->output(c.first)) {
108 SigBit b = c.second.as_bit();
109 Wire *w = b.wire;
110 w->set_bool_attribute("\\abc_scc_break");
111 sel.select(module, w);
112 }
113 }
114 }
115 cell->attributes.erase(it);
116 }
117 }
118
119 // Then cut those selected wires to expose them as new PO/PI
120 Pass::call(design, "expose -cut -sep .abc");
121
122 design->selection_stack.pop_back();
123 }
124
125 std::string add_echos_to_abc_cmd(std::string str)
126 {
127 std::string new_str, token;
128 for (size_t i = 0; i < str.size(); i++) {
129 token += str[i];
130 if (str[i] == ';') {
131 while (i+1 < str.size() && str[i+1] == ' ')
132 i++;
133 new_str += "echo + " + token + " " + token + " ";
134 token.clear();
135 }
136 }
137
138 if (!token.empty()) {
139 if (!new_str.empty())
140 new_str += "echo + " + token + "; ";
141 new_str += token;
142 }
143
144 return new_str;
145 }
146
147 std::string fold_abc_cmd(std::string str)
148 {
149 std::string token, new_str = " ";
150 int char_counter = 10;
151
152 for (size_t i = 0; i <= str.size(); i++) {
153 if (i < str.size())
154 token += str[i];
155 if (i == str.size() || str[i] == ';') {
156 if (char_counter + token.size() > 75)
157 new_str += "\n ", char_counter = 14;
158 new_str += token, char_counter += token.size();
159 token.clear();
160 }
161 }
162
163 return new_str;
164 }
165
166 std::string replace_tempdir(std::string text, std::string tempdir_name, bool show_tempdir)
167 {
168 if (show_tempdir)
169 return text;
170
171 while (1) {
172 size_t pos = text.find(tempdir_name);
173 if (pos == std::string::npos)
174 break;
175 text = text.substr(0, pos) + "<abc-temp-dir>" + text.substr(pos + GetSize(tempdir_name));
176 }
177
178 std::string selfdir_name = proc_self_dirname();
179 if (selfdir_name != "/") {
180 while (1) {
181 size_t pos = text.find(selfdir_name);
182 if (pos == std::string::npos)
183 break;
184 text = text.substr(0, pos) + "<yosys-exe-dir>/" + text.substr(pos + GetSize(selfdir_name));
185 }
186 }
187
188 return text;
189 }
190
191 struct abc_output_filter
192 {
193 bool got_cr;
194 int escape_seq_state;
195 std::string linebuf;
196 std::string tempdir_name;
197 bool show_tempdir;
198
199 abc_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir)
200 {
201 got_cr = false;
202 escape_seq_state = 0;
203 }
204
205 void next_char(char ch)
206 {
207 if (escape_seq_state == 0 && ch == '\033') {
208 escape_seq_state = 1;
209 return;
210 }
211 if (escape_seq_state == 1) {
212 escape_seq_state = ch == '[' ? 2 : 0;
213 return;
214 }
215 if (escape_seq_state == 2) {
216 if ((ch < '0' || '9' < ch) && ch != ';')
217 escape_seq_state = 0;
218 return;
219 }
220 escape_seq_state = 0;
221 if (ch == '\r') {
222 got_cr = true;
223 return;
224 }
225 if (ch == '\n') {
226 log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir).c_str());
227 got_cr = false, linebuf.clear();
228 return;
229 }
230 if (got_cr)
231 got_cr = false, linebuf.clear();
232 linebuf += ch;
233 }
234
235 void next_line(const std::string &line)
236 {
237 int pi, po;
238 if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
239 log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
240 pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???",
241 po, po_map.count(po) ? po_map.at(po).c_str() : "???");
242 return;
243 }
244
245 for (char ch : line)
246 next_char(ch);
247 }
248 };
249
250 static std::pair<RTLIL::IdString, int> wideports_split(std::string name)
251 {
252 int pos = -1;
253
254 if (name.empty() || name.back() != ']')
255 goto failed;
256
257 for (int i = 0; i+1 < GetSize(name); i++) {
258 if (name[i] == '[')
259 pos = i;
260 else if (name[i] < '0' || name[i] > '9')
261 pos = -1;
262 else if (i == pos+1 && name[i] == '0' && name[i+1] != ']')
263 pos = -1;
264 }
265
266 if (pos >= 0)
267 return std::pair<RTLIL::IdString, int>(RTLIL::escape_id(name.substr(0, pos)), atoi(name.c_str() + pos+1));
268
269 failed:
270 return std::pair<RTLIL::IdString, int>(name, 0);
271 }
272
273 void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
274 std::string liberty_file, std::string constr_file, bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
275 bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode,
276 const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, std::string box_file, std::string lut_file)
277 {
278 module = current_module;
279 map_autoidx = autoidx++;
280
281 signal_map.clear();
282 pi_map.clear();
283 po_map.clear();
284 recover_init = false;
285
286 if (clk_str != "$")
287 {
288 clk_polarity = true;
289 clk_sig = RTLIL::SigSpec();
290
291 en_polarity = true;
292 en_sig = RTLIL::SigSpec();
293 }
294
295 if (!clk_str.empty() && clk_str != "$")
296 {
297 if (clk_str.find(',') != std::string::npos) {
298 int pos = clk_str.find(',');
299 std::string en_str = clk_str.substr(pos+1);
300 clk_str = clk_str.substr(0, pos);
301 if (en_str[0] == '!') {
302 en_polarity = false;
303 en_str = en_str.substr(1);
304 }
305 if (module->wires_.count(RTLIL::escape_id(en_str)) != 0)
306 en_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(en_str)), 0));
307 }
308 if (clk_str[0] == '!') {
309 clk_polarity = false;
310 clk_str = clk_str.substr(1);
311 }
312 if (module->wires_.count(RTLIL::escape_id(clk_str)) != 0)
313 clk_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(clk_str)), 0));
314 }
315
316 if (dff_mode && clk_sig.empty())
317 log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
318
319 std::string tempdir_name = "/tmp/yosys-abc-XXXXXX";
320 if (!cleanup)
321 tempdir_name[0] = tempdir_name[4] = '_';
322 tempdir_name = make_temp_dir(tempdir_name);
323 log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
324 module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
325
326 std::string abc_script;
327
328 if (!liberty_file.empty()) {
329 abc_script += stringf("read_lib -w %s; ", liberty_file.c_str());
330 if (!constr_file.empty())
331 abc_script += stringf("read_constr -v %s; ", constr_file.c_str());
332 } else
333 if (!lut_costs.empty()) {
334 abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
335 if (!box_file.empty())
336 abc_script += stringf("read_box -v %s; ", box_file.c_str());
337 }
338 else
339 if (!lut_file.empty()) {
340 abc_script += stringf("read_lut %s; ", lut_file.c_str());
341 if (!box_file.empty())
342 abc_script += stringf("read_box -v %s; ", box_file.c_str());
343 }
344 else
345 abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str());
346
347 abc_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
348
349 if (!script_file.empty()) {
350 if (script_file[0] == '+') {
351 for (size_t i = 1; i < script_file.size(); i++)
352 if (script_file[i] == '\'')
353 abc_script += "'\\''";
354 else if (script_file[i] == ',')
355 abc_script += " ";
356 else
357 abc_script += script_file[i];
358 } else
359 abc_script += stringf("source %s", script_file.c_str());
360 } else if (!lut_costs.empty() || !lut_file.empty()) {
361 //bool all_luts_cost_same = true;
362 //for (int this_cost : lut_costs)
363 // if (this_cost != lut_costs.front())
364 // all_luts_cost_same = false;
365 abc_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
366 //if (all_luts_cost_same && !fast_mode)
367 // abc_script += "; lutpack {S}";
368 } else if (!liberty_file.empty())
369 abc_script += constr_file.empty() ? (fast_mode ? ABC_FAST_COMMAND_LIB : ABC_COMMAND_LIB) : (fast_mode ? ABC_FAST_COMMAND_CTR : ABC_COMMAND_CTR);
370 else if (sop_mode)
371 abc_script += fast_mode ? ABC_FAST_COMMAND_SOP : ABC_COMMAND_SOP;
372 else
373 abc_script += fast_mode ? ABC_FAST_COMMAND_DFL : ABC_COMMAND_DFL;
374
375 if (script_file.empty() && !delay_target.empty())
376 for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1))
377 abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8);
378
379 for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
380 abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);
381
382 for (size_t pos = abc_script.find("{I}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
383 abc_script = abc_script.substr(0, pos) + sop_inputs + abc_script.substr(pos+3);
384
385 for (size_t pos = abc_script.find("{P}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
386 abc_script = abc_script.substr(0, pos) + sop_products + abc_script.substr(pos+3);
387
388 for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
389 abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
390
391 abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
392 abc_script = add_echos_to_abc_cmd(abc_script);
393
394 for (size_t i = 0; i+1 < abc_script.size(); i++)
395 if (abc_script[i] == ';' && abc_script[i+1] == ' ')
396 abc_script[i+1] = '\n';
397
398 FILE *f = fopen(stringf("%s/abc.script", tempdir_name.c_str()).c_str(), "wt");
399 fprintf(f, "%s\n", abc_script.c_str());
400 fclose(f);
401
402 if (dff_mode || !clk_str.empty())
403 {
404 if (clk_sig.size() == 0)
405 log("No%s clock domain found. Not extracting any FF cells.\n", clk_str.empty() ? "" : " matching");
406 else {
407 log("Found%s %s clock domain: %s", clk_str.empty() ? "" : " matching", clk_polarity ? "posedge" : "negedge", log_signal(clk_sig));
408 if (en_sig.size() != 0)
409 log(", enabled by %s%s", en_polarity ? "" : "!", log_signal(en_sig));
410 log("\n");
411 }
412 }
413
414 design->selection_stack.emplace_back(false);
415 RTLIL::Selection& sel = design->selection_stack.back();
416 sel.select(module);
417
418 // Behave as for "abc" where BLIF writer implicitly outputs all undef as zero
419 Pass::call(design, "setundef -zero");
420
421 Pass::call(design, "aigmap");
422
423 handle_loops(design);
424
425 Pass::call(design, stringf("write_xaiger -O -map %s/input.sym %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str()));
426
427 design->selection_stack.pop_back();
428
429 // Now 'unexpose' those wires by undoing
430 // the expose operation -- remove them from PO/PI
431 // and re-connecting them back together
432 for (auto wire : module->wires()) {
433 auto it = wire->attributes.find("\\abc_scc_break");
434 if (it != wire->attributes.end()) {
435 wire->attributes.erase(it);
436 log_assert(wire->port_output);
437 wire->port_output = false;
438 RTLIL::Wire *i_wire = module->wire(wire->name.str() + ".abci");
439 log_assert(i_wire);
440 log_assert(i_wire->port_input);
441 i_wire->port_input = false;
442 module->connect(i_wire, wire);
443 }
444 }
445 module->fixup_ports();
446
447 //log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
448 // count_gates, GetSize(signal_list), count_input, count_output);
449
450 log_push();
451
452 //if (count_output > 0)
453 {
454 log_header(design, "Executing ABC9.\n");
455
456 std::string buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str());
457 f = fopen(buffer.c_str(), "wt");
458 if (f == NULL)
459 log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
460 fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
461 fprintf(f, "GATE ONE 1 Y=CONST1;\n");
462 fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_BUF_"));
463 fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOT_"));
464 if (enabled_gates.empty() || enabled_gates.count("AND"))
465 fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_AND_"));
466 if (enabled_gates.empty() || enabled_gates.count("NAND"))
467 fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NAND_"));
468 if (enabled_gates.empty() || enabled_gates.count("OR"))
469 fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_OR_"));
470 if (enabled_gates.empty() || enabled_gates.count("NOR"))
471 fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOR_"));
472 if (enabled_gates.empty() || enabled_gates.count("XOR"))
473 fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XOR_"));
474 if (enabled_gates.empty() || enabled_gates.count("XNOR"))
475 fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XNOR_"));
476 if (enabled_gates.empty() || enabled_gates.count("ANDNOT"))
477 fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_ANDNOT_"));
478 if (enabled_gates.empty() || enabled_gates.count("ORNOT"))
479 fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_ORNOT_"));
480 if (enabled_gates.empty() || enabled_gates.count("AOI3"))
481 fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI3_"));
482 if (enabled_gates.empty() || enabled_gates.count("OAI3"))
483 fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI3_"));
484 if (enabled_gates.empty() || enabled_gates.count("AOI4"))
485 fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI4_"));
486 if (enabled_gates.empty() || enabled_gates.count("OAI4"))
487 fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI4_"));
488 if (enabled_gates.empty() || enabled_gates.count("MUX"))
489 fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_MUX_"));
490 if (map_mux4)
491 fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*get_cell_cost("$_MUX_"));
492 if (map_mux8)
493 fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*get_cell_cost("$_MUX_"));
494 if (map_mux16)
495 fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*get_cell_cost("$_MUX_"));
496 fclose(f);
497
498 if (!lut_costs.empty()) {
499 buffer = stringf("%s/lutdefs.txt", tempdir_name.c_str());
500 f = fopen(buffer.c_str(), "wt");
501 if (f == NULL)
502 log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
503 for (int i = 0; i < GetSize(lut_costs); i++)
504 fprintf(f, "%d %d.00 1.00\n", i+1, lut_costs.at(i));
505 fclose(f);
506 }
507
508 buffer = stringf("%s -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
509 log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
510
511 #ifndef YOSYS_LINK_ABC
512 abc_output_filter filt(tempdir_name, show_tempdir);
513 int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1));
514 #else
515 // These needs to be mutable, supposedly due to getopt
516 char *abc_argv[5];
517 string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str());
518 abc_argv[0] = strdup(exe_file.c_str());
519 abc_argv[1] = strdup("-s");
520 abc_argv[2] = strdup("-f");
521 abc_argv[3] = strdup(tmp_script_name.c_str());
522 abc_argv[4] = 0;
523 int ret = Abc_RealMain(4, abc_argv);
524 free(abc_argv[0]);
525 free(abc_argv[1]);
526 free(abc_argv[2]);
527 free(abc_argv[3]);
528 #endif
529 if (ret != 0)
530 log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
531
532 buffer = stringf("%s/%s", tempdir_name.c_str(), "output.aig");
533 std::ifstream ifs;
534 ifs.open(buffer);
535 if (ifs.fail())
536 log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
537
538 bool builtin_lib = liberty_file.empty();
539 RTLIL::Design *mapped_design = new RTLIL::Design;
540 //parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
541 buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
542 AigerReader reader(mapped_design, ifs, "\\netlist", "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
543 reader.parse_xaiger();
544
545 ifs.close();
546
547 log_header(design, "Re-integrating ABC9 results.\n");
548 RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"];
549 if (mapped_mod == NULL)
550 log_error("ABC output file does not contain a module `netlist'.\n");
551
552 pool<RTLIL::SigBit> output_bits;
553 for (auto &it : mapped_mod->wires_) {
554 RTLIL::Wire *w = it.second;
555 RTLIL::Wire *remap_wire = module->addWire(remap_name(w->name), GetSize(w));
556 if (markgroups) remap_wire->attributes["\\abcgroup"] = map_autoidx;
557 if (w->port_output) {
558 RTLIL::Wire *wire = module->wire(w->name);
559 if (wire) {
560 for (int i = 0; i < GetSize(wire); i++)
561 output_bits.insert({wire, i});
562 }
563 else {
564 // Attempt another wideports_split here because there
565 // exists the possibility that different bits of a port
566 // could be an input and output, therefore parse_xiager()
567 // could not combine it into a wideport
568 auto r = wideports_split(w->name.str());
569 wire = module->wire(r.first);
570 log_assert(wire);
571 int i = r.second;
572 output_bits.insert({wire, i});
573 }
574 }
575 }
576
577 std::map<std::string, int> cell_stats;
578 for (auto c : mapped_mod->cells())
579 {
580 if (builtin_lib)
581 {
582 if (c->type == "$_NOT_") {
583 RTLIL::Cell *cell;
584 RTLIL::SigBit a_bit = c->getPort("\\A").as_bit();
585 RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit();
586 if (!lut_costs.empty() || !lut_file.empty()) {
587 // ABC can return NOT gates that drive POs
588 if (a_bit.wire->port_input) {
589 // If it's a NOT gate that comes from a primary input directly
590 // then implement it using a LUT
591 cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())),
592 RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset),
593 RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
594 1);
595 }
596 else {
597 // Otherwise, clone the driving LUT to guarantee that we
598 // won't increase the max logic depth
599 // (TODO: Optimise by not cloning unless will increase depth)
600 RTLIL::IdString driver_name;
601 if (GetSize(a_bit.wire) == 1)
602 driver_name = stringf("%s$lut", a_bit.wire->name.c_str());
603 else
604 driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset);
605 RTLIL::Cell* driver = mapped_mod->cell(driver_name);
606 log_assert(driver);
607 auto driver_a = driver->getPort("\\A").chunks();
608 for (auto &chunk : driver_a)
609 chunk.wire = module->wires_[remap_name(chunk.wire->name)];
610 RTLIL::Const driver_lut = driver->getParam("\\LUT");
611 for (auto &b : driver_lut.bits) {
612 if (b == RTLIL::State::S0) b = RTLIL::State::S1;
613 else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
614 }
615 cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())),
616 driver_a,
617 RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
618 driver_lut);
619 }
620 cell_stats["$lut"]++;
621 }
622 else {
623 cell = module->addCell(remap_name(c->name), "$_NOT_");
624 cell->setPort("\\A", RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset));
625 cell->setPort("\\Y", RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset));
626 cell_stats[RTLIL::unescape_id(c->type)]++;
627 }
628 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
629 continue;
630 }
631
632 cell_stats[RTLIL::unescape_id(c->type)]++;
633 if (c->type == "\\ZERO" || c->type == "\\ONE") {
634 RTLIL::SigSig conn;
635 conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]);
636 conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1);
637 module->connect(conn);
638 continue;
639 }
640 if (c->type == "\\BUF") {
641 RTLIL::SigSig conn;
642 conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]);
643 conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]);
644 module->connect(conn);
645 continue;
646 }
647
648 if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR" || c->type == "\\NAND" || c->type == "\\NOR" ||
649 c->type == "\\XNOR" || c->type == "\\ANDNOT" || c->type == "\\ORNOT") {
650 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
651 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
652 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
653 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
654 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
655 continue;
656 }
657 if (c->type == "\\MUX") {
658 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_");
659 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
660 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
661 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
662 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
663 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
664 continue;
665 }
666 if (c->type == "\\MUX4") {
667 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX4_");
668 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
669 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
670 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
671 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
672 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
673 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
674 cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
675 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
676 continue;
677 }
678 if (c->type == "\\MUX8") {
679 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX8_");
680 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
681 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
682 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
683 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
684 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
685 cell->setPort("\\E", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\E").as_wire()->name)]));
686 cell->setPort("\\F", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\F").as_wire()->name)]));
687 cell->setPort("\\G", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\G").as_wire()->name)]));
688 cell->setPort("\\H", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\H").as_wire()->name)]));
689 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
690 cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
691 cell->setPort("\\U", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\U").as_wire()->name)]));
692 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
693 continue;
694 }
695 if (c->type == "\\MUX16") {
696 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX16_");
697 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
698 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
699 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
700 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
701 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
702 cell->setPort("\\E", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\E").as_wire()->name)]));
703 cell->setPort("\\F", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\F").as_wire()->name)]));
704 cell->setPort("\\G", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\G").as_wire()->name)]));
705 cell->setPort("\\H", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\H").as_wire()->name)]));
706 cell->setPort("\\I", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\I").as_wire()->name)]));
707 cell->setPort("\\J", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\J").as_wire()->name)]));
708 cell->setPort("\\K", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\K").as_wire()->name)]));
709 cell->setPort("\\L", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\L").as_wire()->name)]));
710 cell->setPort("\\M", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\M").as_wire()->name)]));
711 cell->setPort("\\N", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\N").as_wire()->name)]));
712 cell->setPort("\\O", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\O").as_wire()->name)]));
713 cell->setPort("\\P", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\P").as_wire()->name)]));
714 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
715 cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
716 cell->setPort("\\U", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\U").as_wire()->name)]));
717 cell->setPort("\\V", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\V").as_wire()->name)]));
718 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
719 continue;
720 }
721 if (c->type == "\\AOI3" || c->type == "\\OAI3") {
722 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
723 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
724 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
725 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
726 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
727 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
728 continue;
729 }
730 if (c->type == "\\AOI4" || c->type == "\\OAI4") {
731 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
732 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
733 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
734 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
735 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
736 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
737 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
738 continue;
739 }
740 if (c->type == "\\DFF") {
741 log_assert(clk_sig.size() == 1);
742 RTLIL::Cell *cell;
743 if (en_sig.size() == 0) {
744 cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
745 } else {
746 log_assert(en_sig.size() == 1);
747 cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
748 cell->setPort("\\E", en_sig);
749 }
750 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
751 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
752 cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
753 cell->setPort("\\C", clk_sig);
754 continue;
755 }
756 }
757 else
758 cell_stats[RTLIL::unescape_id(c->type)]++;
759
760 if (c->type == "\\_const0_" || c->type == "\\_const1_") {
761 RTLIL::SigSig conn;
762 conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->connections().begin()->second.as_wire()->name)]);
763 conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1);
764 module->connect(conn);
765 continue;
766 }
767
768 if (c->type == "\\_dff_") {
769 log_assert(clk_sig.size() == 1);
770 RTLIL::Cell *cell;
771 if (en_sig.size() == 0) {
772 cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
773 } else {
774 log_assert(en_sig.size() == 1);
775 cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
776 cell->setPort("\\E", en_sig);
777 }
778 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
779 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
780 cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
781 cell->setPort("\\C", clk_sig);
782 continue;
783 }
784
785 if (c->type == "$lut" && GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) {
786 SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)];
787 SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)];
788 module->connect(my_y, my_a);
789 continue;
790 }
791
792 RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
793 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
794 cell->parameters = c->parameters;
795 for (auto &conn : c->connections()) {
796 RTLIL::SigSpec newsig;
797 for (auto c : conn.second.chunks()) {
798 if (c.width == 0)
799 continue;
800 //log_assert(c.width == 1);
801 c.wire = module->wires_[remap_name(c.wire->name)];
802 newsig.append(c);
803 }
804 cell->setPort(conn.first, newsig);
805 }
806 }
807
808 // Copy connections (and rename) from mapped_mod to module
809 for (auto conn : mapped_mod->connections()) {
810 if (!conn.first.is_fully_const()) {
811 auto chunks = conn.first.chunks();
812 for (auto &c : chunks)
813 c.wire = module->wires_[remap_name(c.wire->name)];
814 conn.first = std::move(chunks);
815 }
816 if (!conn.second.is_fully_const()) {
817 auto chunks = conn.second.chunks();
818 for (auto &c : chunks)
819 if (c.wire)
820 c.wire = module->wires_[remap_name(c.wire->name)];
821 conn.second = std::move(chunks);
822 }
823 module->connect(conn);
824 }
825
826 if (recover_init)
827 for (auto wire : mapped_mod->wires()) {
828 if (wire->attributes.count("\\init")) {
829 Wire *w = module->wires_[remap_name(wire->name)];
830 log_assert(w->attributes.count("\\init") == 0);
831 w->attributes["\\init"] = wire->attributes.at("\\init");
832 }
833 }
834
835 for (auto &it : cell_stats)
836 log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
837 int in_wires = 0, out_wires = 0;
838 //for (auto &si : signal_list)
839 // if (si.is_port) {
840 // char buffer[100];
841 // snprintf(buffer, 100, "\\n%d", si.id);
842 // RTLIL::SigSig conn;
843 // if (si.type != G(NONE)) {
844 // conn.first = si.bit;
845 // conn.second = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
846 // out_wires++;
847 // } else {
848 // conn.first = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
849 // conn.second = si.bit;
850 // in_wires++;
851 // }
852 // module->connect(conn);
853 // }
854
855 // Go through all AND and NOT output connections,
856 // and for those output ports driving wires
857 // also driven by mapped_mod, disconnect them
858 for (auto cell : module->cells()) {
859 if (!cell->type.in("$_AND_", "$_NOT_"))
860 continue;
861 for (auto &it : cell->connections_) {
862 auto port_name = it.first;
863 if (!cell->output(port_name)) continue;
864 auto &signal = it.second;
865 auto bits = signal.bits();
866 for (auto &b : bits)
867 if (output_bits.count(b))
868 b = module->addWire(NEW_ID);
869 signal = std::move(bits);
870 }
871 }
872 // Do the same for module connections
873 for (auto &it : module->connections_) {
874 auto &signal = it.first;
875 auto bits = signal.bits();
876 for (auto &b : bits)
877 if (output_bits.count(b))
878 b = module->addWire(NEW_ID);
879 signal = std::move(bits);
880 }
881
882 // Stitch in mapped_mod's inputs/outputs into module
883 for (auto &it : mapped_mod->wires_) {
884 RTLIL::Wire *w = it.second;
885 if (!w->port_input && !w->port_output)
886 continue;
887 RTLIL::Wire *wire = module->wire(w->name);
888 RTLIL::Wire *remap_wire = module->wire(remap_name(w->name));
889 RTLIL::SigSpec signal;
890 if (wire) {
891 signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
892 }
893 else {
894 // Attempt another wideports_split here because there
895 // exists the possibility that different bits of a port
896 // could be an input and output, therefore parse_xiager()
897 // could not combine it into a wideport
898 auto r = wideports_split(w->name.str());
899 wire = module->wire(r.first);
900 log_assert(wire);
901 int i = r.second;
902 signal = RTLIL::SigSpec(wire, i);
903 }
904 log_assert(GetSize(signal) >= GetSize(remap_wire));
905
906 log_assert(w->port_input || w->port_output);
907 RTLIL::SigSig conn;
908 if (w->port_input) {
909 conn.first = remap_wire;
910 conn.second = signal;
911 in_wires++;
912 module->connect(conn);
913 }
914 if (w->port_output) {
915 conn.first = signal;
916 conn.second = remap_wire;
917 out_wires++;
918 module->connect(conn);
919 }
920 }
921
922 //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
923 log("ABC RESULTS: input signals: %8d\n", in_wires);
924 log("ABC RESULTS: output signals: %8d\n", out_wires);
925
926 delete mapped_design;
927 }
928 //else
929 //{
930 // log("Don't call ABC as there is nothing to map.\n");
931 //}
932
933 if (cleanup)
934 {
935 log("Removing temp directory.\n");
936 remove_directory(tempdir_name);
937 }
938
939 log_pop();
940 }
941
942 struct Abc9Pass : public Pass {
943 Abc9Pass() : Pass("abc9", "use ABC for technology mapping") { }
944 void help() YS_OVERRIDE
945 {
946 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
947 log("\n");
948 log(" abc9 [options] [selection]\n");
949 log("\n");
950 log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
951 log("library to a target architecture.\n");
952 log("\n");
953 log(" -exe <command>\n");
954 #ifdef ABCEXTERNAL
955 log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
956 #else
957 log(" use the specified command instead of \"<yosys-bindir>/yosys-abc\" to execute ABC.\n");
958 #endif
959 log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
960 log("\n");
961 log(" -script <file>\n");
962 log(" use the specified ABC script file instead of the default script.\n");
963 log("\n");
964 log(" if <file> starts with a plus sign (+), then the rest of the filename\n");
965 log(" string is interpreted as the command string to be passed to ABC. The\n");
966 log(" leading plus sign is removed and all commas (,) in the string are\n");
967 log(" replaced with blanks before the string is passed to ABC.\n");
968 log("\n");
969 log(" if no -script parameter is given, the following scripts are used:\n");
970 log("\n");
971 log(" for -liberty without -constr:\n");
972 log("%s\n", fold_abc_cmd(ABC_COMMAND_LIB).c_str());
973 log("\n");
974 log(" for -liberty with -constr:\n");
975 log("%s\n", fold_abc_cmd(ABC_COMMAND_CTR).c_str());
976 log("\n");
977 log(" for -lut/-luts (only one LUT size):\n");
978 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT "; lutpack {S}").c_str());
979 log("\n");
980 log(" for -lut/-luts (different LUT sizes):\n");
981 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT).c_str());
982 log("\n");
983 log(" for -sop:\n");
984 log("%s\n", fold_abc_cmd(ABC_COMMAND_SOP).c_str());
985 log("\n");
986 log(" otherwise:\n");
987 log("%s\n", fold_abc_cmd(ABC_COMMAND_DFL).c_str());
988 log("\n");
989 log(" -fast\n");
990 log(" use different default scripts that are slightly faster (at the cost\n");
991 log(" of output quality):\n");
992 log("\n");
993 log(" for -liberty without -constr:\n");
994 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LIB).c_str());
995 log("\n");
996 log(" for -liberty with -constr:\n");
997 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_CTR).c_str());
998 log("\n");
999 log(" for -lut/-luts:\n");
1000 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT).c_str());
1001 log("\n");
1002 log(" for -sop:\n");
1003 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_SOP).c_str());
1004 log("\n");
1005 log(" otherwise:\n");
1006 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_DFL).c_str());
1007 log("\n");
1008 log(" -liberty <file>\n");
1009 log(" generate netlists for the specified cell library (using the liberty\n");
1010 log(" file format).\n");
1011 log("\n");
1012 log(" -constr <file>\n");
1013 log(" pass this file with timing constraints to ABC. Use with -liberty.\n");
1014 log("\n");
1015 log(" a constr file contains two lines:\n");
1016 log(" set_driving_cell <cell_name>\n");
1017 log(" set_load <floating_point_number>\n");
1018 log("\n");
1019 log(" the set_driving_cell statement defines which cell type is assumed to\n");
1020 log(" drive the primary inputs and the set_load statement sets the load in\n");
1021 log(" femtofarads for each primary output.\n");
1022 log("\n");
1023 log(" -D <picoseconds>\n");
1024 log(" set delay target. the string {D} in the default scripts above is\n");
1025 log(" replaced by this option when used, and an empty string otherwise.\n");
1026 log(" this also replaces 'dretime' with 'dretime; retime -o {D}' in the\n");
1027 log(" default scripts above.\n");
1028 log("\n");
1029 log(" -I <num>\n");
1030 log(" maximum number of SOP inputs.\n");
1031 log(" (replaces {I} in the default scripts above)\n");
1032 log("\n");
1033 log(" -P <num>\n");
1034 log(" maximum number of SOP products.\n");
1035 log(" (replaces {P} in the default scripts above)\n");
1036 log("\n");
1037 log(" -S <num>\n");
1038 log(" maximum number of LUT inputs shared.\n");
1039 log(" (replaces {S} in the default scripts above, default: -S 1)\n");
1040 log("\n");
1041 log(" -lut <width>\n");
1042 log(" generate netlist using luts of (max) the specified width.\n");
1043 log("\n");
1044 log(" -lut <w1>:<w2>\n");
1045 log(" generate netlist using luts of (max) the specified width <w2>. All\n");
1046 log(" luts with width <= <w1> have constant cost. for luts larger than <w1>\n");
1047 log(" the area cost doubles with each additional input bit. the delay cost\n");
1048 log(" is still constant for all lut widths.\n");
1049 log("\n");
1050 log(" -lut <file>\n");
1051 log(" pass this file with lut library to ABC.\n");
1052 log("\n");
1053 log(" -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..\n");
1054 log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
1055 log(" 2, 3, .. inputs.\n");
1056 log("\n");
1057 log(" -sop\n");
1058 log(" map to sum-of-product cells and inverters\n");
1059 log("\n");
1060 // log(" -mux4, -mux8, -mux16\n");
1061 // log(" try to extract 4-input, 8-input, and/or 16-input muxes\n");
1062 // log(" (ignored when used with -liberty or -lut)\n");
1063 // log("\n");
1064 log(" -g type1,type2,...\n");
1065 log(" Map to the specified list of gate types. Supported gates types are:\n");
1066 log(" AND, NAND, OR, NOR, XOR, XNOR, ANDNOT, ORNOT, MUX, AOI3, OAI3, AOI4, OAI4.\n");
1067 log(" (The NOT gate is always added to this list automatically.)\n");
1068 log("\n");
1069 log(" The following aliases can be used to reference common sets of gate types:\n");
1070 log(" simple: AND OR XOR MUX\n");
1071 log(" cmos2: NAND NOR\n");
1072 log(" cmos3: NAND NOR AOI3 OAI3\n");
1073 log(" cmos4: NAND NOR AOI3 OAI3 AOI4 OAI4\n");
1074 log(" gates: AND NAND OR NOR XOR XNOR ANDNOT ORNOT\n");
1075 log(" aig: AND NAND OR NOR ANDNOT ORNOT\n");
1076 log("\n");
1077 log(" Prefix a gate type with a '-' to remove it from the list. For example\n");
1078 log(" the arguments 'AND,OR,XOR' and 'simple,-MUX' are equivalent.\n");
1079 log("\n");
1080 log(" -dff\n");
1081 log(" also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many\n");
1082 log(" clock domains are automatically partitioned in clock domains and each\n");
1083 log(" domain is passed through ABC independently.\n");
1084 log("\n");
1085 log(" -clk [!]<clock-signal-name>[,[!]<enable-signal-name>]\n");
1086 log(" use only the specified clock domain. this is like -dff, but only FF\n");
1087 log(" cells that belong to the specified clock domain are used.\n");
1088 log("\n");
1089 log(" -keepff\n");
1090 log(" set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
1091 log(" them, for example for equivalence checking.)\n");
1092 log("\n");
1093 log(" -nocleanup\n");
1094 log(" when this option is used, the temporary files created by this pass\n");
1095 log(" are not removed. this is useful for debugging.\n");
1096 log("\n");
1097 log(" -showtmp\n");
1098 log(" print the temp dir name in log. usually this is suppressed so that the\n");
1099 log(" command output is identical across runs.\n");
1100 log("\n");
1101 log(" -markgroups\n");
1102 log(" set a 'abcgroup' attribute on all objects created by ABC. The value of\n");
1103 log(" this attribute is a unique integer for each ABC process started. This\n");
1104 log(" is useful for debugging the partitioning of clock domains.\n");
1105 log("\n");
1106 log(" -box <file>\n");
1107 log(" pass this file with box library to ABC. Use with -lut.\n");
1108 log("\n");
1109 log("When neither -liberty nor -lut is used, the Yosys standard cell library is\n");
1110 log("loaded into ABC before the ABC script is executed.\n");
1111 log("\n");
1112 log("Note that this is a logic optimization pass within Yosys that is calling ABC\n");
1113 log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
1114 log("ABC on logic snippets extracted from your design. You will not get any useful\n");
1115 log("output when passing an ABC script that writes a file. Instead write your full\n");
1116 log("design as BLIF file with write_blif and the load that into ABC externally if\n");
1117 log("you want to use ABC to convert your design into another format.\n");
1118 log("\n");
1119 log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
1120 log("\n");
1121 }
1122 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1123 {
1124 log_header(design, "Executing ABC9 pass (technology mapping using ABC).\n");
1125 log_push();
1126
1127 assign_map.clear();
1128 signal_map.clear();
1129 signal_init.clear();
1130 pi_map.clear();
1131 po_map.clear();
1132
1133 #ifdef ABCEXTERNAL
1134 std::string exe_file = ABCEXTERNAL;
1135 #else
1136 std::string exe_file = proc_self_dirname() + "yosys-abc";
1137 #endif
1138 std::string script_file, liberty_file, constr_file, clk_str, box_file, lut_file;
1139 std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1";
1140 bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
1141 bool show_tempdir = false, sop_mode = false;
1142 vector<int> lut_costs;
1143 markgroups = false;
1144
1145 map_mux4 = false;
1146 map_mux8 = false;
1147 map_mux16 = false;
1148 enabled_gates.clear();
1149
1150 #ifdef _WIN32
1151 #ifndef ABCEXTERNAL
1152 if (!check_file_exists(exe_file + ".exe") && check_file_exists(proc_self_dirname() + "..\\yosys-abc.exe"))
1153 exe_file = proc_self_dirname() + "..\\yosys-abc";
1154 #endif
1155 #endif
1156
1157 size_t argidx;
1158 char pwd [PATH_MAX];
1159 if (!getcwd(pwd, sizeof(pwd))) {
1160 log_cmd_error("getcwd failed: %s\n", strerror(errno));
1161 log_abort();
1162 }
1163 for (argidx = 1; argidx < args.size(); argidx++) {
1164 std::string arg = args[argidx];
1165 if (arg == "-exe" && argidx+1 < args.size()) {
1166 exe_file = args[++argidx];
1167 continue;
1168 }
1169 if (arg == "-script" && argidx+1 < args.size()) {
1170 script_file = args[++argidx];
1171 rewrite_filename(script_file);
1172 if (!script_file.empty() && !is_absolute_path(script_file) && script_file[0] != '+')
1173 script_file = std::string(pwd) + "/" + script_file;
1174 continue;
1175 }
1176 if (arg == "-liberty" && argidx+1 < args.size()) {
1177 liberty_file = args[++argidx];
1178 rewrite_filename(liberty_file);
1179 if (!liberty_file.empty() && !is_absolute_path(liberty_file))
1180 liberty_file = std::string(pwd) + "/" + liberty_file;
1181 continue;
1182 }
1183 if (arg == "-constr" && argidx+1 < args.size()) {
1184 constr_file = args[++argidx];
1185 rewrite_filename(constr_file);
1186 if (!constr_file.empty() && !is_absolute_path(constr_file))
1187 constr_file = std::string(pwd) + "/" + constr_file;
1188 continue;
1189 }
1190 if (arg == "-D" && argidx+1 < args.size()) {
1191 delay_target = "-D " + args[++argidx];
1192 continue;
1193 }
1194 if (arg == "-I" && argidx+1 < args.size()) {
1195 sop_inputs = "-I " + args[++argidx];
1196 continue;
1197 }
1198 if (arg == "-P" && argidx+1 < args.size()) {
1199 sop_products = "-P " + args[++argidx];
1200 continue;
1201 }
1202 if (arg == "-S" && argidx+1 < args.size()) {
1203 lutin_shared = "-S " + args[++argidx];
1204 continue;
1205 }
1206 if (arg == "-lut" && argidx+1 < args.size()) {
1207 string arg = args[++argidx];
1208 size_t pos = arg.find_first_of(':');
1209 int lut_mode = 0, lut_mode2 = 0;
1210 if (pos != string::npos) {
1211 lut_mode = atoi(arg.substr(0, pos).c_str());
1212 lut_mode2 = atoi(arg.substr(pos+1).c_str());
1213 } else {
1214 pos = arg.find_first_of('.');
1215 if (pos != string::npos) {
1216 lut_file = arg;
1217 rewrite_filename(lut_file);
1218 if (!lut_file.empty() && !is_absolute_path(lut_file))
1219 lut_file = std::string(pwd) + "/" + lut_file;
1220 }
1221 else {
1222 lut_mode = atoi(arg.c_str());
1223 lut_mode2 = lut_mode;
1224 }
1225 }
1226 lut_costs.clear();
1227 for (int i = 0; i < lut_mode; i++)
1228 lut_costs.push_back(1);
1229 for (int i = lut_mode; i < lut_mode2; i++)
1230 lut_costs.push_back(2 << (i - lut_mode));
1231 continue;
1232 }
1233 if (arg == "-luts" && argidx+1 < args.size()) {
1234 lut_costs.clear();
1235 for (auto &tok : split_tokens(args[++argidx], ",")) {
1236 auto parts = split_tokens(tok, ":");
1237 if (GetSize(parts) == 0 && !lut_costs.empty())
1238 lut_costs.push_back(lut_costs.back());
1239 else if (GetSize(parts) == 1)
1240 lut_costs.push_back(atoi(parts.at(0).c_str()));
1241 else if (GetSize(parts) == 2)
1242 while (GetSize(lut_costs) < atoi(parts.at(0).c_str()))
1243 lut_costs.push_back(atoi(parts.at(1).c_str()));
1244 else
1245 log_cmd_error("Invalid -luts syntax.\n");
1246 }
1247 continue;
1248 }
1249 if (arg == "-sop") {
1250 sop_mode = true;
1251 continue;
1252 }
1253 if (arg == "-mux4") {
1254 map_mux4 = true;
1255 continue;
1256 }
1257 if (arg == "-mux8") {
1258 map_mux8 = true;
1259 continue;
1260 }
1261 if (arg == "-mux16") {
1262 map_mux16 = true;
1263 continue;
1264 }
1265 if (arg == "-dress") {
1266 // TODO
1267 //abc_dress = true;
1268 continue;
1269 }
1270 if (arg == "-g" && argidx+1 < args.size()) {
1271 for (auto g : split_tokens(args[++argidx], ",")) {
1272 vector<string> gate_list;
1273 bool remove_gates = false;
1274 if (GetSize(g) > 0 && g[0] == '-') {
1275 remove_gates = true;
1276 g = g.substr(1);
1277 }
1278 if (g == "AND") goto ok_gate;
1279 if (g == "NAND") goto ok_gate;
1280 if (g == "OR") goto ok_gate;
1281 if (g == "NOR") goto ok_gate;
1282 if (g == "XOR") goto ok_gate;
1283 if (g == "XNOR") goto ok_gate;
1284 if (g == "ANDNOT") goto ok_gate;
1285 if (g == "ORNOT") goto ok_gate;
1286 if (g == "MUX") goto ok_gate;
1287 if (g == "AOI3") goto ok_gate;
1288 if (g == "OAI3") goto ok_gate;
1289 if (g == "AOI4") goto ok_gate;
1290 if (g == "OAI4") goto ok_gate;
1291 if (g == "simple") {
1292 gate_list.push_back("AND");
1293 gate_list.push_back("OR");
1294 gate_list.push_back("XOR");
1295 gate_list.push_back("MUX");
1296 goto ok_alias;
1297 }
1298 if (g == "cmos2") {
1299 gate_list.push_back("NAND");
1300 gate_list.push_back("NOR");
1301 goto ok_alias;
1302 }
1303 if (g == "cmos3") {
1304 gate_list.push_back("NAND");
1305 gate_list.push_back("NOR");
1306 gate_list.push_back("AOI3");
1307 gate_list.push_back("OAI3");
1308 goto ok_alias;
1309 }
1310 if (g == "cmos4") {
1311 gate_list.push_back("NAND");
1312 gate_list.push_back("NOR");
1313 gate_list.push_back("AOI3");
1314 gate_list.push_back("OAI3");
1315 gate_list.push_back("AOI4");
1316 gate_list.push_back("OAI4");
1317 goto ok_alias;
1318 }
1319 if (g == "gates") {
1320 gate_list.push_back("AND");
1321 gate_list.push_back("NAND");
1322 gate_list.push_back("OR");
1323 gate_list.push_back("NOR");
1324 gate_list.push_back("XOR");
1325 gate_list.push_back("XNOR");
1326 gate_list.push_back("ANDNOT");
1327 gate_list.push_back("ORNOT");
1328 goto ok_alias;
1329 }
1330 if (g == "aig") {
1331 gate_list.push_back("AND");
1332 gate_list.push_back("NAND");
1333 gate_list.push_back("OR");
1334 gate_list.push_back("NOR");
1335 gate_list.push_back("ANDNOT");
1336 gate_list.push_back("ORNOT");
1337 goto ok_alias;
1338 }
1339 cmd_error(args, argidx, stringf("Unsupported gate type: %s", g.c_str()));
1340 ok_gate:
1341 gate_list.push_back(g);
1342 ok_alias:
1343 for (auto gate : gate_list) {
1344 if (remove_gates)
1345 enabled_gates.erase(gate);
1346 else
1347 enabled_gates.insert(gate);
1348 }
1349 }
1350 continue;
1351 }
1352 if (arg == "-fast") {
1353 fast_mode = true;
1354 continue;
1355 }
1356 if (arg == "-dff") {
1357 dff_mode = true;
1358 continue;
1359 }
1360 if (arg == "-clk" && argidx+1 < args.size()) {
1361 clk_str = args[++argidx];
1362 dff_mode = true;
1363 continue;
1364 }
1365 if (arg == "-keepff") {
1366 keepff = true;
1367 continue;
1368 }
1369 if (arg == "-nocleanup") {
1370 cleanup = false;
1371 continue;
1372 }
1373 if (arg == "-showtmp") {
1374 show_tempdir = true;
1375 continue;
1376 }
1377 if (arg == "-markgroups") {
1378 markgroups = true;
1379 continue;
1380 }
1381 if (arg == "-box" && argidx+1 < args.size()) {
1382 box_file = args[++argidx];
1383 rewrite_filename(box_file);
1384 if (!box_file.empty() && !is_absolute_path(box_file))
1385 box_file = std::string(pwd) + "/" + box_file;
1386 continue;
1387 }
1388 break;
1389 }
1390 extra_args(args, argidx, design);
1391
1392 if ((!lut_costs.empty() || !lut_file.empty()) && !liberty_file.empty())
1393 log_cmd_error("Got -lut and -liberty! This two options are exclusive.\n");
1394 if (!constr_file.empty() && liberty_file.empty())
1395 log_cmd_error("Got -constr but no -liberty!\n");
1396
1397 for (auto mod : design->selected_modules())
1398 {
1399 if (mod->attributes.count("\\abc_box_id"))
1400 continue;
1401
1402 if (mod->processes.size() > 0) {
1403 log("Skipping module %s as it contains processes.\n", log_id(mod));
1404 continue;
1405 }
1406
1407 assign_map.set(mod);
1408 signal_init.clear();
1409
1410 for (Wire *wire : mod->wires())
1411 if (wire->attributes.count("\\init")) {
1412 SigSpec initsig = assign_map(wire);
1413 Const initval = wire->attributes.at("\\init");
1414 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
1415 switch (initval[i]) {
1416 case State::S0:
1417 signal_init[initsig[i]] = State::S0;
1418 break;
1419 case State::S1:
1420 signal_init[initsig[i]] = State::S0;
1421 break;
1422 default:
1423 break;
1424 }
1425 }
1426
1427 if (!dff_mode || !clk_str.empty()) {
1428 abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
1429 delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode,
1430 box_file, lut_file);
1431 continue;
1432 }
1433
1434 CellTypes ct(design);
1435
1436 std::vector<RTLIL::Cell*> all_cells = mod->selected_cells();
1437 std::set<RTLIL::Cell*> unassigned_cells(all_cells.begin(), all_cells.end());
1438
1439 std::set<RTLIL::Cell*> expand_queue, next_expand_queue;
1440 std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
1441 std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
1442
1443 typedef tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
1444 std::map<clkdomain_t, std::vector<RTLIL::Cell*>> assigned_cells;
1445 std::map<RTLIL::Cell*, clkdomain_t> assigned_cells_reverse;
1446
1447 std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
1448 std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
1449
1450 for (auto cell : all_cells)
1451 {
1452 clkdomain_t key;
1453
1454 for (auto &conn : cell->connections())
1455 for (auto bit : conn.second) {
1456 bit = assign_map(bit);
1457 if (bit.wire != nullptr) {
1458 cell_to_bit[cell].insert(bit);
1459 bit_to_cell[bit].insert(cell);
1460 if (ct.cell_input(cell->type, conn.first)) {
1461 cell_to_bit_up[cell].insert(bit);
1462 bit_to_cell_down[bit].insert(cell);
1463 }
1464 if (ct.cell_output(cell->type, conn.first)) {
1465 cell_to_bit_down[cell].insert(bit);
1466 bit_to_cell_up[bit].insert(cell);
1467 }
1468 }
1469 }
1470
1471 if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
1472 {
1473 key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
1474 }
1475 else
1476 if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
1477 {
1478 bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_";
1479 bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_";
1480 key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E")));
1481 }
1482 else
1483 continue;
1484
1485 unassigned_cells.erase(cell);
1486 expand_queue.insert(cell);
1487 expand_queue_up.insert(cell);
1488 expand_queue_down.insert(cell);
1489
1490 assigned_cells[key].push_back(cell);
1491 assigned_cells_reverse[cell] = key;
1492 }
1493
1494 while (!expand_queue_up.empty() || !expand_queue_down.empty())
1495 {
1496 if (!expand_queue_up.empty())
1497 {
1498 RTLIL::Cell *cell = *expand_queue_up.begin();
1499 clkdomain_t key = assigned_cells_reverse.at(cell);
1500 expand_queue_up.erase(cell);
1501
1502 for (auto bit : cell_to_bit_up[cell])
1503 for (auto c : bit_to_cell_up[bit])
1504 if (unassigned_cells.count(c)) {
1505 unassigned_cells.erase(c);
1506 next_expand_queue_up.insert(c);
1507 assigned_cells[key].push_back(c);
1508 assigned_cells_reverse[c] = key;
1509 expand_queue.insert(c);
1510 }
1511 }
1512
1513 if (!expand_queue_down.empty())
1514 {
1515 RTLIL::Cell *cell = *expand_queue_down.begin();
1516 clkdomain_t key = assigned_cells_reverse.at(cell);
1517 expand_queue_down.erase(cell);
1518
1519 for (auto bit : cell_to_bit_down[cell])
1520 for (auto c : bit_to_cell_down[bit])
1521 if (unassigned_cells.count(c)) {
1522 unassigned_cells.erase(c);
1523 next_expand_queue_up.insert(c);
1524 assigned_cells[key].push_back(c);
1525 assigned_cells_reverse[c] = key;
1526 expand_queue.insert(c);
1527 }
1528 }
1529
1530 if (expand_queue_up.empty() && expand_queue_down.empty()) {
1531 expand_queue_up.swap(next_expand_queue_up);
1532 expand_queue_down.swap(next_expand_queue_down);
1533 }
1534 }
1535
1536 while (!expand_queue.empty())
1537 {
1538 RTLIL::Cell *cell = *expand_queue.begin();
1539 clkdomain_t key = assigned_cells_reverse.at(cell);
1540 expand_queue.erase(cell);
1541
1542 for (auto bit : cell_to_bit.at(cell)) {
1543 for (auto c : bit_to_cell[bit])
1544 if (unassigned_cells.count(c)) {
1545 unassigned_cells.erase(c);
1546 next_expand_queue.insert(c);
1547 assigned_cells[key].push_back(c);
1548 assigned_cells_reverse[c] = key;
1549 }
1550 bit_to_cell[bit].clear();
1551 }
1552
1553 if (expand_queue.empty())
1554 expand_queue.swap(next_expand_queue);
1555 }
1556
1557 clkdomain_t key(true, RTLIL::SigSpec(), true, RTLIL::SigSpec());
1558 for (auto cell : unassigned_cells) {
1559 assigned_cells[key].push_back(cell);
1560 assigned_cells_reverse[cell] = key;
1561 }
1562
1563 log_header(design, "Summary of detected clock domains:\n");
1564 for (auto &it : assigned_cells)
1565 log(" %d cells in clk=%s%s, en=%s%s\n", GetSize(it.second),
1566 std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
1567 std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
1568
1569 for (auto &it : assigned_cells) {
1570 clk_polarity = std::get<0>(it.first);
1571 clk_sig = assign_map(std::get<1>(it.first));
1572 en_polarity = std::get<2>(it.first);
1573 en_sig = assign_map(std::get<3>(it.first));
1574 abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
1575 keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode,
1576 box_file, lut_file);
1577 assign_map.set(mod);
1578 }
1579 }
1580
1581 Pass::call(design, "clean");
1582
1583 assign_map.clear();
1584 signal_map.clear();
1585 signal_init.clear();
1586 pi_map.clear();
1587 po_map.clear();
1588
1589 log_pop();
1590 }
1591 } Abc9Pass;
1592
1593 PRIVATE_NAMESPACE_END