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[yosys.git] / passes / techmap / abc9.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // [[CITE]] ABC
22 // Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
23 // http://www.eecs.berkeley.edu/~alanmi/abc/
24
25 #if 0
26 // Based on &flow3 - better QoR but more experimental
27 #define ABC_COMMAND_LUT "&st; &ps -l; &sweep -v; &scorr; " \
28 "&st; &if {W}; &save; &st; &syn2; &if {W} -v; &save; &load; "\
29 "&st; &if -g -K 6; &dch -f; &if {W} -v; &save; &load; "\
30 "&st; &if -g -K 6; &synch2; &if {W} -v; &save; &load; "\
31 "&mfs; &ps -l"
32 #else
33 #define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v; &mfs; &ps -l"
34 #endif
35
36
37 #define ABC_FAST_COMMAND_LUT "&st; &if {W} {D}"
38
39 #include "kernel/register.h"
40 #include "kernel/sigtools.h"
41 #include "kernel/celltypes.h"
42 #include "kernel/cost.h"
43 #include "kernel/log.h"
44 #include <stdlib.h>
45 #include <stdio.h>
46 #include <string.h>
47 #include <cerrno>
48 #include <sstream>
49 #include <climits>
50
51 #ifndef _WIN32
52 # include <unistd.h>
53 # include <dirent.h>
54 #endif
55
56 #include "frontends/aiger/aigerparse.h"
57 #include "kernel/utils.h"
58
59 #ifdef YOSYS_LINK_ABC
60 extern "C" int Abc_RealMain(int argc, char *argv[]);
61 #endif
62
63 USING_YOSYS_NAMESPACE
64 PRIVATE_NAMESPACE_BEGIN
65
66 bool markgroups;
67 int map_autoidx;
68
69 inline std::string remap_name(RTLIL::IdString abc9_name)
70 {
71 return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
72 }
73
74 void handle_loops(RTLIL::Design *design, RTLIL::Module *module)
75 {
76 Pass::call(design, "scc -set_attr abc9_scc_id {} % w:*");
77
78 // For every unique SCC found, (arbitrarily) find the first
79 // cell in the component, and select (and mark) all its output
80 // wires
81 pool<RTLIL::Const> ids_seen;
82 for (auto cell : module->cells()) {
83 auto it = cell->attributes.find(ID(abc9_scc_id));
84 if (it != cell->attributes.end()) {
85 auto r = ids_seen.insert(it->second);
86 if (r.second) {
87 for (auto &c : cell->connections_) {
88 if (c.second.is_fully_const()) continue;
89 if (cell->output(c.first)) {
90 SigBit b = c.second.as_bit();
91 Wire *w = b.wire;
92 log_assert(!w->port_input);
93 w->port_input = true;
94 w = module->wire(stringf("%s.abci", w->name.c_str()));
95 if (!w) {
96 w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
97 w->port_output = true;
98 }
99 else {
100 log_assert(w->port_input);
101 log_assert(b.offset < GetSize(w));
102 }
103 w->set_bool_attribute(ID(abc9_scc_break));
104 module->swap_names(b.wire, w);
105 c.second = RTLIL::SigBit(w, b.offset);
106 }
107 }
108 }
109 cell->attributes.erase(it);
110 }
111 }
112
113 module->fixup_ports();
114 }
115
116 std::string add_echos_to_abc9_cmd(std::string str)
117 {
118 std::string new_str, token;
119 for (size_t i = 0; i < str.size(); i++) {
120 token += str[i];
121 if (str[i] == ';') {
122 while (i+1 < str.size() && str[i+1] == ' ')
123 i++;
124 new_str += "echo + " + token + " " + token + " ";
125 token.clear();
126 }
127 }
128
129 if (!token.empty()) {
130 if (!new_str.empty())
131 new_str += "echo + " + token + "; ";
132 new_str += token;
133 }
134
135 return new_str;
136 }
137
138 std::string fold_abc9_cmd(std::string str)
139 {
140 std::string token, new_str = " ";
141 int char_counter = 10;
142
143 for (size_t i = 0; i <= str.size(); i++) {
144 if (i < str.size())
145 token += str[i];
146 if (i == str.size() || str[i] == ';') {
147 if (char_counter + token.size() > 75)
148 new_str += "\n ", char_counter = 14;
149 new_str += token, char_counter += token.size();
150 token.clear();
151 }
152 }
153
154 return new_str;
155 }
156
157 std::string replace_tempdir(std::string text, std::string tempdir_name, bool show_tempdir)
158 {
159 if (show_tempdir)
160 return text;
161
162 while (1) {
163 size_t pos = text.find(tempdir_name);
164 if (pos == std::string::npos)
165 break;
166 text = text.substr(0, pos) + "<abc-temp-dir>" + text.substr(pos + GetSize(tempdir_name));
167 }
168
169 std::string selfdir_name = proc_self_dirname();
170 if (selfdir_name != "/") {
171 while (1) {
172 size_t pos = text.find(selfdir_name);
173 if (pos == std::string::npos)
174 break;
175 text = text.substr(0, pos) + "<yosys-exe-dir>/" + text.substr(pos + GetSize(selfdir_name));
176 }
177 }
178
179 return text;
180 }
181
182 struct abc9_output_filter
183 {
184 bool got_cr;
185 int escape_seq_state;
186 std::string linebuf;
187 std::string tempdir_name;
188 bool show_tempdir;
189
190 abc9_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir)
191 {
192 got_cr = false;
193 escape_seq_state = 0;
194 }
195
196 void next_char(char ch)
197 {
198 if (escape_seq_state == 0 && ch == '\033') {
199 escape_seq_state = 1;
200 return;
201 }
202 if (escape_seq_state == 1) {
203 escape_seq_state = ch == '[' ? 2 : 0;
204 return;
205 }
206 if (escape_seq_state == 2) {
207 if ((ch < '0' || '9' < ch) && ch != ';')
208 escape_seq_state = 0;
209 return;
210 }
211 escape_seq_state = 0;
212 if (ch == '\r') {
213 got_cr = true;
214 return;
215 }
216 if (ch == '\n') {
217 log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir).c_str());
218 got_cr = false, linebuf.clear();
219 return;
220 }
221 if (got_cr)
222 got_cr = false, linebuf.clear();
223 linebuf += ch;
224 }
225
226 void next_line(const std::string &line)
227 {
228 //int pi, po;
229 //if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
230 // log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
231 // pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???",
232 // po, po_map.count(po) ? po_map.at(po).c_str() : "???");
233 // return;
234 //}
235
236 for (char ch : line)
237 next_char(ch);
238 }
239 };
240
241 void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string script_file, std::string exe_file,
242 bool cleanup, vector<int> lut_costs, bool /*dff_mode*/, std::string /*clk_str*/,
243 bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
244 bool show_tempdir, std::string box_file, std::string lut_file,
245 std::string wire_delay, const dict<int,IdString> &box_lookup
246 )
247 {
248 map_autoidx = autoidx++;
249
250 std::string tempdir_name = "/tmp/yosys-abc-XXXXXX";
251 if (!cleanup)
252 tempdir_name[0] = tempdir_name[4] = '_';
253 tempdir_name = make_temp_dir(tempdir_name);
254 log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
255 module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
256
257 std::string abc9_script;
258
259 if (!lut_costs.empty()) {
260 abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
261 if (!box_file.empty())
262 abc9_script += stringf("read_box -v %s; ", box_file.c_str());
263 }
264 else
265 if (!lut_file.empty()) {
266 abc9_script += stringf("read_lut %s; ", lut_file.c_str());
267 if (!box_file.empty())
268 abc9_script += stringf("read_box -v %s; ", box_file.c_str());
269 }
270 else
271 log_abort();
272
273 abc9_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
274
275 if (!script_file.empty()) {
276 if (script_file[0] == '+') {
277 for (size_t i = 1; i < script_file.size(); i++)
278 if (script_file[i] == '\'')
279 abc9_script += "'\\''";
280 else if (script_file[i] == ',')
281 abc9_script += " ";
282 else
283 abc9_script += script_file[i];
284 } else
285 abc9_script += stringf("source %s", script_file.c_str());
286 } else if (!lut_costs.empty() || !lut_file.empty()) {
287 //bool all_luts_cost_same = true;
288 //for (int this_cost : lut_costs)
289 // if (this_cost != lut_costs.front())
290 // all_luts_cost_same = false;
291 abc9_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
292 //if (all_luts_cost_same && !fast_mode)
293 // abc9_script += "; lutpack {S}";
294 } else
295 log_abort();
296
297 //if (script_file.empty() && !delay_target.empty())
298 // for (size_t pos = abc9_script.find("dretime;"); pos != std::string::npos; pos = abc9_script.find("dretime;", pos+1))
299 // abc9_script = abc9_script.substr(0, pos) + "dretime; retime -o {D};" + abc9_script.substr(pos+8);
300
301 for (size_t pos = abc9_script.find("{D}"); pos != std::string::npos; pos = abc9_script.find("{D}", pos))
302 abc9_script = abc9_script.substr(0, pos) + delay_target + abc9_script.substr(pos+3);
303
304 //for (size_t pos = abc9_script.find("{S}"); pos != std::string::npos; pos = abc9_script.find("{S}", pos))
305 // abc9_script = abc9_script.substr(0, pos) + lutin_shared + abc9_script.substr(pos+3);
306
307 for (size_t pos = abc9_script.find("{W}"); pos != std::string::npos; pos = abc9_script.find("{W}", pos))
308 abc9_script = abc9_script.substr(0, pos) + wire_delay + abc9_script.substr(pos+3);
309
310 abc9_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
311 abc9_script = add_echos_to_abc9_cmd(abc9_script);
312
313 for (size_t i = 0; i+1 < abc9_script.size(); i++)
314 if (abc9_script[i] == ';' && abc9_script[i+1] == ' ')
315 abc9_script[i+1] = '\n';
316
317 FILE *f = fopen(stringf("%s/abc.script", tempdir_name.c_str()).c_str(), "wt");
318 fprintf(f, "%s\n", abc9_script.c_str());
319 fclose(f);
320
321 bool count_output = false;
322 for (auto port_name : module->ports) {
323 RTLIL::Wire *port_wire = module->wire(port_name);
324 log_assert(port_wire);
325 if (port_wire->port_output) {
326 count_output = true;
327 break;
328 }
329 }
330
331 log_push();
332
333 if (count_output)
334 {
335 handle_loops(design, module);
336
337 Pass::call(design, "aigmap -select");
338
339 //log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
340 // count_gates, GetSize(signal_list), count_input, count_output);
341
342 Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
343
344 std::string buffer;
345 std::ifstream ifs;
346 #if 0
347 buffer = stringf("%s/%s", tempdir_name.c_str(), "input.xaig");
348 ifs.open(buffer);
349 if (ifs.fail())
350 log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
351 buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
352 log_assert(!design->module(ID($__abc9__)));
353 {
354 AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
355 reader.parse_xaiger();
356 }
357 ifs.close();
358 Pass::call(design, stringf("write_verilog -noexpr -norename"));
359 design->remove(design->module(ID($__abc9__)));
360 #endif
361
362 // Now 'unexpose' those wires by undoing
363 // the expose operation -- remove them from PO/PI
364 // and re-connecting them back together
365 for (auto wire : module->wires()) {
366 auto it = wire->attributes.find(ID(abc9_scc_break));
367 if (it != wire->attributes.end()) {
368 wire->attributes.erase(it);
369 log_assert(wire->port_output);
370 wire->port_output = false;
371 RTLIL::Wire *i_wire = module->wire(wire->name.str() + ".abci");
372 log_assert(i_wire);
373 log_assert(i_wire->port_input);
374 i_wire->port_input = false;
375 module->connect(i_wire, wire);
376 }
377 }
378 module->fixup_ports();
379
380 log_header(design, "Executing ABC9.\n");
381
382 if (!lut_costs.empty()) {
383 buffer = stringf("%s/lutdefs.txt", tempdir_name.c_str());
384 f = fopen(buffer.c_str(), "wt");
385 if (f == NULL)
386 log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
387 for (int i = 0; i < GetSize(lut_costs); i++)
388 fprintf(f, "%d %d.00 1.00\n", i+1, lut_costs.at(i));
389 fclose(f);
390 }
391
392 buffer = stringf("%s -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
393 log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
394
395 #ifndef YOSYS_LINK_ABC
396 abc9_output_filter filt(tempdir_name, show_tempdir);
397 int ret = run_command(buffer, std::bind(&abc9_output_filter::next_line, filt, std::placeholders::_1));
398 #else
399 // These needs to be mutable, supposedly due to getopt
400 char *abc9_argv[5];
401 string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str());
402 abc9_argv[0] = strdup(exe_file.c_str());
403 abc9_argv[1] = strdup("-s");
404 abc9_argv[2] = strdup("-f");
405 abc9_argv[3] = strdup(tmp_script_name.c_str());
406 abc9_argv[4] = 0;
407 int ret = Abc_RealMain(4, abc9_argv);
408 free(abc9_argv[0]);
409 free(abc9_argv[1]);
410 free(abc9_argv[2]);
411 free(abc9_argv[3]);
412 #endif
413 if (ret != 0)
414 log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
415
416 buffer = stringf("%s/%s", tempdir_name.c_str(), "output.aig");
417 ifs.open(buffer, std::ifstream::binary);
418 if (ifs.fail())
419 log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
420
421 buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
422 log_assert(!design->module(ID($__abc9__)));
423
424 AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
425 reader.parse_xaiger(box_lookup);
426 ifs.close();
427
428 #if 0
429 Pass::call(design, stringf("write_verilog -noexpr -norename"));
430 #endif
431
432 log_header(design, "Re-integrating ABC9 results.\n");
433 RTLIL::Module *mapped_mod = design->module(ID($__abc9__));
434 if (mapped_mod == NULL)
435 log_error("ABC output file does not contain a module `$__abc9__'.\n");
436
437 pool<RTLIL::SigBit> output_bits;
438 for (auto &it : mapped_mod->wires_) {
439 RTLIL::Wire *w = it.second;
440 RTLIL::Wire *remap_wire = module->addWire(remap_name(w->name), GetSize(w));
441 if (markgroups) remap_wire->attributes[ID(abcgroup)] = map_autoidx;
442 if (w->port_output) {
443 RTLIL::Wire *wire = module->wire(w->name);
444 log_assert(wire);
445 for (int i = 0; i < GetSize(w); i++)
446 output_bits.insert({wire, i});
447 }
448 }
449
450 for (auto &it : module->connections_) {
451 auto &signal = it.first;
452 auto bits = signal.bits();
453 for (auto &b : bits)
454 if (output_bits.count(b))
455 b = module->addWire(NEW_ID);
456 signal = std::move(bits);
457 }
458
459 dict<IdString, bool> abc9_box;
460 vector<RTLIL::Cell*> boxes;
461 for (auto cell : module->selected_cells()) {
462 if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_))) {
463 module->remove(cell);
464 continue;
465 }
466 auto jt = abc9_box.find(cell->type);
467 if (jt == abc9_box.end()) {
468 RTLIL::Module* box_module = design->module(cell->type);
469 jt = abc9_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(abc9_box_id)))).first;
470 }
471 if (jt->second)
472 boxes.emplace_back(cell);
473 }
474
475 dict<SigBit, pool<IdString>> bit_drivers, bit_users;
476 TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
477 dict<RTLIL::Cell*,RTLIL::Cell*> not2drivers;
478 dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks;
479
480 std::map<IdString, int> cell_stats;
481 for (auto mapped_cell : mapped_mod->cells())
482 {
483 toposort.node(mapped_cell->name);
484
485 RTLIL::Cell *cell = nullptr;
486 if (mapped_cell->type == ID($_NOT_)) {
487 RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A);
488 RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y);
489 bit_users[a_bit].insert(mapped_cell->name);
490 bit_drivers[y_bit].insert(mapped_cell->name);
491
492 if (!a_bit.wire) {
493 mapped_cell->setPort(ID::Y, module->addWire(NEW_ID));
494 RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
495 log_assert(wire);
496 module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
497 }
498 else if (!lut_costs.empty() || !lut_file.empty()) {
499 RTLIL::Cell* driver_lut = nullptr;
500 // ABC can return NOT gates that drive POs
501 if (!a_bit.wire->port_input) {
502 // If it's not a NOT gate that that comes from a PI directly,
503 // find the driver LUT and clone that to guarantee that we won't
504 // increase the max logic depth
505 // (TODO: Optimise by not cloning unless will increase depth)
506 RTLIL::IdString driver_name;
507 if (GetSize(a_bit.wire) == 1)
508 driver_name = stringf("%s$lut", a_bit.wire->name.c_str());
509 else
510 driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset);
511 driver_lut = mapped_mod->cell(driver_name);
512 }
513
514 if (!driver_lut) {
515 // If a driver couldn't be found (could be from PI or box CI)
516 // then implement using a LUT
517 cell = module->addLut(remap_name(stringf("%s$lut", mapped_cell->name.c_str())),
518 RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
519 RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
520 RTLIL::Const::from_string("01"));
521 bit2sinks[cell->getPort(ID::A)].push_back(cell);
522 cell_stats[ID($lut)]++;
523 }
524 else
525 not2drivers[mapped_cell] = driver_lut;
526 continue;
527 }
528 else
529 log_abort();
530 if (cell && markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
531 continue;
532 }
533 cell_stats[mapped_cell->type]++;
534
535 RTLIL::Cell *existing_cell = nullptr;
536 if (mapped_cell->type.in(ID($lut), ID($__ABC9_FF_))) {
537 if (mapped_cell->type == ID($lut) &&
538 GetSize(mapped_cell->getPort(ID::A)) == 1 &&
539 mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
540 SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID::A).as_wire()->name));
541 SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID::Y).as_wire()->name));
542 module->connect(my_y, my_a);
543 if (markgroups) mapped_cell->attributes[ID(abcgroup)] = map_autoidx;
544 log_abort();
545 continue;
546 }
547 cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
548 }
549 else {
550 existing_cell = module->cell(mapped_cell->name);
551 log_assert(existing_cell);
552 cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
553 }
554
555 if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
556 if (existing_cell) {
557 cell->parameters = existing_cell->parameters;
558 cell->attributes = existing_cell->attributes;
559 }
560 else {
561 cell->parameters = mapped_cell->parameters;
562 cell->attributes = mapped_cell->attributes;
563 }
564
565 RTLIL::Module* box_module = design->module(mapped_cell->type);
566 auto abc9_flop = box_module && box_module->attributes.count("\\abc9_flop");
567 for (auto &conn : mapped_cell->connections()) {
568 RTLIL::SigSpec newsig;
569 for (auto c : conn.second.chunks()) {
570 if (c.width == 0)
571 continue;
572 //log_assert(c.width == 1);
573 if (c.wire)
574 c.wire = module->wires_.at(remap_name(c.wire->name));
575 newsig.append(c);
576 }
577 cell->setPort(conn.first, newsig);
578
579 if (!abc9_flop) {
580 if (cell->input(conn.first)) {
581 for (auto i : newsig)
582 bit2sinks[i].push_back(cell);
583 for (auto i : conn.second)
584 bit_users[i].insert(mapped_cell->name);
585 }
586 if (cell->output(conn.first))
587 for (auto i : conn.second)
588 bit_drivers[i].insert(mapped_cell->name);
589 }
590 }
591 }
592
593 for (auto existing_cell : boxes) {
594 Cell *cell = module->cell(remap_name(existing_cell->name));
595 if (cell) {
596 for (auto &conn : existing_cell->connections()) {
597 if (!conn.second.is_wire())
598 continue;
599 Wire *wire = conn.second.as_wire();
600 if (!wire->get_bool_attribute(ID(abc9_padding)))
601 continue;
602 cell->unsetPort(conn.first);
603 log_debug("Dropping padded port connection for %s (%s) .%s (%s )\n", log_id(cell), cell->type.c_str(), log_id(conn.first), log_signal(conn.second));
604 }
605 module->swap_names(cell, existing_cell);
606 }
607 module->remove(existing_cell);
608 }
609
610 // Copy connections (and rename) from mapped_mod to module
611 for (auto conn : mapped_mod->connections()) {
612 if (!conn.first.is_fully_const()) {
613 auto chunks = conn.first.chunks();
614 for (auto &c : chunks)
615 c.wire = module->wires_.at(remap_name(c.wire->name));
616 conn.first = std::move(chunks);
617 }
618 if (!conn.second.is_fully_const()) {
619 auto chunks = conn.second.chunks();
620 for (auto &c : chunks)
621 if (c.wire)
622 c.wire = module->wires_.at(remap_name(c.wire->name));
623 conn.second = std::move(chunks);
624 }
625 module->connect(conn);
626 }
627
628 for (auto &it : cell_stats)
629 log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
630 int in_wires = 0, out_wires = 0;
631
632 // Stitch in mapped_mod's inputs/outputs into module
633 for (auto port : mapped_mod->ports) {
634 RTLIL::Wire *w = mapped_mod->wire(port);
635 RTLIL::Wire *wire = module->wire(port);
636 log_assert(wire);
637 RTLIL::Wire *remap_wire = module->wire(remap_name(port));
638 RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
639 log_assert(GetSize(signal) >= GetSize(remap_wire));
640
641 RTLIL::SigSig conn;
642 if (w->port_output) {
643 conn.first = signal;
644 conn.second = remap_wire;
645 out_wires++;
646 module->connect(conn);
647 }
648 else if (w->port_input) {
649 conn.first = remap_wire;
650 conn.second = signal;
651 in_wires++;
652 module->connect(conn);
653 }
654 }
655
656 for (auto &it : bit_users)
657 if (bit_drivers.count(it.first))
658 for (auto driver_cell : bit_drivers.at(it.first))
659 for (auto user_cell : it.second)
660 toposort.edge(driver_cell, user_cell);
661 bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
662 log_assert(no_loops);
663
664 for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {
665 RTLIL::Cell *not_cell = mapped_mod->cell(*ii);
666 log_assert(not_cell);
667 if (not_cell->type != ID($_NOT_))
668 continue;
669 auto it = not2drivers.find(not_cell);
670 if (it == not2drivers.end())
671 continue;
672 RTLIL::Cell *driver_lut = it->second;
673 RTLIL::SigBit a_bit = not_cell->getPort(ID::A);
674 RTLIL::SigBit y_bit = not_cell->getPort(ID::Y);
675 RTLIL::Const driver_mask;
676
677 a_bit.wire = module->wires_.at(remap_name(a_bit.wire->name));
678 y_bit.wire = module->wires_.at(remap_name(y_bit.wire->name));
679
680 auto jt = bit2sinks.find(a_bit);
681 if (jt == bit2sinks.end())
682 goto clone_lut;
683
684 for (auto sink_cell : jt->second)
685 if (sink_cell->type != ID($lut))
686 goto clone_lut;
687
688 // Push downstream LUTs past inverter
689 for (auto sink_cell : jt->second) {
690 SigSpec A = sink_cell->getPort(ID::A);
691 RTLIL::Const mask = sink_cell->getParam(ID(LUT));
692 int index = 0;
693 for (; index < GetSize(A); index++)
694 if (A[index] == a_bit)
695 break;
696 log_assert(index < GetSize(A));
697 int i = 0;
698 while (i < GetSize(mask)) {
699 for (int j = 0; j < (1 << index); j++)
700 std::swap(mask[i+j], mask[i+j+(1 << index)]);
701 i += 1 << (index+1);
702 }
703 A[index] = y_bit;
704 sink_cell->setPort(ID::A, A);
705 sink_cell->setParam(ID(LUT), mask);
706 }
707
708 // Since we have rewritten all sinks (which we know
709 // to be only LUTs) to be after the inverter, we can
710 // go ahead and clone the LUT with the expectation
711 // that the original driving LUT will become dangling
712 // and get cleaned away
713 clone_lut:
714 driver_mask = driver_lut->getParam(ID(LUT));
715 for (auto &b : driver_mask.bits) {
716 if (b == RTLIL::State::S0) b = RTLIL::State::S1;
717 else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
718 }
719 auto cell = module->addLut(NEW_ID,
720 driver_lut->getPort(ID::A),
721 y_bit,
722 driver_mask);
723 for (auto &bit : cell->connections_.at(ID::A)) {
724 bit.wire = module->wires_.at(remap_name(bit.wire->name));
725 bit2sinks[bit].push_back(cell);
726 }
727 }
728
729 //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
730 log("ABC RESULTS: input signals: %8d\n", in_wires);
731 log("ABC RESULTS: output signals: %8d\n", out_wires);
732
733 design->remove(mapped_mod);
734 }
735 else
736 {
737 log("Don't call ABC as there is nothing to map.\n");
738 }
739
740 if (cleanup)
741 {
742 log("Removing temp directory.\n");
743 remove_directory(tempdir_name);
744 }
745
746 log_pop();
747 }
748
749 struct Abc9Pass : public Pass {
750 Abc9Pass() : Pass("abc9", "use ABC9 for technology mapping") { }
751 void help() YS_OVERRIDE
752 {
753 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
754 log("\n");
755 log(" abc9 [options] [selection]\n");
756 log("\n");
757 log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
758 log("library to a target architecture.\n");
759 log("\n");
760 log(" -exe <command>\n");
761 #ifdef ABCEXTERNAL
762 log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
763 #else
764 log(" use the specified command instead of \"<yosys-bindir>/yosys-abc\" to execute ABC.\n");
765 #endif
766 log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
767 log("\n");
768 log(" -script <file>\n");
769 log(" use the specified ABC script file instead of the default script.\n");
770 log("\n");
771 log(" if <file> starts with a plus sign (+), then the rest of the filename\n");
772 log(" string is interpreted as the command string to be passed to ABC. The\n");
773 log(" leading plus sign is removed and all commas (,) in the string are\n");
774 log(" replaced with blanks before the string is passed to ABC.\n");
775 log("\n");
776 log(" if no -script parameter is given, the following scripts are used:\n");
777 log("\n");
778 log(" for -lut/-luts (only one LUT size):\n");
779 log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT /*"; lutpack {S}"*/).c_str());
780 log("\n");
781 log(" for -lut/-luts (different LUT sizes):\n");
782 log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT).c_str());
783 log("\n");
784 log(" -fast\n");
785 log(" use different default scripts that are slightly faster (at the cost\n");
786 log(" of output quality):\n");
787 log("\n");
788 log(" for -lut/-luts:\n");
789 log("%s\n", fold_abc9_cmd(ABC_FAST_COMMAND_LUT).c_str());
790 log("\n");
791 log(" -D <picoseconds>\n");
792 log(" set delay target. the string {D} in the default scripts above is\n");
793 log(" replaced by this option when used, and an empty string otherwise\n");
794 log(" (indicating best possible delay).\n");
795 // log(" This also replaces 'dretime' with 'dretime; retime -o {D}' in the\n");
796 // log(" default scripts above.\n");
797 log("\n");
798 // log(" -S <num>\n");
799 // log(" maximum number of LUT inputs shared.\n");
800 // log(" (replaces {S} in the default scripts above, default: -S 1)\n");
801 // log("\n");
802 log(" -lut <width>\n");
803 log(" generate netlist using luts of (max) the specified width.\n");
804 log("\n");
805 log(" -lut <w1>:<w2>\n");
806 log(" generate netlist using luts of (max) the specified width <w2>. All\n");
807 log(" luts with width <= <w1> have constant cost. for luts larger than <w1>\n");
808 log(" the area cost doubles with each additional input bit. the delay cost\n");
809 log(" is still constant for all lut widths.\n");
810 log("\n");
811 log(" -lut <file>\n");
812 log(" pass this file with lut library to ABC.\n");
813 log("\n");
814 log(" -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..\n");
815 log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
816 log(" 2, 3, .. inputs.\n");
817 log("\n");
818 // log(" -dff\n");
819 // log(" also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many\n");
820 // log(" clock domains are automatically partitioned in clock domains and each\n");
821 // log(" domain is passed through ABC independently.\n");
822 // log("\n");
823 // log(" -clk [!]<clock-signal-name>[,[!]<enable-signal-name>]\n");
824 // log(" use only the specified clock domain. this is like -dff, but only FF\n");
825 // log(" cells that belong to the specified clock domain are used.\n");
826 // log("\n");
827 // log(" -keepff\n");
828 // log(" set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
829 // log(" them, for example for equivalence checking.)\n");
830 // log("\n");
831 log(" -nocleanup\n");
832 log(" when this option is used, the temporary files created by this pass\n");
833 log(" are not removed. this is useful for debugging.\n");
834 log("\n");
835 log(" -showtmp\n");
836 log(" print the temp dir name in log. usually this is suppressed so that the\n");
837 log(" command output is identical across runs.\n");
838 log("\n");
839 log(" -markgroups\n");
840 log(" set a 'abcgroup' attribute on all objects created by ABC. The value of\n");
841 log(" this attribute is a unique integer for each ABC process started. This\n");
842 log(" is useful for debugging the partitioning of clock domains.\n");
843 log("\n");
844 log(" -box <file>\n");
845 log(" pass this file with box library to ABC. Use with -lut.\n");
846 log("\n");
847 log("Note that this is a logic optimization pass within Yosys that is calling ABC\n");
848 log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
849 log("ABC on logic snippets extracted from your design. You will not get any useful\n");
850 log("output when passing an ABC script that writes a file. Instead write your full\n");
851 log("design as BLIF file with write_blif and then load that into ABC externally if\n");
852 log("you want to use ABC to convert your design into another format.\n");
853 log("\n");
854 log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
855 log("\n");
856 }
857 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
858 {
859 log_header(design, "Executing ABC9 pass (technology mapping using ABC9).\n");
860 log_push();
861
862 #ifdef ABCEXTERNAL
863 std::string exe_file = ABCEXTERNAL;
864 #else
865 std::string exe_file = proc_self_dirname() + "yosys-abc";
866 #endif
867 std::string script_file, clk_str, box_file, lut_file;
868 std::string delay_target, lutin_shared = "-S 1", wire_delay;
869 bool fast_mode = false, /*dff_mode = false,*/ keepff = false, cleanup = true;
870 bool show_tempdir = false;
871 vector<int> lut_costs;
872 markgroups = false;
873
874 #if 0
875 cleanup = false;
876 show_tempdir = true;
877 #endif
878
879 #ifdef _WIN32
880 #ifndef ABCEXTERNAL
881 if (!check_file_exists(exe_file + ".exe") && check_file_exists(proc_self_dirname() + "..\\yosys-abc.exe"))
882 exe_file = proc_self_dirname() + "..\\yosys-abc";
883 #endif
884 #endif
885
886 size_t argidx;
887 char pwd [PATH_MAX];
888 if (!getcwd(pwd, sizeof(pwd))) {
889 log_cmd_error("getcwd failed: %s\n", strerror(errno));
890 log_abort();
891 }
892 for (argidx = 1; argidx < args.size(); argidx++) {
893 std::string arg = args[argidx];
894 if (arg == "-exe" && argidx+1 < args.size()) {
895 exe_file = args[++argidx];
896 continue;
897 }
898 if (arg == "-script" && argidx+1 < args.size()) {
899 script_file = args[++argidx];
900 rewrite_filename(script_file);
901 if (!script_file.empty() && !is_absolute_path(script_file) && script_file[0] != '+')
902 script_file = std::string(pwd) + "/" + script_file;
903 continue;
904 }
905 if (arg == "-D" && argidx+1 < args.size()) {
906 delay_target = "-D " + args[++argidx];
907 continue;
908 }
909 //if (arg == "-S" && argidx+1 < args.size()) {
910 // lutin_shared = "-S " + args[++argidx];
911 // continue;
912 //}
913 if (arg == "-lut" && argidx+1 < args.size()) {
914 string arg = args[++argidx];
915 size_t pos = arg.find_first_of(':');
916 int lut_mode = 0, lut_mode2 = 0;
917 if (pos != string::npos) {
918 lut_mode = atoi(arg.substr(0, pos).c_str());
919 lut_mode2 = atoi(arg.substr(pos+1).c_str());
920 } else {
921 pos = arg.find_first_of('.');
922 if (pos != string::npos) {
923 lut_file = arg;
924 rewrite_filename(lut_file);
925 if (!lut_file.empty() && !is_absolute_path(lut_file))
926 lut_file = std::string(pwd) + "/" + lut_file;
927 }
928 else {
929 lut_mode = atoi(arg.c_str());
930 lut_mode2 = lut_mode;
931 }
932 }
933 lut_costs.clear();
934 for (int i = 0; i < lut_mode; i++)
935 lut_costs.push_back(1);
936 for (int i = lut_mode; i < lut_mode2; i++)
937 lut_costs.push_back(2 << (i - lut_mode));
938 continue;
939 }
940 if (arg == "-luts" && argidx+1 < args.size()) {
941 lut_costs.clear();
942 for (auto &tok : split_tokens(args[++argidx], ",")) {
943 auto parts = split_tokens(tok, ":");
944 if (GetSize(parts) == 0 && !lut_costs.empty())
945 lut_costs.push_back(lut_costs.back());
946 else if (GetSize(parts) == 1)
947 lut_costs.push_back(atoi(parts.at(0).c_str()));
948 else if (GetSize(parts) == 2)
949 while (GetSize(lut_costs) < atoi(parts.at(0).c_str()))
950 lut_costs.push_back(atoi(parts.at(1).c_str()));
951 else
952 log_cmd_error("Invalid -luts syntax.\n");
953 }
954 continue;
955 }
956 if (arg == "-fast") {
957 fast_mode = true;
958 continue;
959 }
960 //if (arg == "-dff") {
961 // dff_mode = true;
962 // continue;
963 //}
964 //if (arg == "-clk" && argidx+1 < args.size()) {
965 // clk_str = args[++argidx];
966 // dff_mode = true;
967 // continue;
968 //}
969 //if (arg == "-keepff") {
970 // keepff = true;
971 // continue;
972 //}
973 if (arg == "-nocleanup") {
974 cleanup = false;
975 continue;
976 }
977 if (arg == "-showtmp") {
978 show_tempdir = true;
979 continue;
980 }
981 if (arg == "-markgroups") {
982 markgroups = true;
983 continue;
984 }
985 if (arg == "-box" && argidx+1 < args.size()) {
986 box_file = args[++argidx];
987 continue;
988 }
989 if (arg == "-W" && argidx+1 < args.size()) {
990 wire_delay = "-W " + args[++argidx];
991 continue;
992 }
993 break;
994 }
995 extra_args(args, argidx, design);
996
997 // ABC expects a box file for XAIG
998 if (box_file.empty())
999 box_file = "+/dummy.box";
1000
1001 rewrite_filename(box_file);
1002 if (!box_file.empty() && !is_absolute_path(box_file))
1003 box_file = std::string(pwd) + "/" + box_file;
1004
1005 dict<int,IdString> box_lookup;
1006 for (auto m : design->modules()) {
1007 auto it = m->attributes.find(ID(abc9_box_id));
1008 if (it == m->attributes.end())
1009 continue;
1010 if (m->name.begins_with("$paramod"))
1011 continue;
1012 auto id = it->second.as_int();
1013 auto r = box_lookup.insert(std::make_pair(id, m->name));
1014 if (!r.second)
1015 log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
1016 log_id(m), id, log_id(r.first->second));
1017 log_assert(r.second);
1018
1019 RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
1020 for (auto p : m->ports) {
1021 auto w = m->wire(p);
1022 log_assert(w);
1023 if (w->attributes.count(ID(abc9_carry))) {
1024 if (w->port_input) {
1025 if (carry_in)
1026 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
1027 carry_in = w;
1028 }
1029 else if (w->port_output) {
1030 if (carry_out)
1031 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
1032 carry_out = w;
1033 }
1034 }
1035 }
1036 if (carry_in || carry_out) {
1037 if (carry_in && !carry_out)
1038 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
1039 if (!carry_in && carry_out)
1040 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
1041 // Make carry_in the last PI, and carry_out the last PO
1042 // since ABC requires it this way
1043 auto &ports = m->ports;
1044 for (auto it = ports.begin(); it != ports.end(); ) {
1045 RTLIL::Wire* w = m->wire(*it);
1046 log_assert(w);
1047 if (w == carry_in || w == carry_out) {
1048 it = ports.erase(it);
1049 continue;
1050 }
1051 if (w->port_id > carry_in->port_id)
1052 --w->port_id;
1053 if (w->port_id > carry_out->port_id)
1054 --w->port_id;
1055 log_assert(w->port_input || w->port_output);
1056 log_assert(ports[w->port_id-1] == w->name);
1057 ++it;
1058 }
1059 ports.push_back(carry_in->name);
1060 carry_in->port_id = ports.size();
1061 ports.push_back(carry_out->name);
1062 carry_out->port_id = ports.size();
1063 }
1064 }
1065
1066 for (auto module : design->selected_modules())
1067 {
1068 if (module->attributes.count(ID(abc9_box_id)))
1069 continue;
1070
1071 if (module->processes.size() > 0) {
1072 log("Skipping module %s as it contains processes.\n", log_id(module));
1073 continue;
1074 }
1075
1076 SigMap assign_map(module);
1077
1078 CellTypes ct(design);
1079
1080 std::vector<RTLIL::Cell*> all_cells = module->selected_cells();
1081 std::set<RTLIL::Cell*> unassigned_cells(all_cells.begin(), all_cells.end());
1082
1083 std::set<RTLIL::Cell*> expand_queue, next_expand_queue;
1084 std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
1085 std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
1086
1087 std::map<SigSpec, pool<RTLIL::IdString>> assigned_cells;
1088 std::map<RTLIL::Cell*, SigSpec> assigned_cells_reverse;
1089
1090 std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
1091 std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
1092
1093 typedef std::pair<IdString, SigSpec> endomain_t;
1094 std::map<endomain_t, int> mergeability_class;
1095
1096 for (auto cell : all_cells) {
1097 for (auto &conn : cell->connections())
1098 for (auto bit : assign_map(conn.second))
1099 if (bit.wire != nullptr) {
1100 cell_to_bit[cell].insert(bit);
1101 bit_to_cell[bit].insert(cell);
1102 if (ct.cell_input(cell->type, conn.first)) {
1103 cell_to_bit_up[cell].insert(bit);
1104 bit_to_cell_down[bit].insert(cell);
1105 }
1106 if (ct.cell_output(cell->type, conn.first)) {
1107 cell_to_bit_down[cell].insert(bit);
1108 bit_to_cell_up[bit].insert(cell);
1109 }
1110 }
1111
1112 auto inst_module = design->module(cell->type);
1113 if (!inst_module || !inst_module->attributes.count("\\abc9_flop"))
1114 continue;
1115
1116 auto derived_name = inst_module->derive(design, cell->parameters);
1117 auto derived_module = design->module(derived_name);
1118 log_assert(derived_module);
1119 if (derived_module->has_processes())
1120 Pass::call_on_module(design, derived_module, "proc");
1121 SigMap derived_sigmap(derived_module);
1122
1123 SigSpec pattern;
1124 SigSpec with;
1125 for (auto &conn : cell->connections()) {
1126 Wire *first = derived_module->wire(conn.first);
1127 log_assert(first);
1128 SigSpec second = assign_map(conn.second);
1129 log_assert(GetSize(first) == GetSize(second));
1130 pattern.append(first);
1131 with.append(second);
1132 }
1133
1134 Wire *abc9_clock_wire = derived_module->wire("\\$abc9_clock");
1135 if (abc9_clock_wire == NULL)
1136 log_error("'\\$abc9_clock' is not a wire present in module '%s'.\n", log_id(cell->type));
1137 SigSpec abc9_clock = derived_sigmap(abc9_clock_wire);
1138 abc9_clock.replace(pattern, with);
1139 for (const auto &c : abc9_clock.chunks())
1140 log_assert(!c.wire || c.wire->module == module);
1141
1142 Wire *abc9_control_wire = derived_module->wire("\\$abc9_control");
1143 if (abc9_control_wire == NULL)
1144 log_error("'\\$abc9_control' is not a wire present in module '%s'.\n", log_id(cell->type));
1145 SigSpec abc9_control = derived_sigmap(abc9_control_wire);
1146 abc9_control.replace(pattern, with);
1147 for (const auto &c : abc9_control.chunks())
1148 log_assert(!c.wire || c.wire->module == module);
1149
1150 unassigned_cells.erase(cell);
1151 expand_queue.insert(cell);
1152 expand_queue_up.insert(cell);
1153 expand_queue_down.insert(cell);
1154
1155 assigned_cells[abc9_clock].insert(cell->name);
1156 assigned_cells_reverse[cell] = abc9_clock;
1157
1158 endomain_t key(cell->type, abc9_control);
1159 auto r = mergeability_class.emplace(key, mergeability_class.size() + 1);
1160 auto YS_ATTRIBUTE(unused) r2 = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
1161 log_assert(r2.second);
1162 }
1163
1164 while (!expand_queue_up.empty() || !expand_queue_down.empty())
1165 {
1166 if (!expand_queue_up.empty())
1167 {
1168 RTLIL::Cell *cell = *expand_queue_up.begin();
1169 SigSpec key = assigned_cells_reverse.at(cell);
1170 expand_queue_up.erase(cell);
1171
1172 for (auto bit : cell_to_bit_up[cell])
1173 for (auto c : bit_to_cell_up[bit])
1174 if (unassigned_cells.count(c)) {
1175 unassigned_cells.erase(c);
1176 next_expand_queue_up.insert(c);
1177 assigned_cells[key].insert(c->name);
1178 assigned_cells_reverse[c] = key;
1179 expand_queue.insert(c);
1180 }
1181 }
1182
1183 if (!expand_queue_down.empty())
1184 {
1185 RTLIL::Cell *cell = *expand_queue_down.begin();
1186 SigSpec key = assigned_cells_reverse.at(cell);
1187 expand_queue_down.erase(cell);
1188
1189 for (auto bit : cell_to_bit_down[cell])
1190 for (auto c : bit_to_cell_down[bit])
1191 if (unassigned_cells.count(c)) {
1192 unassigned_cells.erase(c);
1193 next_expand_queue_up.insert(c);
1194 assigned_cells[key].insert(c->name);
1195 assigned_cells_reverse[c] = key;
1196 expand_queue.insert(c);
1197 }
1198 }
1199
1200 if (expand_queue_up.empty() && expand_queue_down.empty()) {
1201 expand_queue_up.swap(next_expand_queue_up);
1202 expand_queue_down.swap(next_expand_queue_down);
1203 }
1204 }
1205
1206 while (!expand_queue.empty())
1207 {
1208 RTLIL::Cell *cell = *expand_queue.begin();
1209 SigSpec key = assigned_cells_reverse.at(cell);
1210 expand_queue.erase(cell);
1211
1212 for (auto bit : cell_to_bit.at(cell)) {
1213 for (auto c : bit_to_cell[bit])
1214 if (unassigned_cells.count(c)) {
1215 unassigned_cells.erase(c);
1216 next_expand_queue.insert(c);
1217 assigned_cells[key].insert(c->name);
1218 assigned_cells_reverse[c] = key;
1219 }
1220 bit_to_cell[bit].clear();
1221 }
1222
1223 if (expand_queue.empty())
1224 expand_queue.swap(next_expand_queue);
1225 }
1226
1227 SigSpec key;
1228 for (auto cell : unassigned_cells) {
1229 assigned_cells[key].insert(cell->name);
1230 assigned_cells_reverse[cell] = key;
1231 }
1232
1233 log_header(design, "Summary of detected clock domains:\n");
1234 for (auto &it : assigned_cells)
1235 log(" %d cells in clk=%s\n", GetSize(it.second), log_signal(it.first));
1236
1237 design->selection_stack.emplace_back(false);
1238 design->selected_active_module = module->name.str();
1239 for (auto &it : assigned_cells) {
1240 RTLIL::Selection& sel = design->selection_stack.back();
1241 sel.selected_members[module->name] = std::move(it.second);
1242 abc9_module(design, module, script_file, exe_file, cleanup, lut_costs, false, "$",
1243 keepff, delay_target, lutin_shared, fast_mode, show_tempdir,
1244 box_file, lut_file, wire_delay, box_lookup);
1245 }
1246 design->selection_stack.pop_back();
1247 design->selected_active_module.clear();
1248 }
1249
1250 log_pop();
1251 }
1252 } Abc9Pass;
1253
1254 PRIVATE_NAMESPACE_END