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Merge remote-tracking branch 'origin/master' into xc7mux
[yosys.git] / passes / techmap / abc9.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // [[CITE]] ABC
22 // Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
23 // http://www.eecs.berkeley.edu/~alanmi/abc/
24
25 #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
26 #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p"
27 //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2"
28 #define ABC_COMMAND_LUT "&st; &fraig; &scorr; &dc2; &retime; &dch -f; &if; &mfs"
29 #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}"
30 #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
31
32 #define ABC_FAST_COMMAND_LIB "strash; dretime; map {D}"
33 #define ABC_FAST_COMMAND_CTR "strash; dretime; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
34 #define ABC_FAST_COMMAND_LUT "&st; &retime; &if"
35 #define ABC_FAST_COMMAND_SOP "strash; dretime; cover -I {I} -P {P}"
36 #define ABC_FAST_COMMAND_DFL "strash; dretime; map"
37
38 #include "kernel/register.h"
39 #include "kernel/sigtools.h"
40 #include "kernel/celltypes.h"
41 #include "kernel/cost.h"
42 #include "kernel/log.h"
43 #include <stdlib.h>
44 #include <stdio.h>
45 #include <string.h>
46 #include <cerrno>
47 #include <sstream>
48 #include <climits>
49
50 #ifndef _WIN32
51 # include <unistd.h>
52 # include <dirent.h>
53 #endif
54
55 #include "frontends/aiger/aigerparse.h"
56
57 #ifdef YOSYS_LINK_ABC
58 extern "C" int Abc_RealMain(int argc, char *argv[]);
59 #endif
60
61 USING_YOSYS_NAMESPACE
62 PRIVATE_NAMESPACE_BEGIN
63
64 bool map_mux4;
65 bool map_mux8;
66 bool map_mux16;
67
68 bool markgroups;
69 int map_autoidx;
70 SigMap assign_map;
71 RTLIL::Module *module;
72 std::map<RTLIL::SigBit, int> signal_map;
73 std::map<RTLIL::SigBit, RTLIL::State> signal_init;
74 pool<std::string> enabled_gates;
75 bool recover_init;
76
77 bool clk_polarity, en_polarity;
78 RTLIL::SigSpec clk_sig, en_sig;
79 dict<int, std::string> pi_map, po_map;
80
81 std::string remap_name(RTLIL::IdString abc_name)
82 {
83 std::stringstream sstr;
84 sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1);
85 return sstr.str();
86 }
87
88 void handle_loops(RTLIL::Design *design)
89 {
90 Pass::call(design, "scc -set_attr abc_scc_id {}");
91
92 design->selection_stack.emplace_back(false);
93 RTLIL::Selection& sel = design->selection_stack.back();
94
95 // For every unique SCC found, (arbitrarily) find the first
96 // cell in the component, and select (and mark) all its output
97 // wires
98 pool<RTLIL::Const> ids_seen;
99 for (auto cell : module->cells()) {
100 auto it = cell->attributes.find("\\abc_scc_id");
101 if (it != cell->attributes.end()) {
102 auto r = ids_seen.insert(it->second);
103 if (r.second) {
104 for (const auto &c : cell->connections()) {
105 if (c.second.is_fully_const()) continue;
106 if (cell->output(c.first)) {
107 SigBit b = c.second.as_bit();
108 Wire *w = b.wire;
109 w->set_bool_attribute("\\abc_scc_break");
110 sel.select(module, w);
111 }
112 }
113 }
114 cell->attributes.erase(it);
115 }
116 }
117
118 // Then cut those selected wires to expose them as new PO/PI
119 Pass::call(design, "expose -cut -sep .abc");
120
121 design->selection_stack.pop_back();
122 }
123
124 std::string add_echos_to_abc_cmd(std::string str)
125 {
126 std::string new_str, token;
127 for (size_t i = 0; i < str.size(); i++) {
128 token += str[i];
129 if (str[i] == ';') {
130 while (i+1 < str.size() && str[i+1] == ' ')
131 i++;
132 new_str += "echo + " + token + " " + token + " ";
133 token.clear();
134 }
135 }
136
137 if (!token.empty()) {
138 if (!new_str.empty())
139 new_str += "echo + " + token + "; ";
140 new_str += token;
141 }
142
143 return new_str;
144 }
145
146 std::string fold_abc_cmd(std::string str)
147 {
148 std::string token, new_str = " ";
149 int char_counter = 10;
150
151 for (size_t i = 0; i <= str.size(); i++) {
152 if (i < str.size())
153 token += str[i];
154 if (i == str.size() || str[i] == ';') {
155 if (char_counter + token.size() > 75)
156 new_str += "\n ", char_counter = 14;
157 new_str += token, char_counter += token.size();
158 token.clear();
159 }
160 }
161
162 return new_str;
163 }
164
165 std::string replace_tempdir(std::string text, std::string tempdir_name, bool show_tempdir)
166 {
167 if (show_tempdir)
168 return text;
169
170 while (1) {
171 size_t pos = text.find(tempdir_name);
172 if (pos == std::string::npos)
173 break;
174 text = text.substr(0, pos) + "<abc-temp-dir>" + text.substr(pos + GetSize(tempdir_name));
175 }
176
177 std::string selfdir_name = proc_self_dirname();
178 if (selfdir_name != "/") {
179 while (1) {
180 size_t pos = text.find(selfdir_name);
181 if (pos == std::string::npos)
182 break;
183 text = text.substr(0, pos) + "<yosys-exe-dir>/" + text.substr(pos + GetSize(selfdir_name));
184 }
185 }
186
187 return text;
188 }
189
190 struct abc_output_filter
191 {
192 bool got_cr;
193 int escape_seq_state;
194 std::string linebuf;
195 std::string tempdir_name;
196 bool show_tempdir;
197
198 abc_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir)
199 {
200 got_cr = false;
201 escape_seq_state = 0;
202 }
203
204 void next_char(char ch)
205 {
206 if (escape_seq_state == 0 && ch == '\033') {
207 escape_seq_state = 1;
208 return;
209 }
210 if (escape_seq_state == 1) {
211 escape_seq_state = ch == '[' ? 2 : 0;
212 return;
213 }
214 if (escape_seq_state == 2) {
215 if ((ch < '0' || '9' < ch) && ch != ';')
216 escape_seq_state = 0;
217 return;
218 }
219 escape_seq_state = 0;
220 if (ch == '\r') {
221 got_cr = true;
222 return;
223 }
224 if (ch == '\n') {
225 log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir).c_str());
226 got_cr = false, linebuf.clear();
227 return;
228 }
229 if (got_cr)
230 got_cr = false, linebuf.clear();
231 linebuf += ch;
232 }
233
234 void next_line(const std::string &line)
235 {
236 int pi, po;
237 if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
238 log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
239 pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???",
240 po, po_map.count(po) ? po_map.at(po).c_str() : "???");
241 return;
242 }
243
244 for (char ch : line)
245 next_char(ch);
246 }
247 };
248
249 static std::pair<RTLIL::IdString, int> wideports_split(std::string name)
250 {
251 int pos = -1;
252
253 if (name.empty() || name.back() != ']')
254 goto failed;
255
256 for (int i = 0; i+1 < GetSize(name); i++) {
257 if (name[i] == '[')
258 pos = i;
259 else if (name[i] < '0' || name[i] > '9')
260 pos = -1;
261 else if (i == pos+1 && name[i] == '0' && name[i+1] != ']')
262 pos = -1;
263 }
264
265 if (pos >= 0)
266 return std::pair<RTLIL::IdString, int>(RTLIL::escape_id(name.substr(0, pos)), atoi(name.c_str() + pos+1));
267
268 failed:
269 return std::pair<RTLIL::IdString, int>(name, 0);
270 }
271
272 void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
273 std::string liberty_file, std::string constr_file, bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
274 bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode,
275 const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, std::string box_file, std::string lut_file)
276 {
277 module = current_module;
278 map_autoidx = autoidx++;
279
280 signal_map.clear();
281 pi_map.clear();
282 po_map.clear();
283 recover_init = false;
284
285 if (clk_str != "$")
286 {
287 clk_polarity = true;
288 clk_sig = RTLIL::SigSpec();
289
290 en_polarity = true;
291 en_sig = RTLIL::SigSpec();
292 }
293
294 if (!clk_str.empty() && clk_str != "$")
295 {
296 if (clk_str.find(',') != std::string::npos) {
297 int pos = clk_str.find(',');
298 std::string en_str = clk_str.substr(pos+1);
299 clk_str = clk_str.substr(0, pos);
300 if (en_str[0] == '!') {
301 en_polarity = false;
302 en_str = en_str.substr(1);
303 }
304 if (module->wires_.count(RTLIL::escape_id(en_str)) != 0)
305 en_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(en_str)), 0));
306 }
307 if (clk_str[0] == '!') {
308 clk_polarity = false;
309 clk_str = clk_str.substr(1);
310 }
311 if (module->wires_.count(RTLIL::escape_id(clk_str)) != 0)
312 clk_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(clk_str)), 0));
313 }
314
315 if (dff_mode && clk_sig.empty())
316 log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
317
318 std::string tempdir_name = "/tmp/yosys-abc-XXXXXX";
319 if (!cleanup)
320 tempdir_name[0] = tempdir_name[4] = '_';
321 tempdir_name = make_temp_dir(tempdir_name);
322 log_header(design, "Extracting gate netlist of module `%s' to `%s/input.aig'..\n",
323 module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
324
325 std::string abc_script = stringf("read %s/input.aig; &get -n; ", tempdir_name.c_str());
326
327 if (!liberty_file.empty()) {
328 abc_script += stringf("read_lib -w %s; ", liberty_file.c_str());
329 if (!constr_file.empty())
330 abc_script += stringf("read_constr -v %s; ", constr_file.c_str());
331 } else
332 if (!lut_costs.empty()) {
333 abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
334 if (!box_file.empty())
335 abc_script += stringf("read_box -v %s; ", box_file.c_str());
336 }
337 else
338 if (!lut_file.empty()) {
339 abc_script += stringf("read_lut %s; ", lut_file.c_str());
340 if (!box_file.empty())
341 abc_script += stringf("read_box -v %s; ", box_file.c_str());
342 }
343 else
344 abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str());
345
346 if (!script_file.empty()) {
347 if (script_file[0] == '+') {
348 for (size_t i = 1; i < script_file.size(); i++)
349 if (script_file[i] == '\'')
350 abc_script += "'\\''";
351 else if (script_file[i] == ',')
352 abc_script += " ";
353 else
354 abc_script += script_file[i];
355 } else
356 abc_script += stringf("source %s", script_file.c_str());
357 } else if (!lut_costs.empty() || !lut_file.empty()) {
358 //bool all_luts_cost_same = true;
359 //for (int this_cost : lut_costs)
360 // if (this_cost != lut_costs.front())
361 // all_luts_cost_same = false;
362 abc_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
363 //if (all_luts_cost_same && !fast_mode)
364 // abc_script += "; lutpack {S}";
365 } else if (!liberty_file.empty())
366 abc_script += constr_file.empty() ? (fast_mode ? ABC_FAST_COMMAND_LIB : ABC_COMMAND_LIB) : (fast_mode ? ABC_FAST_COMMAND_CTR : ABC_COMMAND_CTR);
367 else if (sop_mode)
368 abc_script += fast_mode ? ABC_FAST_COMMAND_SOP : ABC_COMMAND_SOP;
369 else
370 abc_script += fast_mode ? ABC_FAST_COMMAND_DFL : ABC_COMMAND_DFL;
371
372 if (script_file.empty() && !delay_target.empty())
373 for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1))
374 abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8);
375
376 for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
377 abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);
378
379 for (size_t pos = abc_script.find("{I}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
380 abc_script = abc_script.substr(0, pos) + sop_inputs + abc_script.substr(pos+3);
381
382 for (size_t pos = abc_script.find("{P}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
383 abc_script = abc_script.substr(0, pos) + sop_products + abc_script.substr(pos+3);
384
385 for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
386 abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
387
388 abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
389 abc_script = add_echos_to_abc_cmd(abc_script);
390
391 for (size_t i = 0; i+1 < abc_script.size(); i++)
392 if (abc_script[i] == ';' && abc_script[i+1] == ' ')
393 abc_script[i+1] = '\n';
394
395 FILE *f = fopen(stringf("%s/abc.script", tempdir_name.c_str()).c_str(), "wt");
396 fprintf(f, "%s\n", abc_script.c_str());
397 fclose(f);
398
399 if (dff_mode || !clk_str.empty())
400 {
401 if (clk_sig.size() == 0)
402 log("No%s clock domain found. Not extracting any FF cells.\n", clk_str.empty() ? "" : " matching");
403 else {
404 log("Found%s %s clock domain: %s", clk_str.empty() ? "" : " matching", clk_polarity ? "posedge" : "negedge", log_signal(clk_sig));
405 if (en_sig.size() != 0)
406 log(", enabled by %s%s", en_polarity ? "" : "!", log_signal(en_sig));
407 log("\n");
408 }
409 }
410
411 design->selection_stack.emplace_back(false);
412 RTLIL::Selection& sel = design->selection_stack.back();
413 sel.select(module);
414
415 // Adopt same behaviour as abc
416 // TODO: How to specify don't-care to abc9?
417 Pass::call(design, "setundef -zero");
418
419 Pass::call(design, "aigmap");
420
421 handle_loops(design);
422
423 Pass::call(design, stringf("write_xaiger -O -symbols %s/input.aig; ", tempdir_name.c_str()));
424
425 design->selection_stack.pop_back();
426
427 // Now 'unexpose' those wires by undoing
428 // the expose operation -- remove them from PO/PI
429 // and re-connecting them back together
430 for (auto wire : module->wires()) {
431 auto it = wire->attributes.find("\\abc_scc_break");
432 if (it != wire->attributes.end()) {
433 wire->attributes.erase(it);
434 log_assert(wire->port_output);
435 wire->port_output = false;
436 RTLIL::Wire *i_wire = module->wire(wire->name.str() + ".abci");
437 log_assert(i_wire);
438 log_assert(i_wire->port_input);
439 i_wire->port_input = false;
440 module->connect(i_wire, wire);
441 }
442 }
443 module->fixup_ports();
444
445 //log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
446 // count_gates, GetSize(signal_list), count_input, count_output);
447
448 log_push();
449
450 //if (count_output > 0)
451 {
452 log_header(design, "Executing ABC9.\n");
453
454 std::string buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str());
455 f = fopen(buffer.c_str(), "wt");
456 if (f == NULL)
457 log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
458 fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
459 fprintf(f, "GATE ONE 1 Y=CONST1;\n");
460 fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_BUF_"));
461 fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOT_"));
462 if (enabled_gates.empty() || enabled_gates.count("AND"))
463 fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_AND_"));
464 if (enabled_gates.empty() || enabled_gates.count("NAND"))
465 fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NAND_"));
466 if (enabled_gates.empty() || enabled_gates.count("OR"))
467 fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_OR_"));
468 if (enabled_gates.empty() || enabled_gates.count("NOR"))
469 fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOR_"));
470 if (enabled_gates.empty() || enabled_gates.count("XOR"))
471 fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XOR_"));
472 if (enabled_gates.empty() || enabled_gates.count("XNOR"))
473 fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XNOR_"));
474 if (enabled_gates.empty() || enabled_gates.count("ANDNOT"))
475 fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_ANDNOT_"));
476 if (enabled_gates.empty() || enabled_gates.count("ORNOT"))
477 fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_ORNOT_"));
478 if (enabled_gates.empty() || enabled_gates.count("AOI3"))
479 fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI3_"));
480 if (enabled_gates.empty() || enabled_gates.count("OAI3"))
481 fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI3_"));
482 if (enabled_gates.empty() || enabled_gates.count("AOI4"))
483 fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI4_"));
484 if (enabled_gates.empty() || enabled_gates.count("OAI4"))
485 fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI4_"));
486 if (enabled_gates.empty() || enabled_gates.count("MUX"))
487 fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_MUX_"));
488 if (map_mux4)
489 fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*get_cell_cost("$_MUX_"));
490 if (map_mux8)
491 fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*get_cell_cost("$_MUX_"));
492 if (map_mux16)
493 fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*get_cell_cost("$_MUX_"));
494 fclose(f);
495
496 if (!lut_costs.empty()) {
497 buffer = stringf("%s/lutdefs.txt", tempdir_name.c_str());
498 f = fopen(buffer.c_str(), "wt");
499 if (f == NULL)
500 log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
501 for (int i = 0; i < GetSize(lut_costs); i++)
502 fprintf(f, "%d %d.00 1.00\n", i+1, lut_costs.at(i));
503 fclose(f);
504 }
505
506 buffer = stringf("%s -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
507 log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
508
509 #ifndef YOSYS_LINK_ABC
510 abc_output_filter filt(tempdir_name, show_tempdir);
511 int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1));
512 #else
513 // These needs to be mutable, supposedly due to getopt
514 char *abc_argv[5];
515 string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str());
516 abc_argv[0] = strdup(exe_file.c_str());
517 abc_argv[1] = strdup("-s");
518 abc_argv[2] = strdup("-f");
519 abc_argv[3] = strdup(tmp_script_name.c_str());
520 abc_argv[4] = 0;
521 int ret = Abc_RealMain(4, abc_argv);
522 free(abc_argv[0]);
523 free(abc_argv[1]);
524 free(abc_argv[2]);
525 free(abc_argv[3]);
526 #endif
527 if (ret != 0)
528 log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
529
530 buffer = stringf("%s/%s", tempdir_name.c_str(), "output.aig");
531 std::ifstream ifs;
532 ifs.open(buffer);
533 if (ifs.fail())
534 log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
535
536 bool builtin_lib = liberty_file.empty();
537 RTLIL::Design *mapped_design = new RTLIL::Design;
538 //parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
539 AigerReader reader(mapped_design, ifs, "\\netlist", "" /* clk_name */, "" /* map_filename */, true /* wideports */);
540 reader.parse_xaiger();
541
542 ifs.close();
543
544 log_header(design, "Re-integrating ABC9 results.\n");
545 RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"];
546 if (mapped_mod == NULL)
547 log_error("ABC output file does not contain a module `netlist'.\n");
548
549 pool<RTLIL::SigBit> output_bits;
550 for (auto &it : mapped_mod->wires_) {
551 RTLIL::Wire *w = it.second;
552 RTLIL::Wire *remap_wire = module->addWire(remap_name(w->name), GetSize(w));
553 if (markgroups) remap_wire->attributes["\\abcgroup"] = map_autoidx;
554 if (w->port_output) {
555 RTLIL::Wire *wire = module->wire(w->name);
556 if (wire) {
557 for (int i = 0; i < GetSize(wire); i++)
558 output_bits.insert({wire, i});
559 }
560 else {
561 if (w->name.str() == "\\__dummy_o__") {
562 log("Don't call ABC as there is nothing to map.\n");
563 goto cleanup;
564 }
565
566 // Attempt another wideports_split here because there
567 // exists the possibility that different bits of a port
568 // could be an input and output, therefore parse_xiager()
569 // could not combine it into a wideport
570 auto r = wideports_split(w->name.str());
571 wire = module->wire(r.first);
572 log_assert(wire);
573 int i = r.second;
574 output_bits.insert({wire, i});
575 }
576 }
577 }
578
579 std::map<std::string, int> cell_stats;
580 for (auto c : mapped_mod->cells())
581 {
582 if (builtin_lib)
583 {
584 if (c->type == "$_NOT_") {
585 RTLIL::Cell *cell;
586 RTLIL::SigBit a_bit = c->getPort("\\A").as_bit();
587 RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit();
588 if (!lut_costs.empty() || !lut_file.empty()) {
589 // ABC can return NOT gates that drive POs
590 if (a_bit.wire->port_input) {
591 // If it's a NOT gate that comes from a primary input directly
592 // then implement it using a LUT
593 cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())),
594 RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset),
595 RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
596 1);
597 }
598 else {
599 // Otherwise, clone the driving LUT to guarantee that we
600 // won't increase the max logic depth
601 // (TODO: Optimise by not cloning unless will increase depth)
602 RTLIL::IdString driver_name;
603 if (GetSize(a_bit.wire) == 1)
604 driver_name = stringf("%s$lut", a_bit.wire->name.c_str());
605 else
606 driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset);
607 RTLIL::Cell* driver = mapped_mod->cell(driver_name);
608 log_assert(driver);
609 auto driver_a = driver->getPort("\\A").chunks();
610 for (auto &chunk : driver_a)
611 chunk.wire = module->wires_[remap_name(chunk.wire->name)];
612 RTLIL::Const driver_lut = driver->getParam("\\LUT");
613 for (auto &b : driver_lut.bits) {
614 if (b == RTLIL::State::S0) b = RTLIL::State::S1;
615 else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
616 }
617 cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())),
618 driver_a,
619 RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
620 driver_lut);
621 }
622 cell_stats["$lut"]++;
623 }
624 else {
625 cell = module->addCell(remap_name(c->name), "$_NOT_");
626 cell->setPort("\\A", RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset));
627 cell->setPort("\\Y", RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset));
628 cell_stats[RTLIL::unescape_id(c->type)]++;
629 }
630 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
631 continue;
632 }
633
634 cell_stats[RTLIL::unescape_id(c->type)]++;
635 if (c->type == "\\ZERO" || c->type == "\\ONE") {
636 RTLIL::SigSig conn;
637 conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]);
638 conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1);
639 module->connect(conn);
640 continue;
641 }
642 if (c->type == "\\BUF") {
643 RTLIL::SigSig conn;
644 conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]);
645 conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]);
646 module->connect(conn);
647 continue;
648 }
649
650 if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR" || c->type == "\\NAND" || c->type == "\\NOR" ||
651 c->type == "\\XNOR" || c->type == "\\ANDNOT" || c->type == "\\ORNOT") {
652 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
653 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
654 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
655 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
656 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
657 continue;
658 }
659 if (c->type == "\\MUX") {
660 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_");
661 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
662 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
663 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
664 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
665 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
666 continue;
667 }
668 if (c->type == "\\MUX4") {
669 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX4_");
670 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
671 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
672 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
673 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
674 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
675 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
676 cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
677 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
678 continue;
679 }
680 if (c->type == "\\MUX8") {
681 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX8_");
682 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
683 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
684 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
685 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
686 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
687 cell->setPort("\\E", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\E").as_wire()->name)]));
688 cell->setPort("\\F", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\F").as_wire()->name)]));
689 cell->setPort("\\G", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\G").as_wire()->name)]));
690 cell->setPort("\\H", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\H").as_wire()->name)]));
691 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
692 cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
693 cell->setPort("\\U", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\U").as_wire()->name)]));
694 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
695 continue;
696 }
697 if (c->type == "\\MUX16") {
698 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX16_");
699 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
700 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
701 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
702 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
703 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
704 cell->setPort("\\E", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\E").as_wire()->name)]));
705 cell->setPort("\\F", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\F").as_wire()->name)]));
706 cell->setPort("\\G", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\G").as_wire()->name)]));
707 cell->setPort("\\H", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\H").as_wire()->name)]));
708 cell->setPort("\\I", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\I").as_wire()->name)]));
709 cell->setPort("\\J", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\J").as_wire()->name)]));
710 cell->setPort("\\K", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\K").as_wire()->name)]));
711 cell->setPort("\\L", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\L").as_wire()->name)]));
712 cell->setPort("\\M", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\M").as_wire()->name)]));
713 cell->setPort("\\N", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\N").as_wire()->name)]));
714 cell->setPort("\\O", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\O").as_wire()->name)]));
715 cell->setPort("\\P", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\P").as_wire()->name)]));
716 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
717 cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
718 cell->setPort("\\U", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\U").as_wire()->name)]));
719 cell->setPort("\\V", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\V").as_wire()->name)]));
720 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
721 continue;
722 }
723 if (c->type == "\\AOI3" || c->type == "\\OAI3") {
724 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
725 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
726 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
727 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
728 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
729 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
730 continue;
731 }
732 if (c->type == "\\AOI4" || c->type == "\\OAI4") {
733 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
734 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
735 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
736 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
737 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
738 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
739 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
740 continue;
741 }
742 if (c->type == "\\DFF") {
743 log_assert(clk_sig.size() == 1);
744 RTLIL::Cell *cell;
745 if (en_sig.size() == 0) {
746 cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
747 } else {
748 log_assert(en_sig.size() == 1);
749 cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
750 cell->setPort("\\E", en_sig);
751 }
752 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
753 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
754 cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
755 cell->setPort("\\C", clk_sig);
756 continue;
757 }
758 }
759 else
760 cell_stats[RTLIL::unescape_id(c->type)]++;
761
762 if (c->type == "\\_const0_" || c->type == "\\_const1_") {
763 RTLIL::SigSig conn;
764 conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->connections().begin()->second.as_wire()->name)]);
765 conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1);
766 module->connect(conn);
767 continue;
768 }
769
770 if (c->type == "\\_dff_") {
771 log_assert(clk_sig.size() == 1);
772 RTLIL::Cell *cell;
773 if (en_sig.size() == 0) {
774 cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
775 } else {
776 log_assert(en_sig.size() == 1);
777 cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
778 cell->setPort("\\E", en_sig);
779 }
780 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
781 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
782 cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
783 cell->setPort("\\C", clk_sig);
784 continue;
785 }
786
787 if (c->type == "$lut" && GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) {
788 SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)];
789 SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)];
790 module->connect(my_y, my_a);
791 continue;
792 }
793
794 RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
795 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
796 cell->parameters = c->parameters;
797 for (auto &conn : c->connections()) {
798 RTLIL::SigSpec newsig;
799 for (auto c : conn.second.chunks()) {
800 if (c.width == 0)
801 continue;
802 //log_assert(c.width == 1);
803 c.wire = module->wires_[remap_name(c.wire->name)];
804 newsig.append(c);
805 }
806 cell->setPort(conn.first, newsig);
807 }
808 }
809
810 // Copy connections (and rename) from mapped_mod to module
811 for (auto conn : mapped_mod->connections()) {
812 if (!conn.first.is_fully_const()) {
813 auto chunks = conn.first.chunks();
814 for (auto &c : chunks)
815 c.wire = module->wires_[remap_name(c.wire->name)];
816 conn.first = std::move(chunks);
817 }
818 if (!conn.second.is_fully_const()) {
819 auto chunks = conn.second.chunks();
820 for (auto &c : chunks)
821 if (c.wire)
822 c.wire = module->wires_[remap_name(c.wire->name)];
823 conn.second = std::move(chunks);
824 }
825 module->connect(conn);
826 }
827
828 if (recover_init)
829 for (auto wire : mapped_mod->wires()) {
830 if (wire->attributes.count("\\init")) {
831 Wire *w = module->wires_[remap_name(wire->name)];
832 log_assert(w->attributes.count("\\init") == 0);
833 w->attributes["\\init"] = wire->attributes.at("\\init");
834 }
835 }
836
837 for (auto &it : cell_stats)
838 log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
839 int in_wires = 0, out_wires = 0;
840 //for (auto &si : signal_list)
841 // if (si.is_port) {
842 // char buffer[100];
843 // snprintf(buffer, 100, "\\n%d", si.id);
844 // RTLIL::SigSig conn;
845 // if (si.type != G(NONE)) {
846 // conn.first = si.bit;
847 // conn.second = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
848 // out_wires++;
849 // } else {
850 // conn.first = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
851 // conn.second = si.bit;
852 // in_wires++;
853 // }
854 // module->connect(conn);
855 // }
856
857 // Go through all AND and NOT output connections,
858 // and for those output ports driving wires
859 // also driven by mapped_mod, disconnect them
860 for (auto cell : module->cells()) {
861 if (!cell->type.in("$_AND_", "$_NOT_"))
862 continue;
863 for (auto &it : cell->connections_) {
864 auto port_name = it.first;
865 if (!cell->output(port_name)) continue;
866 auto &signal = it.second;
867 auto bits = signal.bits();
868 for (auto &b : bits)
869 if (output_bits.count(b))
870 b = module->addWire(NEW_ID);
871 signal = std::move(bits);
872 }
873 }
874 // Do the same for module connections
875 for (auto &it : module->connections_) {
876 auto &signal = it.first;
877 auto bits = signal.bits();
878 for (auto &b : bits)
879 if (output_bits.count(b))
880 b = module->addWire(NEW_ID);
881 signal = std::move(bits);
882 }
883
884 // Stitch in mapped_mod's inputs/outputs into module
885 for (auto &it : mapped_mod->wires_) {
886 RTLIL::Wire *w = it.second;
887 if (!w->port_input && !w->port_output)
888 continue;
889 RTLIL::Wire *wire = module->wire(w->name);
890 RTLIL::Wire *remap_wire = module->wire(remap_name(w->name));
891 RTLIL::SigSpec signal;
892 if (wire) {
893 signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
894 }
895 else {
896 // Attempt another wideports_split here because there
897 // exists the possibility that different bits of a port
898 // could be an input and output, therefore parse_xiager()
899 // could not combine it into a wideport
900 auto r = wideports_split(w->name.str());
901 wire = module->wire(r.first);
902 log_assert(wire);
903 int i = r.second;
904 signal = RTLIL::SigSpec(wire, i);
905 }
906 log_assert(GetSize(signal) >= GetSize(remap_wire));
907
908 log_assert(w->port_input || w->port_output);
909 RTLIL::SigSig conn;
910 if (w->port_input) {
911 conn.first = remap_wire;
912 conn.second = signal;
913 in_wires++;
914 module->connect(conn);
915 }
916 if (w->port_output) {
917 conn.first = signal;
918 conn.second = remap_wire;
919 out_wires++;
920 module->connect(conn);
921 }
922 }
923
924 //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
925 log("ABC RESULTS: input signals: %8d\n", in_wires);
926 log("ABC RESULTS: output signals: %8d\n", out_wires);
927
928 delete mapped_design;
929 }
930 //else
931 //{
932 // log("Don't call ABC as there is nothing to map.\n");
933 //}
934
935 cleanup:
936 if (cleanup)
937 {
938 log("Removing temp directory.\n");
939 remove_directory(tempdir_name);
940 }
941
942 log_pop();
943 }
944
945 struct Abc9Pass : public Pass {
946 Abc9Pass() : Pass("abc9", "use ABC for technology mapping") { }
947 void help() YS_OVERRIDE
948 {
949 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
950 log("\n");
951 log(" abc9 [options] [selection]\n");
952 log("\n");
953 log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
954 log("library to a target architecture.\n");
955 log("\n");
956 log(" -exe <command>\n");
957 #ifdef ABCEXTERNAL
958 log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
959 #else
960 log(" use the specified command instead of \"<yosys-bindir>/yosys-abc\" to execute ABC.\n");
961 #endif
962 log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
963 log("\n");
964 log(" -script <file>\n");
965 log(" use the specified ABC script file instead of the default script.\n");
966 log("\n");
967 log(" if <file> starts with a plus sign (+), then the rest of the filename\n");
968 log(" string is interpreted as the command string to be passed to ABC. The\n");
969 log(" leading plus sign is removed and all commas (,) in the string are\n");
970 log(" replaced with blanks before the string is passed to ABC.\n");
971 log("\n");
972 log(" if no -script parameter is given, the following scripts are used:\n");
973 log("\n");
974 log(" for -liberty without -constr:\n");
975 log("%s\n", fold_abc_cmd(ABC_COMMAND_LIB).c_str());
976 log("\n");
977 log(" for -liberty with -constr:\n");
978 log("%s\n", fold_abc_cmd(ABC_COMMAND_CTR).c_str());
979 log("\n");
980 log(" for -lut/-luts (only one LUT size):\n");
981 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT "; lutpack {S}").c_str());
982 log("\n");
983 log(" for -lut/-luts (different LUT sizes):\n");
984 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT).c_str());
985 log("\n");
986 log(" for -sop:\n");
987 log("%s\n", fold_abc_cmd(ABC_COMMAND_SOP).c_str());
988 log("\n");
989 log(" otherwise:\n");
990 log("%s\n", fold_abc_cmd(ABC_COMMAND_DFL).c_str());
991 log("\n");
992 log(" -fast\n");
993 log(" use different default scripts that are slightly faster (at the cost\n");
994 log(" of output quality):\n");
995 log("\n");
996 log(" for -liberty without -constr:\n");
997 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LIB).c_str());
998 log("\n");
999 log(" for -liberty with -constr:\n");
1000 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_CTR).c_str());
1001 log("\n");
1002 log(" for -lut/-luts:\n");
1003 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT).c_str());
1004 log("\n");
1005 log(" for -sop:\n");
1006 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_SOP).c_str());
1007 log("\n");
1008 log(" otherwise:\n");
1009 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_DFL).c_str());
1010 log("\n");
1011 log(" -liberty <file>\n");
1012 log(" generate netlists for the specified cell library (using the liberty\n");
1013 log(" file format).\n");
1014 log("\n");
1015 log(" -constr <file>\n");
1016 log(" pass this file with timing constraints to ABC. Use with -liberty.\n");
1017 log("\n");
1018 log(" a constr file contains two lines:\n");
1019 log(" set_driving_cell <cell_name>\n");
1020 log(" set_load <floating_point_number>\n");
1021 log("\n");
1022 log(" the set_driving_cell statement defines which cell type is assumed to\n");
1023 log(" drive the primary inputs and the set_load statement sets the load in\n");
1024 log(" femtofarads for each primary output.\n");
1025 log("\n");
1026 log(" -D <picoseconds>\n");
1027 log(" set delay target. the string {D} in the default scripts above is\n");
1028 log(" replaced by this option when used, and an empty string otherwise.\n");
1029 log(" this also replaces 'dretime' with 'dretime; retime -o {D}' in the\n");
1030 log(" default scripts above.\n");
1031 log("\n");
1032 log(" -I <num>\n");
1033 log(" maximum number of SOP inputs.\n");
1034 log(" (replaces {I} in the default scripts above)\n");
1035 log("\n");
1036 log(" -P <num>\n");
1037 log(" maximum number of SOP products.\n");
1038 log(" (replaces {P} in the default scripts above)\n");
1039 log("\n");
1040 log(" -S <num>\n");
1041 log(" maximum number of LUT inputs shared.\n");
1042 log(" (replaces {S} in the default scripts above, default: -S 1)\n");
1043 log("\n");
1044 log(" -lut <width>\n");
1045 log(" generate netlist using luts of (max) the specified width.\n");
1046 log("\n");
1047 log(" -lut <w1>:<w2>\n");
1048 log(" generate netlist using luts of (max) the specified width <w2>. All\n");
1049 log(" luts with width <= <w1> have constant cost. for luts larger than <w1>\n");
1050 log(" the area cost doubles with each additional input bit. the delay cost\n");
1051 log(" is still constant for all lut widths.\n");
1052 log("\n");
1053 log(" -lut <file>\n");
1054 log(" pass this file with lut library to ABC.\n");
1055 log("\n");
1056 log(" -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..\n");
1057 log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
1058 log(" 2, 3, .. inputs.\n");
1059 log("\n");
1060 log(" -sop\n");
1061 log(" map to sum-of-product cells and inverters\n");
1062 log("\n");
1063 // log(" -mux4, -mux8, -mux16\n");
1064 // log(" try to extract 4-input, 8-input, and/or 16-input muxes\n");
1065 // log(" (ignored when used with -liberty or -lut)\n");
1066 // log("\n");
1067 log(" -g type1,type2,...\n");
1068 log(" Map to the specified list of gate types. Supported gates types are:\n");
1069 log(" AND, NAND, OR, NOR, XOR, XNOR, ANDNOT, ORNOT, MUX, AOI3, OAI3, AOI4, OAI4.\n");
1070 log(" (The NOT gate is always added to this list automatically.)\n");
1071 log("\n");
1072 log(" The following aliases can be used to reference common sets of gate types:\n");
1073 log(" simple: AND OR XOR MUX\n");
1074 log(" cmos2: NAND NOR\n");
1075 log(" cmos3: NAND NOR AOI3 OAI3\n");
1076 log(" cmos4: NAND NOR AOI3 OAI3 AOI4 OAI4\n");
1077 log(" gates: AND NAND OR NOR XOR XNOR ANDNOT ORNOT\n");
1078 log(" aig: AND NAND OR NOR ANDNOT ORNOT\n");
1079 log("\n");
1080 log(" Prefix a gate type with a '-' to remove it from the list. For example\n");
1081 log(" the arguments 'AND,OR,XOR' and 'simple,-MUX' are equivalent.\n");
1082 log("\n");
1083 log(" -dff\n");
1084 log(" also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many\n");
1085 log(" clock domains are automatically partitioned in clock domains and each\n");
1086 log(" domain is passed through ABC independently.\n");
1087 log("\n");
1088 log(" -clk [!]<clock-signal-name>[,[!]<enable-signal-name>]\n");
1089 log(" use only the specified clock domain. this is like -dff, but only FF\n");
1090 log(" cells that belong to the specified clock domain are used.\n");
1091 log("\n");
1092 log(" -keepff\n");
1093 log(" set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
1094 log(" them, for example for equivalence checking.)\n");
1095 log("\n");
1096 log(" -nocleanup\n");
1097 log(" when this option is used, the temporary files created by this pass\n");
1098 log(" are not removed. this is useful for debugging.\n");
1099 log("\n");
1100 log(" -showtmp\n");
1101 log(" print the temp dir name in log. usually this is suppressed so that the\n");
1102 log(" command output is identical across runs.\n");
1103 log("\n");
1104 log(" -markgroups\n");
1105 log(" set a 'abcgroup' attribute on all objects created by ABC. The value of\n");
1106 log(" this attribute is a unique integer for each ABC process started. This\n");
1107 log(" is useful for debugging the partitioning of clock domains.\n");
1108 log("\n");
1109 log(" -box <file>\n");
1110 log(" pass this file with box library to ABC. Use with -lut.\n");
1111 log("\n");
1112 log("When neither -liberty nor -lut is used, the Yosys standard cell library is\n");
1113 log("loaded into ABC before the ABC script is executed.\n");
1114 log("\n");
1115 log("Note that this is a logic optimization pass within Yosys that is calling ABC\n");
1116 log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
1117 log("ABC on logic snippets extracted from your design. You will not get any useful\n");
1118 log("output when passing an ABC script that writes a file. Instead write your full\n");
1119 log("design as BLIF file with write_blif and the load that into ABC externally if\n");
1120 log("you want to use ABC to convert your design into another format.\n");
1121 log("\n");
1122 log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
1123 log("\n");
1124 }
1125 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1126 {
1127 log_header(design, "Executing ABC9 pass (technology mapping using ABC).\n");
1128 log_push();
1129
1130 assign_map.clear();
1131 signal_map.clear();
1132 signal_init.clear();
1133 pi_map.clear();
1134 po_map.clear();
1135
1136 #ifdef ABCEXTERNAL
1137 std::string exe_file = ABCEXTERNAL;
1138 #else
1139 std::string exe_file = proc_self_dirname() + "yosys-abc";
1140 #endif
1141 std::string script_file, liberty_file, constr_file, clk_str, box_file, lut_file;
1142 std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1";
1143 bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
1144 bool show_tempdir = false, sop_mode = false;
1145 vector<int> lut_costs;
1146 markgroups = false;
1147
1148 map_mux4 = false;
1149 map_mux8 = false;
1150 map_mux16 = false;
1151 enabled_gates.clear();
1152
1153 #ifdef _WIN32
1154 #ifndef ABCEXTERNAL
1155 if (!check_file_exists(exe_file + ".exe") && check_file_exists(proc_self_dirname() + "..\\yosys-abc.exe"))
1156 exe_file = proc_self_dirname() + "..\\yosys-abc";
1157 #endif
1158 #endif
1159
1160 size_t argidx;
1161 char pwd [PATH_MAX];
1162 if (!getcwd(pwd, sizeof(pwd))) {
1163 log_cmd_error("getcwd failed: %s\n", strerror(errno));
1164 log_abort();
1165 }
1166 for (argidx = 1; argidx < args.size(); argidx++) {
1167 std::string arg = args[argidx];
1168 if (arg == "-exe" && argidx+1 < args.size()) {
1169 exe_file = args[++argidx];
1170 continue;
1171 }
1172 if (arg == "-script" && argidx+1 < args.size()) {
1173 script_file = args[++argidx];
1174 rewrite_filename(script_file);
1175 if (!script_file.empty() && !is_absolute_path(script_file) && script_file[0] != '+')
1176 script_file = std::string(pwd) + "/" + script_file;
1177 continue;
1178 }
1179 if (arg == "-liberty" && argidx+1 < args.size()) {
1180 liberty_file = args[++argidx];
1181 rewrite_filename(liberty_file);
1182 if (!liberty_file.empty() && !is_absolute_path(liberty_file))
1183 liberty_file = std::string(pwd) + "/" + liberty_file;
1184 continue;
1185 }
1186 if (arg == "-constr" && argidx+1 < args.size()) {
1187 constr_file = args[++argidx];
1188 rewrite_filename(constr_file);
1189 if (!constr_file.empty() && !is_absolute_path(constr_file))
1190 constr_file = std::string(pwd) + "/" + constr_file;
1191 continue;
1192 }
1193 if (arg == "-D" && argidx+1 < args.size()) {
1194 delay_target = "-D " + args[++argidx];
1195 continue;
1196 }
1197 if (arg == "-I" && argidx+1 < args.size()) {
1198 sop_inputs = "-I " + args[++argidx];
1199 continue;
1200 }
1201 if (arg == "-P" && argidx+1 < args.size()) {
1202 sop_products = "-P " + args[++argidx];
1203 continue;
1204 }
1205 if (arg == "-S" && argidx+1 < args.size()) {
1206 lutin_shared = "-S " + args[++argidx];
1207 continue;
1208 }
1209 if (arg == "-lut" && argidx+1 < args.size()) {
1210 string arg = args[++argidx];
1211 size_t pos = arg.find_first_of(':');
1212 int lut_mode = 0, lut_mode2 = 0;
1213 if (pos != string::npos) {
1214 lut_mode = atoi(arg.substr(0, pos).c_str());
1215 lut_mode2 = atoi(arg.substr(pos+1).c_str());
1216 } else {
1217 pos = arg.find_first_of('.');
1218 if (pos != string::npos) {
1219 lut_file = arg;
1220 rewrite_filename(lut_file);
1221 if (!lut_file.empty() && !is_absolute_path(lut_file))
1222 lut_file = std::string(pwd) + "/" + lut_file;
1223 }
1224 else {
1225 lut_mode = atoi(arg.c_str());
1226 lut_mode2 = lut_mode;
1227 }
1228 }
1229 lut_costs.clear();
1230 for (int i = 0; i < lut_mode; i++)
1231 lut_costs.push_back(1);
1232 for (int i = lut_mode; i < lut_mode2; i++)
1233 lut_costs.push_back(2 << (i - lut_mode));
1234 continue;
1235 }
1236 if (arg == "-luts" && argidx+1 < args.size()) {
1237 lut_costs.clear();
1238 for (auto &tok : split_tokens(args[++argidx], ",")) {
1239 auto parts = split_tokens(tok, ":");
1240 if (GetSize(parts) == 0 && !lut_costs.empty())
1241 lut_costs.push_back(lut_costs.back());
1242 else if (GetSize(parts) == 1)
1243 lut_costs.push_back(atoi(parts.at(0).c_str()));
1244 else if (GetSize(parts) == 2)
1245 while (GetSize(lut_costs) < atoi(parts.at(0).c_str()))
1246 lut_costs.push_back(atoi(parts.at(1).c_str()));
1247 else
1248 log_cmd_error("Invalid -luts syntax.\n");
1249 }
1250 continue;
1251 }
1252 if (arg == "-sop") {
1253 sop_mode = true;
1254 continue;
1255 }
1256 if (arg == "-mux4") {
1257 map_mux4 = true;
1258 continue;
1259 }
1260 if (arg == "-mux8") {
1261 map_mux8 = true;
1262 continue;
1263 }
1264 if (arg == "-mux16") {
1265 map_mux16 = true;
1266 continue;
1267 }
1268 if (arg == "-dress") {
1269 // TODO
1270 //abc_dress = true;
1271 continue;
1272 }
1273 if (arg == "-g" && argidx+1 < args.size()) {
1274 for (auto g : split_tokens(args[++argidx], ",")) {
1275 vector<string> gate_list;
1276 bool remove_gates = false;
1277 if (GetSize(g) > 0 && g[0] == '-') {
1278 remove_gates = true;
1279 g = g.substr(1);
1280 }
1281 if (g == "AND") goto ok_gate;
1282 if (g == "NAND") goto ok_gate;
1283 if (g == "OR") goto ok_gate;
1284 if (g == "NOR") goto ok_gate;
1285 if (g == "XOR") goto ok_gate;
1286 if (g == "XNOR") goto ok_gate;
1287 if (g == "ANDNOT") goto ok_gate;
1288 if (g == "ORNOT") goto ok_gate;
1289 if (g == "MUX") goto ok_gate;
1290 if (g == "AOI3") goto ok_gate;
1291 if (g == "OAI3") goto ok_gate;
1292 if (g == "AOI4") goto ok_gate;
1293 if (g == "OAI4") goto ok_gate;
1294 if (g == "simple") {
1295 gate_list.push_back("AND");
1296 gate_list.push_back("OR");
1297 gate_list.push_back("XOR");
1298 gate_list.push_back("MUX");
1299 goto ok_alias;
1300 }
1301 if (g == "cmos2") {
1302 gate_list.push_back("NAND");
1303 gate_list.push_back("NOR");
1304 goto ok_alias;
1305 }
1306 if (g == "cmos3") {
1307 gate_list.push_back("NAND");
1308 gate_list.push_back("NOR");
1309 gate_list.push_back("AOI3");
1310 gate_list.push_back("OAI3");
1311 goto ok_alias;
1312 }
1313 if (g == "cmos4") {
1314 gate_list.push_back("NAND");
1315 gate_list.push_back("NOR");
1316 gate_list.push_back("AOI3");
1317 gate_list.push_back("OAI3");
1318 gate_list.push_back("AOI4");
1319 gate_list.push_back("OAI4");
1320 goto ok_alias;
1321 }
1322 if (g == "gates") {
1323 gate_list.push_back("AND");
1324 gate_list.push_back("NAND");
1325 gate_list.push_back("OR");
1326 gate_list.push_back("NOR");
1327 gate_list.push_back("XOR");
1328 gate_list.push_back("XNOR");
1329 gate_list.push_back("ANDNOT");
1330 gate_list.push_back("ORNOT");
1331 goto ok_alias;
1332 }
1333 if (g == "aig") {
1334 gate_list.push_back("AND");
1335 gate_list.push_back("NAND");
1336 gate_list.push_back("OR");
1337 gate_list.push_back("NOR");
1338 gate_list.push_back("ANDNOT");
1339 gate_list.push_back("ORNOT");
1340 goto ok_alias;
1341 }
1342 cmd_error(args, argidx, stringf("Unsupported gate type: %s", g.c_str()));
1343 ok_gate:
1344 gate_list.push_back(g);
1345 ok_alias:
1346 for (auto gate : gate_list) {
1347 if (remove_gates)
1348 enabled_gates.erase(gate);
1349 else
1350 enabled_gates.insert(gate);
1351 }
1352 }
1353 continue;
1354 }
1355 if (arg == "-fast") {
1356 fast_mode = true;
1357 continue;
1358 }
1359 if (arg == "-dff") {
1360 dff_mode = true;
1361 continue;
1362 }
1363 if (arg == "-clk" && argidx+1 < args.size()) {
1364 clk_str = args[++argidx];
1365 dff_mode = true;
1366 continue;
1367 }
1368 if (arg == "-keepff") {
1369 keepff = true;
1370 continue;
1371 }
1372 if (arg == "-nocleanup") {
1373 cleanup = false;
1374 continue;
1375 }
1376 if (arg == "-showtmp") {
1377 show_tempdir = true;
1378 continue;
1379 }
1380 if (arg == "-markgroups") {
1381 markgroups = true;
1382 continue;
1383 }
1384 if (arg == "-box" && argidx+1 < args.size()) {
1385 box_file = args[++argidx];
1386 rewrite_filename(box_file);
1387 if (!box_file.empty() && !is_absolute_path(box_file))
1388 box_file = std::string(pwd) + "/" + box_file;
1389 continue;
1390 }
1391 break;
1392 }
1393 extra_args(args, argidx, design);
1394
1395 if ((!lut_costs.empty() || !lut_file.empty()) && !liberty_file.empty())
1396 log_cmd_error("Got -lut and -liberty! This two options are exclusive.\n");
1397 if (!constr_file.empty() && liberty_file.empty())
1398 log_cmd_error("Got -constr but no -liberty!\n");
1399
1400 for (auto mod : design->selected_modules())
1401 {
1402 if (mod->processes.size() > 0) {
1403 log("Skipping module %s as it contains processes.\n", log_id(mod));
1404 continue;
1405 }
1406
1407 assign_map.set(mod);
1408 signal_init.clear();
1409
1410 for (Wire *wire : mod->wires())
1411 if (wire->attributes.count("\\init")) {
1412 SigSpec initsig = assign_map(wire);
1413 Const initval = wire->attributes.at("\\init");
1414 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
1415 switch (initval[i]) {
1416 case State::S0:
1417 signal_init[initsig[i]] = State::S0;
1418 break;
1419 case State::S1:
1420 signal_init[initsig[i]] = State::S0;
1421 break;
1422 default:
1423 break;
1424 }
1425 }
1426
1427 if (!dff_mode || !clk_str.empty()) {
1428 abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
1429 delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode,
1430 box_file, lut_file);
1431 continue;
1432 }
1433
1434 CellTypes ct(design);
1435
1436 std::vector<RTLIL::Cell*> all_cells = mod->selected_cells();
1437 std::set<RTLIL::Cell*> unassigned_cells(all_cells.begin(), all_cells.end());
1438
1439 std::set<RTLIL::Cell*> expand_queue, next_expand_queue;
1440 std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
1441 std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
1442
1443 typedef tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
1444 std::map<clkdomain_t, std::vector<RTLIL::Cell*>> assigned_cells;
1445 std::map<RTLIL::Cell*, clkdomain_t> assigned_cells_reverse;
1446
1447 std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
1448 std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
1449
1450 for (auto cell : all_cells)
1451 {
1452 clkdomain_t key;
1453
1454 for (auto &conn : cell->connections())
1455 for (auto bit : conn.second) {
1456 bit = assign_map(bit);
1457 if (bit.wire != nullptr) {
1458 cell_to_bit[cell].insert(bit);
1459 bit_to_cell[bit].insert(cell);
1460 if (ct.cell_input(cell->type, conn.first)) {
1461 cell_to_bit_up[cell].insert(bit);
1462 bit_to_cell_down[bit].insert(cell);
1463 }
1464 if (ct.cell_output(cell->type, conn.first)) {
1465 cell_to_bit_down[cell].insert(bit);
1466 bit_to_cell_up[bit].insert(cell);
1467 }
1468 }
1469 }
1470
1471 if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
1472 {
1473 key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
1474 }
1475 else
1476 if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
1477 {
1478 bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_";
1479 bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_";
1480 key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E")));
1481 }
1482 else
1483 continue;
1484
1485 unassigned_cells.erase(cell);
1486 expand_queue.insert(cell);
1487 expand_queue_up.insert(cell);
1488 expand_queue_down.insert(cell);
1489
1490 assigned_cells[key].push_back(cell);
1491 assigned_cells_reverse[cell] = key;
1492 }
1493
1494 while (!expand_queue_up.empty() || !expand_queue_down.empty())
1495 {
1496 if (!expand_queue_up.empty())
1497 {
1498 RTLIL::Cell *cell = *expand_queue_up.begin();
1499 clkdomain_t key = assigned_cells_reverse.at(cell);
1500 expand_queue_up.erase(cell);
1501
1502 for (auto bit : cell_to_bit_up[cell])
1503 for (auto c : bit_to_cell_up[bit])
1504 if (unassigned_cells.count(c)) {
1505 unassigned_cells.erase(c);
1506 next_expand_queue_up.insert(c);
1507 assigned_cells[key].push_back(c);
1508 assigned_cells_reverse[c] = key;
1509 expand_queue.insert(c);
1510 }
1511 }
1512
1513 if (!expand_queue_down.empty())
1514 {
1515 RTLIL::Cell *cell = *expand_queue_down.begin();
1516 clkdomain_t key = assigned_cells_reverse.at(cell);
1517 expand_queue_down.erase(cell);
1518
1519 for (auto bit : cell_to_bit_down[cell])
1520 for (auto c : bit_to_cell_down[bit])
1521 if (unassigned_cells.count(c)) {
1522 unassigned_cells.erase(c);
1523 next_expand_queue_up.insert(c);
1524 assigned_cells[key].push_back(c);
1525 assigned_cells_reverse[c] = key;
1526 expand_queue.insert(c);
1527 }
1528 }
1529
1530 if (expand_queue_up.empty() && expand_queue_down.empty()) {
1531 expand_queue_up.swap(next_expand_queue_up);
1532 expand_queue_down.swap(next_expand_queue_down);
1533 }
1534 }
1535
1536 while (!expand_queue.empty())
1537 {
1538 RTLIL::Cell *cell = *expand_queue.begin();
1539 clkdomain_t key = assigned_cells_reverse.at(cell);
1540 expand_queue.erase(cell);
1541
1542 for (auto bit : cell_to_bit.at(cell)) {
1543 for (auto c : bit_to_cell[bit])
1544 if (unassigned_cells.count(c)) {
1545 unassigned_cells.erase(c);
1546 next_expand_queue.insert(c);
1547 assigned_cells[key].push_back(c);
1548 assigned_cells_reverse[c] = key;
1549 }
1550 bit_to_cell[bit].clear();
1551 }
1552
1553 if (expand_queue.empty())
1554 expand_queue.swap(next_expand_queue);
1555 }
1556
1557 clkdomain_t key(true, RTLIL::SigSpec(), true, RTLIL::SigSpec());
1558 for (auto cell : unassigned_cells) {
1559 assigned_cells[key].push_back(cell);
1560 assigned_cells_reverse[cell] = key;
1561 }
1562
1563 log_header(design, "Summary of detected clock domains:\n");
1564 for (auto &it : assigned_cells)
1565 log(" %d cells in clk=%s%s, en=%s%s\n", GetSize(it.second),
1566 std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
1567 std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
1568
1569 for (auto &it : assigned_cells) {
1570 clk_polarity = std::get<0>(it.first);
1571 clk_sig = assign_map(std::get<1>(it.first));
1572 en_polarity = std::get<2>(it.first);
1573 en_sig = assign_map(std::get<3>(it.first));
1574 abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
1575 keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode,
1576 box_file, lut_file);
1577 assign_map.set(mod);
1578 }
1579 }
1580
1581 Pass::call(design, "clean");
1582
1583 assign_map.clear();
1584 signal_map.clear();
1585 signal_init.clear();
1586 pi_map.clear();
1587 po_map.clear();
1588
1589 log_pop();
1590 }
1591 } Abc9Pass;
1592
1593 PRIVATE_NAMESPACE_END