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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
[yosys.git] / passes / techmap / abc9.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // [[CITE]] ABC
22 // Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
23 // http://www.eecs.berkeley.edu/~alanmi/abc/
24
25 #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
26 #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p"
27 //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2"
28 #define ABC_COMMAND_LUT "&st; &fraig; &scorr; &dc2; &retime; &dch -f; &if; &mfs"
29 #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}"
30 #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
31
32 #define ABC_FAST_COMMAND_LIB "strash; dretime; map {D}"
33 #define ABC_FAST_COMMAND_CTR "strash; dretime; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
34 #define ABC_FAST_COMMAND_LUT "&st; &retime; &if"
35 #define ABC_FAST_COMMAND_SOP "strash; dretime; cover -I {I} -P {P}"
36 #define ABC_FAST_COMMAND_DFL "strash; dretime; map"
37
38 #include "kernel/register.h"
39 #include "kernel/sigtools.h"
40 #include "kernel/celltypes.h"
41 #include "kernel/cost.h"
42 #include "kernel/log.h"
43 #include <stdlib.h>
44 #include <stdio.h>
45 #include <string.h>
46 #include <cerrno>
47 #include <sstream>
48 #include <climits>
49
50 #ifndef _WIN32
51 # include <unistd.h>
52 # include <dirent.h>
53 #endif
54
55 #include "frontends/aiger/aigerparse.h"
56
57 #ifdef YOSYS_LINK_ABC
58 extern "C" int Abc_RealMain(int argc, char *argv[]);
59 #endif
60
61 USING_YOSYS_NAMESPACE
62 PRIVATE_NAMESPACE_BEGIN
63
64 bool map_mux4;
65 bool map_mux8;
66 bool map_mux16;
67
68 bool markgroups;
69 int map_autoidx;
70 SigMap assign_map;
71 RTLIL::Module *module;
72 std::map<RTLIL::SigBit, int> signal_map;
73 std::map<RTLIL::SigBit, RTLIL::State> signal_init;
74 pool<std::string> enabled_gates;
75 bool recover_init;
76
77 bool clk_polarity, en_polarity;
78 RTLIL::SigSpec clk_sig, en_sig;
79 dict<int, std::string> pi_map, po_map;
80
81 std::string remap_name(RTLIL::IdString abc_name)
82 {
83 std::stringstream sstr;
84 sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1);
85 return sstr.str();
86 }
87
88 void handle_loops(RTLIL::Design *design)
89 {
90 Pass::call(design, "scc -set_attr abc_scc_id {}");
91
92 design->selection_stack.emplace_back(false);
93 RTLIL::Selection& sel = design->selection_stack.back();
94
95 // For every unique SCC found, (arbitrarily) find the first
96 // cell in the component, and select (and mark) all its output
97 // wires
98 pool<RTLIL::Const> ids_seen;
99 for (auto cell : module->cells()) {
100 auto it = cell->attributes.find("\\abc_scc_id");
101 if (it != cell->attributes.end()) {
102 auto r = ids_seen.insert(it->second);
103 if (r.second) {
104 for (const auto &c : cell->connections()) {
105 if (c.second.is_fully_const()) continue;
106 if (cell->output(c.first)) {
107 SigBit b = c.second.as_bit();
108 Wire *w = b.wire;
109 w->set_bool_attribute("\\abc_scc_break");
110 sel.select(module, w);
111 }
112 }
113 }
114 cell->attributes.erase(it);
115 }
116 }
117
118 // Then cut those selected wires to expose them as new PO/PI
119 Pass::call(design, "expose -cut -sep .abc");
120
121 design->selection_stack.pop_back();
122 }
123
124 std::string add_echos_to_abc_cmd(std::string str)
125 {
126 std::string new_str, token;
127 for (size_t i = 0; i < str.size(); i++) {
128 token += str[i];
129 if (str[i] == ';') {
130 while (i+1 < str.size() && str[i+1] == ' ')
131 i++;
132 new_str += "echo + " + token + " " + token + " ";
133 token.clear();
134 }
135 }
136
137 if (!token.empty()) {
138 if (!new_str.empty())
139 new_str += "echo + " + token + "; ";
140 new_str += token;
141 }
142
143 return new_str;
144 }
145
146 std::string fold_abc_cmd(std::string str)
147 {
148 std::string token, new_str = " ";
149 int char_counter = 10;
150
151 for (size_t i = 0; i <= str.size(); i++) {
152 if (i < str.size())
153 token += str[i];
154 if (i == str.size() || str[i] == ';') {
155 if (char_counter + token.size() > 75)
156 new_str += "\n ", char_counter = 14;
157 new_str += token, char_counter += token.size();
158 token.clear();
159 }
160 }
161
162 return new_str;
163 }
164
165 std::string replace_tempdir(std::string text, std::string tempdir_name, bool show_tempdir)
166 {
167 if (show_tempdir)
168 return text;
169
170 while (1) {
171 size_t pos = text.find(tempdir_name);
172 if (pos == std::string::npos)
173 break;
174 text = text.substr(0, pos) + "<abc-temp-dir>" + text.substr(pos + GetSize(tempdir_name));
175 }
176
177 std::string selfdir_name = proc_self_dirname();
178 if (selfdir_name != "/") {
179 while (1) {
180 size_t pos = text.find(selfdir_name);
181 if (pos == std::string::npos)
182 break;
183 text = text.substr(0, pos) + "<yosys-exe-dir>/" + text.substr(pos + GetSize(selfdir_name));
184 }
185 }
186
187 return text;
188 }
189
190 struct abc_output_filter
191 {
192 bool got_cr;
193 int escape_seq_state;
194 std::string linebuf;
195 std::string tempdir_name;
196 bool show_tempdir;
197
198 abc_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir)
199 {
200 got_cr = false;
201 escape_seq_state = 0;
202 }
203
204 void next_char(char ch)
205 {
206 if (escape_seq_state == 0 && ch == '\033') {
207 escape_seq_state = 1;
208 return;
209 }
210 if (escape_seq_state == 1) {
211 escape_seq_state = ch == '[' ? 2 : 0;
212 return;
213 }
214 if (escape_seq_state == 2) {
215 if ((ch < '0' || '9' < ch) && ch != ';')
216 escape_seq_state = 0;
217 return;
218 }
219 escape_seq_state = 0;
220 if (ch == '\r') {
221 got_cr = true;
222 return;
223 }
224 if (ch == '\n') {
225 log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir).c_str());
226 got_cr = false, linebuf.clear();
227 return;
228 }
229 if (got_cr)
230 got_cr = false, linebuf.clear();
231 linebuf += ch;
232 }
233
234 void next_line(const std::string &line)
235 {
236 int pi, po;
237 if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
238 log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
239 pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???",
240 po, po_map.count(po) ? po_map.at(po).c_str() : "???");
241 return;
242 }
243
244 for (char ch : line)
245 next_char(ch);
246 }
247 };
248
249 static std::pair<RTLIL::IdString, int> wideports_split(std::string name)
250 {
251 int pos = -1;
252
253 if (name.empty() || name.back() != ']')
254 goto failed;
255
256 for (int i = 0; i+1 < GetSize(name); i++) {
257 if (name[i] == '[')
258 pos = i;
259 else if (name[i] < '0' || name[i] > '9')
260 pos = -1;
261 else if (i == pos+1 && name[i] == '0' && name[i+1] != ']')
262 pos = -1;
263 }
264
265 if (pos >= 0)
266 return std::pair<RTLIL::IdString, int>(RTLIL::escape_id(name.substr(0, pos)), atoi(name.c_str() + pos+1));
267
268 failed:
269 return std::pair<RTLIL::IdString, int>(name, 0);
270 }
271
272 void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
273 std::string liberty_file, std::string constr_file, bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
274 bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode,
275 const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode)
276 {
277 module = current_module;
278 map_autoidx = autoidx++;
279
280 signal_map.clear();
281 pi_map.clear();
282 po_map.clear();
283 recover_init = false;
284
285 if (clk_str != "$")
286 {
287 clk_polarity = true;
288 clk_sig = RTLIL::SigSpec();
289
290 en_polarity = true;
291 en_sig = RTLIL::SigSpec();
292 }
293
294 if (!clk_str.empty() && clk_str != "$")
295 {
296 if (clk_str.find(',') != std::string::npos) {
297 int pos = clk_str.find(',');
298 std::string en_str = clk_str.substr(pos+1);
299 clk_str = clk_str.substr(0, pos);
300 if (en_str[0] == '!') {
301 en_polarity = false;
302 en_str = en_str.substr(1);
303 }
304 if (module->wires_.count(RTLIL::escape_id(en_str)) != 0)
305 en_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(en_str)), 0));
306 }
307 if (clk_str[0] == '!') {
308 clk_polarity = false;
309 clk_str = clk_str.substr(1);
310 }
311 if (module->wires_.count(RTLIL::escape_id(clk_str)) != 0)
312 clk_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(clk_str)), 0));
313 }
314
315 if (dff_mode && clk_sig.empty())
316 log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
317
318 std::string tempdir_name = "/tmp/yosys-abc-XXXXXX";
319 if (!cleanup)
320 tempdir_name[0] = tempdir_name[4] = '_';
321 tempdir_name = make_temp_dir(tempdir_name);
322 log_header(design, "Extracting gate netlist of module `%s' to `%s/input.aig'..\n",
323 module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
324
325 std::string abc_script = stringf("read %s/input.aig; &get -n; ", tempdir_name.c_str());
326
327 if (!liberty_file.empty()) {
328 abc_script += stringf("read_lib -w %s; ", liberty_file.c_str());
329 if (!constr_file.empty())
330 abc_script += stringf("read_constr -v %s; ", constr_file.c_str());
331 } else
332 if (!lut_costs.empty())
333 abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
334 else
335 abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str());
336
337 if (!script_file.empty()) {
338 if (script_file[0] == '+') {
339 for (size_t i = 1; i < script_file.size(); i++)
340 if (script_file[i] == '\'')
341 abc_script += "'\\''";
342 else if (script_file[i] == ',')
343 abc_script += " ";
344 else
345 abc_script += script_file[i];
346 } else
347 abc_script += stringf("source %s", script_file.c_str());
348 } else if (!lut_costs.empty()) {
349 bool all_luts_cost_same = true;
350 for (int this_cost : lut_costs)
351 if (this_cost != lut_costs.front())
352 all_luts_cost_same = false;
353 abc_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
354 //if (all_luts_cost_same && !fast_mode)
355 // abc_script += "; lutpack {S}";
356 } else if (!liberty_file.empty())
357 abc_script += constr_file.empty() ? (fast_mode ? ABC_FAST_COMMAND_LIB : ABC_COMMAND_LIB) : (fast_mode ? ABC_FAST_COMMAND_CTR : ABC_COMMAND_CTR);
358 else if (sop_mode)
359 abc_script += fast_mode ? ABC_FAST_COMMAND_SOP : ABC_COMMAND_SOP;
360 else
361 abc_script += fast_mode ? ABC_FAST_COMMAND_DFL : ABC_COMMAND_DFL;
362
363 if (script_file.empty() && !delay_target.empty())
364 for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1))
365 abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8);
366
367 for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
368 abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);
369
370 for (size_t pos = abc_script.find("{I}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
371 abc_script = abc_script.substr(0, pos) + sop_inputs + abc_script.substr(pos+3);
372
373 for (size_t pos = abc_script.find("{P}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
374 abc_script = abc_script.substr(0, pos) + sop_products + abc_script.substr(pos+3);
375
376 for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
377 abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
378
379 abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
380 abc_script = add_echos_to_abc_cmd(abc_script);
381
382 for (size_t i = 0; i+1 < abc_script.size(); i++)
383 if (abc_script[i] == ';' && abc_script[i+1] == ' ')
384 abc_script[i+1] = '\n';
385
386 FILE *f = fopen(stringf("%s/abc.script", tempdir_name.c_str()).c_str(), "wt");
387 fprintf(f, "%s\n", abc_script.c_str());
388 fclose(f);
389
390 if (dff_mode || !clk_str.empty())
391 {
392 if (clk_sig.size() == 0)
393 log("No%s clock domain found. Not extracting any FF cells.\n", clk_str.empty() ? "" : " matching");
394 else {
395 log("Found%s %s clock domain: %s", clk_str.empty() ? "" : " matching", clk_polarity ? "posedge" : "negedge", log_signal(clk_sig));
396 if (en_sig.size() != 0)
397 log(", enabled by %s%s", en_polarity ? "" : "!", log_signal(en_sig));
398 log("\n");
399 }
400 }
401
402 design->selection_stack.emplace_back(false);
403 RTLIL::Selection& sel = design->selection_stack.back();
404 sel.select(module);
405
406 Pass::call(design, "aigmap");
407
408 handle_loops(design);
409
410 Pass::call(design, stringf("write_xaiger -O -map %s/input.sym %s/input.aig; ", tempdir_name.c_str(), tempdir_name.c_str()));
411
412 design->selection_stack.pop_back();
413
414 // Now 'unexpose' those wires by undoing
415 // the expose operation -- remove them from PO/PI
416 // and re-connecting them back together
417 for (auto wire : module->wires()) {
418 auto it = wire->attributes.find("\\abc_scc_break");
419 if (it != wire->attributes.end()) {
420 wire->attributes.erase(it);
421 log_assert(wire->port_output);
422 wire->port_output = false;
423 RTLIL::Wire *i_wire = module->wire(wire->name.str() + ".abci");
424 log_assert(i_wire);
425 log_assert(i_wire->port_input);
426 i_wire->port_input = false;
427 module->connect(i_wire, wire);
428 }
429 }
430 module->fixup_ports();
431
432 //log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
433 // count_gates, GetSize(signal_list), count_input, count_output);
434
435 log_push();
436
437 //if (count_output > 0)
438 {
439 log_header(design, "Executing ABC9.\n");
440
441 std::string buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str());
442 f = fopen(buffer.c_str(), "wt");
443 if (f == NULL)
444 log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
445 fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
446 fprintf(f, "GATE ONE 1 Y=CONST1;\n");
447 fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_BUF_"));
448 fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOT_"));
449 if (enabled_gates.empty() || enabled_gates.count("AND"))
450 fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_AND_"));
451 if (enabled_gates.empty() || enabled_gates.count("NAND"))
452 fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NAND_"));
453 if (enabled_gates.empty() || enabled_gates.count("OR"))
454 fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_OR_"));
455 if (enabled_gates.empty() || enabled_gates.count("NOR"))
456 fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOR_"));
457 if (enabled_gates.empty() || enabled_gates.count("XOR"))
458 fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XOR_"));
459 if (enabled_gates.empty() || enabled_gates.count("XNOR"))
460 fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XNOR_"));
461 if (enabled_gates.empty() || enabled_gates.count("ANDNOT"))
462 fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_ANDNOT_"));
463 if (enabled_gates.empty() || enabled_gates.count("ORNOT"))
464 fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_ORNOT_"));
465 if (enabled_gates.empty() || enabled_gates.count("AOI3"))
466 fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI3_"));
467 if (enabled_gates.empty() || enabled_gates.count("OAI3"))
468 fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI3_"));
469 if (enabled_gates.empty() || enabled_gates.count("AOI4"))
470 fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI4_"));
471 if (enabled_gates.empty() || enabled_gates.count("OAI4"))
472 fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI4_"));
473 if (enabled_gates.empty() || enabled_gates.count("MUX"))
474 fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_MUX_"));
475 if (map_mux4)
476 fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*get_cell_cost("$_MUX_"));
477 if (map_mux8)
478 fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*get_cell_cost("$_MUX_"));
479 if (map_mux16)
480 fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*get_cell_cost("$_MUX_"));
481 fclose(f);
482
483 if (!lut_costs.empty()) {
484 buffer = stringf("%s/lutdefs.txt", tempdir_name.c_str());
485 f = fopen(buffer.c_str(), "wt");
486 if (f == NULL)
487 log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
488 for (int i = 0; i < GetSize(lut_costs); i++)
489 fprintf(f, "%d %d.00 1.00\n", i+1, lut_costs.at(i));
490 fclose(f);
491 }
492
493 buffer = stringf("%s -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
494 log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
495
496 #ifndef YOSYS_LINK_ABC
497 abc_output_filter filt(tempdir_name, show_tempdir);
498 int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1));
499 #else
500 // These needs to be mutable, supposedly due to getopt
501 char *abc_argv[5];
502 string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str());
503 abc_argv[0] = strdup(exe_file.c_str());
504 abc_argv[1] = strdup("-s");
505 abc_argv[2] = strdup("-f");
506 abc_argv[3] = strdup(tmp_script_name.c_str());
507 abc_argv[4] = 0;
508 int ret = Abc_RealMain(4, abc_argv);
509 free(abc_argv[0]);
510 free(abc_argv[1]);
511 free(abc_argv[2]);
512 free(abc_argv[3]);
513 #endif
514 if (ret != 0)
515 log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
516
517 buffer = stringf("%s/%s", tempdir_name.c_str(), "output.aig");
518 std::ifstream ifs;
519 ifs.open(buffer);
520 if (ifs.fail())
521 log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
522
523 bool builtin_lib = liberty_file.empty();
524 RTLIL::Design *mapped_design = new RTLIL::Design;
525 //parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
526 buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
527 AigerReader reader(mapped_design, ifs, "\\netlist", "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
528 reader.parse_xaiger();
529
530 ifs.close();
531
532 log_header(design, "Re-integrating ABC9 results.\n");
533 RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"];
534 if (mapped_mod == NULL)
535 log_error("ABC output file does not contain a module `netlist'.\n");
536
537 pool<RTLIL::SigBit> output_bits;
538 for (auto &it : mapped_mod->wires_) {
539 RTLIL::Wire *w = it.second;
540 RTLIL::Wire *remap_wire = module->addWire(remap_name(w->name), GetSize(w));
541 if (markgroups) remap_wire->attributes["\\abcgroup"] = map_autoidx;
542 if (w->port_output) {
543 RTLIL::Wire *wire = module->wire(w->name);
544 if (wire) {
545 for (int i = 0; i < GetSize(wire); i++)
546 output_bits.insert({wire, i});
547 }
548 else {
549 if (w->name.str() == "\\__dummy_o__") {
550 log("Don't call ABC as there is nothing to map.\n");
551 goto cleanup;
552 }
553
554 // Attempt another wideports_split here because there
555 // exists the possibility that different bits of a port
556 // could be an input and output, therefore parse_xiager()
557 // could not combine it into a wideport
558 auto r = wideports_split(w->name.str());
559 wire = module->wire(r.first);
560 log_assert(wire);
561 int i = r.second;
562 output_bits.insert({wire, i});
563 }
564 }
565 }
566
567 std::map<std::string, int> cell_stats;
568 for (auto c : mapped_mod->cells())
569 {
570 if (builtin_lib)
571 {
572 if (c->type == "$_NOT_") {
573 RTLIL::Cell *cell;
574 RTLIL::SigBit a_bit = c->getPort("\\A").as_bit();
575 RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit();
576 if (!lut_costs.empty()) {
577 // ABC can return NOT gates that drive POs
578 if (a_bit.wire->port_input) {
579 // If it's a NOT gate that comes from a primary input directly
580 // then implement it using a LUT
581 cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())),
582 RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset),
583 RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
584 1);
585 }
586 else {
587 // Otherwise, clone the driving LUT to guarantee that we
588 // won't increase the max logic depth
589 // (TODO: Optimise by not cloning unless will increase depth)
590 RTLIL::IdString driver_name;
591 if (GetSize(a_bit.wire) == 1)
592 driver_name = stringf("%s$lut", a_bit.wire->name.c_str());
593 else
594 driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset);
595 RTLIL::Cell* driver = mapped_mod->cell(driver_name);
596 log_assert(driver);
597 auto driver_a = driver->getPort("\\A").chunks();
598 for (auto &chunk : driver_a)
599 chunk.wire = module->wires_[remap_name(chunk.wire->name)];
600 RTLIL::Const driver_lut = driver->getParam("\\LUT");
601 for (auto &b : driver_lut.bits) {
602 if (b == RTLIL::State::S0) b = RTLIL::State::S1;
603 else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
604 }
605 cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())),
606 driver_a,
607 RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
608 driver_lut);
609 }
610 cell_stats["$lut"]++;
611 }
612 else {
613 cell = module->addCell(remap_name(c->name), "$_NOT_");
614 cell->setPort("\\A", RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset));
615 cell->setPort("\\Y", RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset));
616 cell_stats[RTLIL::unescape_id(c->type)]++;
617 }
618 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
619 continue;
620 }
621
622 cell_stats[RTLIL::unescape_id(c->type)]++;
623 if (c->type == "\\ZERO" || c->type == "\\ONE") {
624 RTLIL::SigSig conn;
625 conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]);
626 conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1);
627 module->connect(conn);
628 continue;
629 }
630 if (c->type == "\\BUF") {
631 RTLIL::SigSig conn;
632 conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]);
633 conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]);
634 module->connect(conn);
635 continue;
636 }
637
638 if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR" || c->type == "\\NAND" || c->type == "\\NOR" ||
639 c->type == "\\XNOR" || c->type == "\\ANDNOT" || c->type == "\\ORNOT") {
640 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
641 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
642 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
643 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
644 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
645 continue;
646 }
647 if (c->type == "\\MUX") {
648 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_");
649 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
650 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
651 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
652 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
653 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
654 continue;
655 }
656 if (c->type == "\\MUX4") {
657 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX4_");
658 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
659 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
660 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
661 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
662 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
663 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
664 cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
665 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
666 continue;
667 }
668 if (c->type == "\\MUX8") {
669 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX8_");
670 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
671 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
672 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
673 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
674 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
675 cell->setPort("\\E", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\E").as_wire()->name)]));
676 cell->setPort("\\F", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\F").as_wire()->name)]));
677 cell->setPort("\\G", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\G").as_wire()->name)]));
678 cell->setPort("\\H", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\H").as_wire()->name)]));
679 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
680 cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
681 cell->setPort("\\U", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\U").as_wire()->name)]));
682 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
683 continue;
684 }
685 if (c->type == "\\MUX16") {
686 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX16_");
687 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
688 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
689 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
690 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
691 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
692 cell->setPort("\\E", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\E").as_wire()->name)]));
693 cell->setPort("\\F", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\F").as_wire()->name)]));
694 cell->setPort("\\G", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\G").as_wire()->name)]));
695 cell->setPort("\\H", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\H").as_wire()->name)]));
696 cell->setPort("\\I", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\I").as_wire()->name)]));
697 cell->setPort("\\J", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\J").as_wire()->name)]));
698 cell->setPort("\\K", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\K").as_wire()->name)]));
699 cell->setPort("\\L", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\L").as_wire()->name)]));
700 cell->setPort("\\M", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\M").as_wire()->name)]));
701 cell->setPort("\\N", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\N").as_wire()->name)]));
702 cell->setPort("\\O", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\O").as_wire()->name)]));
703 cell->setPort("\\P", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\P").as_wire()->name)]));
704 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
705 cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
706 cell->setPort("\\U", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\U").as_wire()->name)]));
707 cell->setPort("\\V", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\V").as_wire()->name)]));
708 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
709 continue;
710 }
711 if (c->type == "\\AOI3" || c->type == "\\OAI3") {
712 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
713 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
714 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
715 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
716 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
717 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
718 continue;
719 }
720 if (c->type == "\\AOI4" || c->type == "\\OAI4") {
721 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
722 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
723 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
724 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
725 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
726 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
727 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
728 continue;
729 }
730 if (c->type == "\\DFF") {
731 log_assert(clk_sig.size() == 1);
732 RTLIL::Cell *cell;
733 if (en_sig.size() == 0) {
734 cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
735 } else {
736 log_assert(en_sig.size() == 1);
737 cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
738 cell->setPort("\\E", en_sig);
739 }
740 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
741 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
742 cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
743 cell->setPort("\\C", clk_sig);
744 continue;
745 }
746 }
747 else
748 cell_stats[RTLIL::unescape_id(c->type)]++;
749
750 if (c->type == "\\_const0_" || c->type == "\\_const1_") {
751 RTLIL::SigSig conn;
752 conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->connections().begin()->second.as_wire()->name)]);
753 conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1);
754 module->connect(conn);
755 continue;
756 }
757
758 if (c->type == "\\_dff_") {
759 log_assert(clk_sig.size() == 1);
760 RTLIL::Cell *cell;
761 if (en_sig.size() == 0) {
762 cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
763 } else {
764 log_assert(en_sig.size() == 1);
765 cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
766 cell->setPort("\\E", en_sig);
767 }
768 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
769 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
770 cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
771 cell->setPort("\\C", clk_sig);
772 continue;
773 }
774
775 if (c->type == "$lut" && GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) {
776 SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)];
777 SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)];
778 module->connect(my_y, my_a);
779 continue;
780 }
781
782 RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
783 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
784 cell->parameters = c->parameters;
785 for (auto &conn : c->connections()) {
786 RTLIL::SigSpec newsig;
787 for (auto c : conn.second.chunks()) {
788 if (c.width == 0)
789 continue;
790 //log_assert(c.width == 1);
791 c.wire = module->wires_[remap_name(c.wire->name)];
792 newsig.append(c);
793 }
794 cell->setPort(conn.first, newsig);
795 }
796 }
797
798 // Copy connections (and rename) from mapped_mod to module
799 for (auto conn : mapped_mod->connections()) {
800 if (!conn.first.is_fully_const()) {
801 auto chunks = conn.first.chunks();
802 for (auto &c : chunks)
803 c.wire = module->wires_[remap_name(c.wire->name)];
804 conn.first = std::move(chunks);
805 }
806 if (!conn.second.is_fully_const()) {
807 auto chunks = conn.second.chunks();
808 for (auto &c : chunks)
809 if (c.wire)
810 c.wire = module->wires_[remap_name(c.wire->name)];
811 conn.second = std::move(chunks);
812 }
813 module->connect(conn);
814 }
815
816 if (recover_init)
817 for (auto wire : mapped_mod->wires()) {
818 if (wire->attributes.count("\\init")) {
819 Wire *w = module->wires_[remap_name(wire->name)];
820 log_assert(w->attributes.count("\\init") == 0);
821 w->attributes["\\init"] = wire->attributes.at("\\init");
822 }
823 }
824
825 for (auto &it : cell_stats)
826 log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
827 int in_wires = 0, out_wires = 0;
828 //for (auto &si : signal_list)
829 // if (si.is_port) {
830 // char buffer[100];
831 // snprintf(buffer, 100, "\\n%d", si.id);
832 // RTLIL::SigSig conn;
833 // if (si.type != G(NONE)) {
834 // conn.first = si.bit;
835 // conn.second = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
836 // out_wires++;
837 // } else {
838 // conn.first = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
839 // conn.second = si.bit;
840 // in_wires++;
841 // }
842 // module->connect(conn);
843 // }
844
845 // Go through all AND and NOT output connections,
846 // and for those output ports driving wires
847 // also driven by mapped_mod, disconnect them
848 for (auto cell : module->cells()) {
849 if (!cell->type.in("$_AND_", "$_NOT_"))
850 continue;
851 for (auto &it : cell->connections_) {
852 auto port_name = it.first;
853 if (!cell->output(port_name)) continue;
854 auto &signal = it.second;
855 auto bits = signal.bits();
856 for (auto &b : bits)
857 if (output_bits.count(b))
858 b = module->addWire(NEW_ID);
859 signal = std::move(bits);
860 }
861 }
862 // Do the same for module connections
863 for (auto &it : module->connections_) {
864 auto &signal = it.first;
865 auto bits = signal.bits();
866 for (auto &b : bits)
867 if (output_bits.count(b))
868 b = module->addWire(NEW_ID);
869 signal = std::move(bits);
870 }
871
872 // Stitch in mapped_mod's inputs/outputs into module
873 for (auto &it : mapped_mod->wires_) {
874 RTLIL::Wire *w = it.second;
875 if (!w->port_input && !w->port_output)
876 continue;
877 RTLIL::Wire *wire = module->wire(w->name);
878 RTLIL::Wire *remap_wire = module->wire(remap_name(w->name));
879 RTLIL::SigSpec signal;
880 if (wire) {
881 signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
882 }
883 else {
884 // Attempt another wideports_split here because there
885 // exists the possibility that different bits of a port
886 // could be an input and output, therefore parse_xiager()
887 // could not combine it into a wideport
888 auto r = wideports_split(w->name.str());
889 wire = module->wire(r.first);
890 log_assert(wire);
891 int i = r.second;
892 signal = RTLIL::SigSpec(wire, i);
893 }
894 log_assert(GetSize(signal) >= GetSize(remap_wire));
895
896 log_assert(w->port_input || w->port_output);
897 RTLIL::SigSig conn;
898 if (w->port_input) {
899 conn.first = remap_wire;
900 conn.second = signal;
901 in_wires++;
902 module->connect(conn);
903 }
904 if (w->port_output) {
905 conn.first = signal;
906 conn.second = remap_wire;
907 out_wires++;
908 module->connect(conn);
909 }
910 }
911
912 //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
913 log("ABC RESULTS: input signals: %8d\n", in_wires);
914 log("ABC RESULTS: output signals: %8d\n", out_wires);
915
916 delete mapped_design;
917 }
918 //else
919 //{
920 // log("Don't call ABC as there is nothing to map.\n");
921 //}
922
923 cleanup:
924 if (cleanup)
925 {
926 log("Removing temp directory.\n");
927 remove_directory(tempdir_name);
928 }
929
930 log_pop();
931 }
932
933 struct Abc9Pass : public Pass {
934 Abc9Pass() : Pass("abc9", "use ABC for technology mapping") { }
935 void help() YS_OVERRIDE
936 {
937 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
938 log("\n");
939 log(" abc9 [options] [selection]\n");
940 log("\n");
941 log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
942 log("library to a target architecture.\n");
943 log("\n");
944 log(" -exe <command>\n");
945 #ifdef ABCEXTERNAL
946 log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
947 #else
948 log(" use the specified command instead of \"<yosys-bindir>/yosys-abc\" to execute ABC.\n");
949 #endif
950 log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
951 log("\n");
952 log(" -script <file>\n");
953 log(" use the specified ABC script file instead of the default script.\n");
954 log("\n");
955 log(" if <file> starts with a plus sign (+), then the rest of the filename\n");
956 log(" string is interpreted as the command string to be passed to ABC. The\n");
957 log(" leading plus sign is removed and all commas (,) in the string are\n");
958 log(" replaced with blanks before the string is passed to ABC.\n");
959 log("\n");
960 log(" if no -script parameter is given, the following scripts are used:\n");
961 log("\n");
962 log(" for -liberty without -constr:\n");
963 log("%s\n", fold_abc_cmd(ABC_COMMAND_LIB).c_str());
964 log("\n");
965 log(" for -liberty with -constr:\n");
966 log("%s\n", fold_abc_cmd(ABC_COMMAND_CTR).c_str());
967 log("\n");
968 log(" for -lut/-luts (only one LUT size):\n");
969 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT "; lutpack {S}").c_str());
970 log("\n");
971 log(" for -lut/-luts (different LUT sizes):\n");
972 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT).c_str());
973 log("\n");
974 log(" for -sop:\n");
975 log("%s\n", fold_abc_cmd(ABC_COMMAND_SOP).c_str());
976 log("\n");
977 log(" otherwise:\n");
978 log("%s\n", fold_abc_cmd(ABC_COMMAND_DFL).c_str());
979 log("\n");
980 log(" -fast\n");
981 log(" use different default scripts that are slightly faster (at the cost\n");
982 log(" of output quality):\n");
983 log("\n");
984 log(" for -liberty without -constr:\n");
985 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LIB).c_str());
986 log("\n");
987 log(" for -liberty with -constr:\n");
988 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_CTR).c_str());
989 log("\n");
990 log(" for -lut/-luts:\n");
991 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT).c_str());
992 log("\n");
993 log(" for -sop:\n");
994 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_SOP).c_str());
995 log("\n");
996 log(" otherwise:\n");
997 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_DFL).c_str());
998 log("\n");
999 log(" -liberty <file>\n");
1000 log(" generate netlists for the specified cell library (using the liberty\n");
1001 log(" file format).\n");
1002 log("\n");
1003 log(" -constr <file>\n");
1004 log(" pass this file with timing constraints to ABC. use with -liberty.\n");
1005 log("\n");
1006 log(" a constr file contains two lines:\n");
1007 log(" set_driving_cell <cell_name>\n");
1008 log(" set_load <floating_point_number>\n");
1009 log("\n");
1010 log(" the set_driving_cell statement defines which cell type is assumed to\n");
1011 log(" drive the primary inputs and the set_load statement sets the load in\n");
1012 log(" femtofarads for each primary output.\n");
1013 log("\n");
1014 log(" -D <picoseconds>\n");
1015 log(" set delay target. the string {D} in the default scripts above is\n");
1016 log(" replaced by this option when used, and an empty string otherwise.\n");
1017 log(" this also replaces 'dretime' with 'dretime; retime -o {D}' in the\n");
1018 log(" default scripts above.\n");
1019 log("\n");
1020 log(" -I <num>\n");
1021 log(" maximum number of SOP inputs.\n");
1022 log(" (replaces {I} in the default scripts above)\n");
1023 log("\n");
1024 log(" -P <num>\n");
1025 log(" maximum number of SOP products.\n");
1026 log(" (replaces {P} in the default scripts above)\n");
1027 log("\n");
1028 log(" -S <num>\n");
1029 log(" maximum number of LUT inputs shared.\n");
1030 log(" (replaces {S} in the default scripts above, default: -S 1)\n");
1031 log("\n");
1032 log(" -lut <width>\n");
1033 log(" generate netlist using luts of (max) the specified width.\n");
1034 log("\n");
1035 log(" -lut <w1>:<w2>\n");
1036 log(" generate netlist using luts of (max) the specified width <w2>. All\n");
1037 log(" luts with width <= <w1> have constant cost. for luts larger than <w1>\n");
1038 log(" the area cost doubles with each additional input bit. the delay cost\n");
1039 log(" is still constant for all lut widths.\n");
1040 log("\n");
1041 log(" -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..\n");
1042 log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
1043 log(" 2, 3, .. inputs.\n");
1044 log("\n");
1045 log(" -sop\n");
1046 log(" map to sum-of-product cells and inverters\n");
1047 log("\n");
1048 // log(" -mux4, -mux8, -mux16\n");
1049 // log(" try to extract 4-input, 8-input, and/or 16-input muxes\n");
1050 // log(" (ignored when used with -liberty or -lut)\n");
1051 // log("\n");
1052 log(" -g type1,type2,...\n");
1053 log(" Map to the specified list of gate types. Supported gates types are:\n");
1054 log(" AND, NAND, OR, NOR, XOR, XNOR, ANDNOT, ORNOT, MUX, AOI3, OAI3, AOI4, OAI4.\n");
1055 log(" (The NOT gate is always added to this list automatically.)\n");
1056 log("\n");
1057 log(" The following aliases can be used to reference common sets of gate types:\n");
1058 log(" simple: AND OR XOR MUX\n");
1059 log(" cmos2: NAND NOR\n");
1060 log(" cmos3: NAND NOR AOI3 OAI3\n");
1061 log(" cmos4: NAND NOR AOI3 OAI3 AOI4 OAI4\n");
1062 log(" gates: AND NAND OR NOR XOR XNOR ANDNOT ORNOT\n");
1063 log(" aig: AND NAND OR NOR ANDNOT ORNOT\n");
1064 log("\n");
1065 log(" Prefix a gate type with a '-' to remove it from the list. For example\n");
1066 log(" the arguments 'AND,OR,XOR' and 'simple,-MUX' are equivalent.\n");
1067 log("\n");
1068 log(" -dff\n");
1069 log(" also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many\n");
1070 log(" clock domains are automatically partitioned in clock domains and each\n");
1071 log(" domain is passed through ABC independently.\n");
1072 log("\n");
1073 log(" -clk [!]<clock-signal-name>[,[!]<enable-signal-name>]\n");
1074 log(" use only the specified clock domain. this is like -dff, but only FF\n");
1075 log(" cells that belong to the specified clock domain are used.\n");
1076 log("\n");
1077 log(" -keepff\n");
1078 log(" set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
1079 log(" them, for example for equivalence checking.)\n");
1080 log("\n");
1081 log(" -nocleanup\n");
1082 log(" when this option is used, the temporary files created by this pass\n");
1083 log(" are not removed. this is useful for debugging.\n");
1084 log("\n");
1085 log(" -showtmp\n");
1086 log(" print the temp dir name in log. usually this is suppressed so that the\n");
1087 log(" command output is identical across runs.\n");
1088 log("\n");
1089 log(" -markgroups\n");
1090 log(" set a 'abcgroup' attribute on all objects created by ABC. The value of\n");
1091 log(" this attribute is a unique integer for each ABC process started. This\n");
1092 log(" is useful for debugging the partitioning of clock domains.\n");
1093 log("\n");
1094 log("When neither -liberty nor -lut is used, the Yosys standard cell library is\n");
1095 log("loaded into ABC before the ABC script is executed.\n");
1096 log("\n");
1097 log("Note that this is a logic optimization pass within Yosys that is calling ABC\n");
1098 log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
1099 log("ABC on logic snippets extracted from your design. You will not get any useful\n");
1100 log("output when passing an ABC script that writes a file. Instead write your full\n");
1101 log("design as BLIF file with write_blif and the load that into ABC externally if\n");
1102 log("you want to use ABC to convert your design into another format.\n");
1103 log("\n");
1104 log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
1105 log("\n");
1106 }
1107 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1108 {
1109 log_header(design, "Executing ABC9 pass (technology mapping using ABC).\n");
1110 log_push();
1111
1112 assign_map.clear();
1113 signal_map.clear();
1114 signal_init.clear();
1115 pi_map.clear();
1116 po_map.clear();
1117
1118 #ifdef ABCEXTERNAL
1119 std::string exe_file = ABCEXTERNAL;
1120 #else
1121 std::string exe_file = proc_self_dirname() + "yosys-abc";
1122 #endif
1123 std::string script_file, liberty_file, constr_file, clk_str;
1124 std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1";
1125 bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
1126 bool show_tempdir = false, sop_mode = false;
1127 vector<int> lut_costs;
1128 markgroups = false;
1129
1130 map_mux4 = false;
1131 map_mux8 = false;
1132 map_mux16 = false;
1133 enabled_gates.clear();
1134
1135 #ifdef _WIN32
1136 #ifndef ABCEXTERNAL
1137 if (!check_file_exists(exe_file + ".exe") && check_file_exists(proc_self_dirname() + "..\\yosys-abc.exe"))
1138 exe_file = proc_self_dirname() + "..\\yosys-abc";
1139 #endif
1140 #endif
1141
1142 size_t argidx;
1143 char pwd [PATH_MAX];
1144 if (!getcwd(pwd, sizeof(pwd))) {
1145 log_cmd_error("getcwd failed: %s\n", strerror(errno));
1146 log_abort();
1147 }
1148 for (argidx = 1; argidx < args.size(); argidx++) {
1149 std::string arg = args[argidx];
1150 if (arg == "-exe" && argidx+1 < args.size()) {
1151 exe_file = args[++argidx];
1152 continue;
1153 }
1154 if (arg == "-script" && argidx+1 < args.size()) {
1155 script_file = args[++argidx];
1156 rewrite_filename(script_file);
1157 if (!script_file.empty() && !is_absolute_path(script_file) && script_file[0] != '+')
1158 script_file = std::string(pwd) + "/" + script_file;
1159 continue;
1160 }
1161 if (arg == "-liberty" && argidx+1 < args.size()) {
1162 liberty_file = args[++argidx];
1163 rewrite_filename(liberty_file);
1164 if (!liberty_file.empty() && !is_absolute_path(liberty_file))
1165 liberty_file = std::string(pwd) + "/" + liberty_file;
1166 continue;
1167 }
1168 if (arg == "-constr" && argidx+1 < args.size()) {
1169 rewrite_filename(constr_file);
1170 constr_file = args[++argidx];
1171 if (!constr_file.empty() && !is_absolute_path(constr_file))
1172 constr_file = std::string(pwd) + "/" + constr_file;
1173 continue;
1174 }
1175 if (arg == "-D" && argidx+1 < args.size()) {
1176 delay_target = "-D " + args[++argidx];
1177 continue;
1178 }
1179 if (arg == "-I" && argidx+1 < args.size()) {
1180 sop_inputs = "-I " + args[++argidx];
1181 continue;
1182 }
1183 if (arg == "-P" && argidx+1 < args.size()) {
1184 sop_products = "-P " + args[++argidx];
1185 continue;
1186 }
1187 if (arg == "-S" && argidx+1 < args.size()) {
1188 lutin_shared = "-S " + args[++argidx];
1189 continue;
1190 }
1191 if (arg == "-lut" && argidx+1 < args.size()) {
1192 string arg = args[++argidx];
1193 size_t pos = arg.find_first_of(':');
1194 int lut_mode = 0, lut_mode2 = 0;
1195 if (pos != string::npos) {
1196 lut_mode = atoi(arg.substr(0, pos).c_str());
1197 lut_mode2 = atoi(arg.substr(pos+1).c_str());
1198 } else {
1199 lut_mode = atoi(arg.c_str());
1200 lut_mode2 = lut_mode;
1201 }
1202 lut_costs.clear();
1203 for (int i = 0; i < lut_mode; i++)
1204 lut_costs.push_back(1);
1205 for (int i = lut_mode; i < lut_mode2; i++)
1206 lut_costs.push_back(2 << (i - lut_mode));
1207 continue;
1208 }
1209 if (arg == "-luts" && argidx+1 < args.size()) {
1210 lut_costs.clear();
1211 for (auto &tok : split_tokens(args[++argidx], ",")) {
1212 auto parts = split_tokens(tok, ":");
1213 if (GetSize(parts) == 0 && !lut_costs.empty())
1214 lut_costs.push_back(lut_costs.back());
1215 else if (GetSize(parts) == 1)
1216 lut_costs.push_back(atoi(parts.at(0).c_str()));
1217 else if (GetSize(parts) == 2)
1218 while (GetSize(lut_costs) < atoi(parts.at(0).c_str()))
1219 lut_costs.push_back(atoi(parts.at(1).c_str()));
1220 else
1221 log_cmd_error("Invalid -luts syntax.\n");
1222 }
1223 continue;
1224 }
1225 if (arg == "-sop") {
1226 sop_mode = true;
1227 continue;
1228 }
1229 if (arg == "-mux4") {
1230 map_mux4 = true;
1231 continue;
1232 }
1233 if (arg == "-mux8") {
1234 map_mux8 = true;
1235 continue;
1236 }
1237 if (arg == "-mux16") {
1238 map_mux16 = true;
1239 continue;
1240 }
1241 if (arg == "-dress") {
1242 // TODO
1243 //abc_dress = true;
1244 continue;
1245 }
1246 if (arg == "-g" && argidx+1 < args.size()) {
1247 for (auto g : split_tokens(args[++argidx], ",")) {
1248 vector<string> gate_list;
1249 bool remove_gates = false;
1250 if (GetSize(g) > 0 && g[0] == '-') {
1251 remove_gates = true;
1252 g = g.substr(1);
1253 }
1254 if (g == "AND") goto ok_gate;
1255 if (g == "NAND") goto ok_gate;
1256 if (g == "OR") goto ok_gate;
1257 if (g == "NOR") goto ok_gate;
1258 if (g == "XOR") goto ok_gate;
1259 if (g == "XNOR") goto ok_gate;
1260 if (g == "ANDNOT") goto ok_gate;
1261 if (g == "ORNOT") goto ok_gate;
1262 if (g == "MUX") goto ok_gate;
1263 if (g == "AOI3") goto ok_gate;
1264 if (g == "OAI3") goto ok_gate;
1265 if (g == "AOI4") goto ok_gate;
1266 if (g == "OAI4") goto ok_gate;
1267 if (g == "simple") {
1268 gate_list.push_back("AND");
1269 gate_list.push_back("OR");
1270 gate_list.push_back("XOR");
1271 gate_list.push_back("MUX");
1272 goto ok_alias;
1273 }
1274 if (g == "cmos2") {
1275 gate_list.push_back("NAND");
1276 gate_list.push_back("NOR");
1277 goto ok_alias;
1278 }
1279 if (g == "cmos3") {
1280 gate_list.push_back("NAND");
1281 gate_list.push_back("NOR");
1282 gate_list.push_back("AOI3");
1283 gate_list.push_back("OAI3");
1284 goto ok_alias;
1285 }
1286 if (g == "cmos4") {
1287 gate_list.push_back("NAND");
1288 gate_list.push_back("NOR");
1289 gate_list.push_back("AOI3");
1290 gate_list.push_back("OAI3");
1291 gate_list.push_back("AOI4");
1292 gate_list.push_back("OAI4");
1293 goto ok_alias;
1294 }
1295 if (g == "gates") {
1296 gate_list.push_back("AND");
1297 gate_list.push_back("NAND");
1298 gate_list.push_back("OR");
1299 gate_list.push_back("NOR");
1300 gate_list.push_back("XOR");
1301 gate_list.push_back("XNOR");
1302 gate_list.push_back("ANDNOT");
1303 gate_list.push_back("ORNOT");
1304 goto ok_alias;
1305 }
1306 if (g == "aig") {
1307 gate_list.push_back("AND");
1308 gate_list.push_back("NAND");
1309 gate_list.push_back("OR");
1310 gate_list.push_back("NOR");
1311 gate_list.push_back("ANDNOT");
1312 gate_list.push_back("ORNOT");
1313 goto ok_alias;
1314 }
1315 cmd_error(args, argidx, stringf("Unsupported gate type: %s", g.c_str()));
1316 ok_gate:
1317 gate_list.push_back(g);
1318 ok_alias:
1319 for (auto gate : gate_list) {
1320 if (remove_gates)
1321 enabled_gates.erase(gate);
1322 else
1323 enabled_gates.insert(gate);
1324 }
1325 }
1326 continue;
1327 }
1328 if (arg == "-fast") {
1329 fast_mode = true;
1330 continue;
1331 }
1332 if (arg == "-dff") {
1333 dff_mode = true;
1334 continue;
1335 }
1336 if (arg == "-clk" && argidx+1 < args.size()) {
1337 clk_str = args[++argidx];
1338 dff_mode = true;
1339 continue;
1340 }
1341 if (arg == "-keepff") {
1342 keepff = true;
1343 continue;
1344 }
1345 if (arg == "-nocleanup") {
1346 cleanup = false;
1347 continue;
1348 }
1349 if (arg == "-showtmp") {
1350 show_tempdir = true;
1351 continue;
1352 }
1353 if (arg == "-markgroups") {
1354 markgroups = true;
1355 continue;
1356 }
1357 break;
1358 }
1359 extra_args(args, argidx, design);
1360
1361 if (!lut_costs.empty() && !liberty_file.empty())
1362 log_cmd_error("Got -lut and -liberty! This two options are exclusive.\n");
1363 if (!constr_file.empty() && liberty_file.empty())
1364 log_cmd_error("Got -constr but no -liberty!\n");
1365
1366 for (auto mod : design->selected_modules())
1367 {
1368 if (mod->processes.size() > 0) {
1369 log("Skipping module %s as it contains processes.\n", log_id(mod));
1370 continue;
1371 }
1372
1373 assign_map.set(mod);
1374 signal_init.clear();
1375
1376 for (Wire *wire : mod->wires())
1377 if (wire->attributes.count("\\init")) {
1378 SigSpec initsig = assign_map(wire);
1379 Const initval = wire->attributes.at("\\init");
1380 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
1381 switch (initval[i]) {
1382 case State::S0:
1383 signal_init[initsig[i]] = State::S0;
1384 break;
1385 case State::S1:
1386 signal_init[initsig[i]] = State::S0;
1387 break;
1388 default:
1389 break;
1390 }
1391 }
1392
1393 if (!dff_mode || !clk_str.empty()) {
1394 abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
1395 delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode);
1396 continue;
1397 }
1398
1399 CellTypes ct(design);
1400
1401 std::vector<RTLIL::Cell*> all_cells = mod->selected_cells();
1402 std::set<RTLIL::Cell*> unassigned_cells(all_cells.begin(), all_cells.end());
1403
1404 std::set<RTLIL::Cell*> expand_queue, next_expand_queue;
1405 std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
1406 std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
1407
1408 typedef tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
1409 std::map<clkdomain_t, std::vector<RTLIL::Cell*>> assigned_cells;
1410 std::map<RTLIL::Cell*, clkdomain_t> assigned_cells_reverse;
1411
1412 std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
1413 std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
1414
1415 for (auto cell : all_cells)
1416 {
1417 clkdomain_t key;
1418
1419 for (auto &conn : cell->connections())
1420 for (auto bit : conn.second) {
1421 bit = assign_map(bit);
1422 if (bit.wire != nullptr) {
1423 cell_to_bit[cell].insert(bit);
1424 bit_to_cell[bit].insert(cell);
1425 if (ct.cell_input(cell->type, conn.first)) {
1426 cell_to_bit_up[cell].insert(bit);
1427 bit_to_cell_down[bit].insert(cell);
1428 }
1429 if (ct.cell_output(cell->type, conn.first)) {
1430 cell_to_bit_down[cell].insert(bit);
1431 bit_to_cell_up[bit].insert(cell);
1432 }
1433 }
1434 }
1435
1436 if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
1437 {
1438 key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
1439 }
1440 else
1441 if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
1442 {
1443 bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_";
1444 bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_";
1445 key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E")));
1446 }
1447 else
1448 continue;
1449
1450 unassigned_cells.erase(cell);
1451 expand_queue.insert(cell);
1452 expand_queue_up.insert(cell);
1453 expand_queue_down.insert(cell);
1454
1455 assigned_cells[key].push_back(cell);
1456 assigned_cells_reverse[cell] = key;
1457 }
1458
1459 while (!expand_queue_up.empty() || !expand_queue_down.empty())
1460 {
1461 if (!expand_queue_up.empty())
1462 {
1463 RTLIL::Cell *cell = *expand_queue_up.begin();
1464 clkdomain_t key = assigned_cells_reverse.at(cell);
1465 expand_queue_up.erase(cell);
1466
1467 for (auto bit : cell_to_bit_up[cell])
1468 for (auto c : bit_to_cell_up[bit])
1469 if (unassigned_cells.count(c)) {
1470 unassigned_cells.erase(c);
1471 next_expand_queue_up.insert(c);
1472 assigned_cells[key].push_back(c);
1473 assigned_cells_reverse[c] = key;
1474 expand_queue.insert(c);
1475 }
1476 }
1477
1478 if (!expand_queue_down.empty())
1479 {
1480 RTLIL::Cell *cell = *expand_queue_down.begin();
1481 clkdomain_t key = assigned_cells_reverse.at(cell);
1482 expand_queue_down.erase(cell);
1483
1484 for (auto bit : cell_to_bit_down[cell])
1485 for (auto c : bit_to_cell_down[bit])
1486 if (unassigned_cells.count(c)) {
1487 unassigned_cells.erase(c);
1488 next_expand_queue_up.insert(c);
1489 assigned_cells[key].push_back(c);
1490 assigned_cells_reverse[c] = key;
1491 expand_queue.insert(c);
1492 }
1493 }
1494
1495 if (expand_queue_up.empty() && expand_queue_down.empty()) {
1496 expand_queue_up.swap(next_expand_queue_up);
1497 expand_queue_down.swap(next_expand_queue_down);
1498 }
1499 }
1500
1501 while (!expand_queue.empty())
1502 {
1503 RTLIL::Cell *cell = *expand_queue.begin();
1504 clkdomain_t key = assigned_cells_reverse.at(cell);
1505 expand_queue.erase(cell);
1506
1507 for (auto bit : cell_to_bit.at(cell)) {
1508 for (auto c : bit_to_cell[bit])
1509 if (unassigned_cells.count(c)) {
1510 unassigned_cells.erase(c);
1511 next_expand_queue.insert(c);
1512 assigned_cells[key].push_back(c);
1513 assigned_cells_reverse[c] = key;
1514 }
1515 bit_to_cell[bit].clear();
1516 }
1517
1518 if (expand_queue.empty())
1519 expand_queue.swap(next_expand_queue);
1520 }
1521
1522 clkdomain_t key(true, RTLIL::SigSpec(), true, RTLIL::SigSpec());
1523 for (auto cell : unassigned_cells) {
1524 assigned_cells[key].push_back(cell);
1525 assigned_cells_reverse[cell] = key;
1526 }
1527
1528 log_header(design, "Summary of detected clock domains:\n");
1529 for (auto &it : assigned_cells)
1530 log(" %d cells in clk=%s%s, en=%s%s\n", GetSize(it.second),
1531 std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
1532 std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
1533
1534 for (auto &it : assigned_cells) {
1535 clk_polarity = std::get<0>(it.first);
1536 clk_sig = assign_map(std::get<1>(it.first));
1537 en_polarity = std::get<2>(it.first);
1538 en_sig = assign_map(std::get<3>(it.first));
1539 abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
1540 keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode);
1541 assign_map.set(mod);
1542 }
1543 }
1544
1545 Pass::call(design, "clean");
1546
1547 assign_map.clear();
1548 signal_map.clear();
1549 signal_init.clear();
1550 pi_map.clear();
1551 po_map.clear();
1552
1553 log_pop();
1554 }
1555 } Abc9Pass;
1556
1557 PRIVATE_NAMESPACE_END