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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
[yosys.git] / passes / techmap / abc9.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // [[CITE]] ABC
22 // Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
23 // http://www.eecs.berkeley.edu/~alanmi/abc/
24
25 #if 0
26 // Based on &flow3 - better QoR but more experimental
27 #define ABC_COMMAND_LUT "&st; &ps -l; &sweep -v; &scorr; " \
28 "&st; &if {W}; &save; &st; &syn2; &if {W} -v; &save; &load; "\
29 "&st; &if -g -K 6; &dch -f; &if {W} -v; &save; &load; "\
30 "&st; &if -g -K 6; &synch2; &if {W} -v; &save; &load; "\
31 "&mfs; &ps -l"
32 #else
33 #define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v; &mfs; &ps -l"
34 #endif
35
36
37 #define ABC_FAST_COMMAND_LUT "&st; &if {W} {D}"
38
39 #include "kernel/register.h"
40 #include "kernel/sigtools.h"
41 #include "kernel/celltypes.h"
42 #include "kernel/cost.h"
43 #include "kernel/log.h"
44 #include <stdlib.h>
45 #include <stdio.h>
46 #include <string.h>
47 #include <cerrno>
48 #include <sstream>
49 #include <climits>
50
51 #ifndef _WIN32
52 # include <unistd.h>
53 # include <dirent.h>
54 #endif
55
56 #include "frontends/aiger/aigerparse.h"
57 #include "kernel/utils.h"
58
59 #ifdef YOSYS_LINK_ABC
60 extern "C" int Abc_RealMain(int argc, char *argv[]);
61 #endif
62
63 USING_YOSYS_NAMESPACE
64 PRIVATE_NAMESPACE_BEGIN
65
66 bool markgroups;
67 int map_autoidx;
68
69 inline std::string remap_name(RTLIL::IdString abc9_name)
70 {
71 return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
72 }
73
74 void handle_loops(RTLIL::Design *design, RTLIL::Module *module)
75 {
76 Pass::call(design, "scc -set_attr abc9_scc_id {} % w:*");
77
78 // For every unique SCC found, (arbitrarily) find the first
79 // cell in the component, and select (and mark) all its output
80 // wires
81 pool<RTLIL::Const> ids_seen;
82 for (auto cell : module->cells()) {
83 auto it = cell->attributes.find(ID(abc9_scc_id));
84 if (it != cell->attributes.end()) {
85 auto r = ids_seen.insert(it->second);
86 if (r.second) {
87 for (auto &c : cell->connections_) {
88 if (c.second.is_fully_const()) continue;
89 if (cell->output(c.first)) {
90 SigBit b = c.second.as_bit();
91 Wire *w = b.wire;
92 log_assert(!w->port_input);
93 w->port_input = true;
94 w = module->wire(stringf("%s.abci", w->name.c_str()));
95 if (!w) {
96 w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
97 w->port_output = true;
98 }
99 else {
100 log_assert(w->port_input);
101 log_assert(b.offset < GetSize(w));
102 }
103 w->set_bool_attribute(ID(abc9_scc_break));
104 module->swap_names(b.wire, w);
105 c.second = RTLIL::SigBit(w, b.offset);
106 }
107 }
108 }
109 cell->attributes.erase(it);
110 }
111 }
112
113 module->fixup_ports();
114 }
115
116 std::string add_echos_to_abc9_cmd(std::string str)
117 {
118 std::string new_str, token;
119 for (size_t i = 0; i < str.size(); i++) {
120 token += str[i];
121 if (str[i] == ';') {
122 while (i+1 < str.size() && str[i+1] == ' ')
123 i++;
124 new_str += "echo + " + token + " " + token + " ";
125 token.clear();
126 }
127 }
128
129 if (!token.empty()) {
130 if (!new_str.empty())
131 new_str += "echo + " + token + "; ";
132 new_str += token;
133 }
134
135 return new_str;
136 }
137
138 std::string fold_abc9_cmd(std::string str)
139 {
140 std::string token, new_str = " ";
141 int char_counter = 10;
142
143 for (size_t i = 0; i <= str.size(); i++) {
144 if (i < str.size())
145 token += str[i];
146 if (i == str.size() || str[i] == ';') {
147 if (char_counter + token.size() > 75)
148 new_str += "\n ", char_counter = 14;
149 new_str += token, char_counter += token.size();
150 token.clear();
151 }
152 }
153
154 return new_str;
155 }
156
157 std::string replace_tempdir(std::string text, std::string tempdir_name, bool show_tempdir)
158 {
159 if (show_tempdir)
160 return text;
161
162 while (1) {
163 size_t pos = text.find(tempdir_name);
164 if (pos == std::string::npos)
165 break;
166 text = text.substr(0, pos) + "<abc-temp-dir>" + text.substr(pos + GetSize(tempdir_name));
167 }
168
169 std::string selfdir_name = proc_self_dirname();
170 if (selfdir_name != "/") {
171 while (1) {
172 size_t pos = text.find(selfdir_name);
173 if (pos == std::string::npos)
174 break;
175 text = text.substr(0, pos) + "<yosys-exe-dir>/" + text.substr(pos + GetSize(selfdir_name));
176 }
177 }
178
179 return text;
180 }
181
182 struct abc9_output_filter
183 {
184 bool got_cr;
185 int escape_seq_state;
186 std::string linebuf;
187 std::string tempdir_name;
188 bool show_tempdir;
189
190 abc9_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir)
191 {
192 got_cr = false;
193 escape_seq_state = 0;
194 }
195
196 void next_char(char ch)
197 {
198 if (escape_seq_state == 0 && ch == '\033') {
199 escape_seq_state = 1;
200 return;
201 }
202 if (escape_seq_state == 1) {
203 escape_seq_state = ch == '[' ? 2 : 0;
204 return;
205 }
206 if (escape_seq_state == 2) {
207 if ((ch < '0' || '9' < ch) && ch != ';')
208 escape_seq_state = 0;
209 return;
210 }
211 escape_seq_state = 0;
212 if (ch == '\r') {
213 got_cr = true;
214 return;
215 }
216 if (ch == '\n') {
217 log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir).c_str());
218 got_cr = false, linebuf.clear();
219 return;
220 }
221 if (got_cr)
222 got_cr = false, linebuf.clear();
223 linebuf += ch;
224 }
225
226 void next_line(const std::string &line)
227 {
228 //int pi, po;
229 //if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
230 // log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
231 // pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???",
232 // po, po_map.count(po) ? po_map.at(po).c_str() : "???");
233 // return;
234 //}
235
236 for (char ch : line)
237 next_char(ch);
238 }
239 };
240
241 void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string script_file, std::string exe_file,
242 bool cleanup, vector<int> lut_costs, bool /*dff_mode*/, std::string /*clk_str*/,
243 bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
244 bool show_tempdir, std::string box_file, std::string lut_file,
245 std::string wire_delay, const dict<int,IdString> &box_lookup, bool nomfs
246 )
247 {
248 map_autoidx = autoidx++;
249
250 std::string tempdir_name = "/tmp/yosys-abc-XXXXXX";
251 if (!cleanup)
252 tempdir_name[0] = tempdir_name[4] = '_';
253 tempdir_name = make_temp_dir(tempdir_name);
254 log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
255 module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
256
257 std::string abc9_script;
258
259 if (!lut_costs.empty()) {
260 abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
261 if (!box_file.empty())
262 abc9_script += stringf("read_box -v %s; ", box_file.c_str());
263 }
264 else
265 if (!lut_file.empty()) {
266 abc9_script += stringf("read_lut %s; ", lut_file.c_str());
267 if (!box_file.empty())
268 abc9_script += stringf("read_box -v %s; ", box_file.c_str());
269 }
270 else
271 log_abort();
272
273 abc9_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
274
275 if (!script_file.empty()) {
276 if (script_file[0] == '+') {
277 for (size_t i = 1; i < script_file.size(); i++)
278 if (script_file[i] == '\'')
279 abc9_script += "'\\''";
280 else if (script_file[i] == ',')
281 abc9_script += " ";
282 else
283 abc9_script += script_file[i];
284 } else
285 abc9_script += stringf("source %s", script_file.c_str());
286 } else if (!lut_costs.empty() || !lut_file.empty()) {
287 //bool all_luts_cost_same = true;
288 //for (int this_cost : lut_costs)
289 // if (this_cost != lut_costs.front())
290 // all_luts_cost_same = false;
291 abc9_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
292 //if (all_luts_cost_same && !fast_mode)
293 // abc9_script += "; lutpack {S}";
294 } else
295 log_abort();
296
297 //if (script_file.empty() && !delay_target.empty())
298 // for (size_t pos = abc9_script.find("dretime;"); pos != std::string::npos; pos = abc9_script.find("dretime;", pos+1))
299 // abc9_script = abc9_script.substr(0, pos) + "dretime; retime -o {D};" + abc9_script.substr(pos+8);
300
301 for (size_t pos = abc9_script.find("{D}"); pos != std::string::npos; pos = abc9_script.find("{D}", pos))
302 abc9_script = abc9_script.substr(0, pos) + delay_target + abc9_script.substr(pos+3);
303
304 //for (size_t pos = abc9_script.find("{S}"); pos != std::string::npos; pos = abc9_script.find("{S}", pos))
305 // abc9_script = abc9_script.substr(0, pos) + lutin_shared + abc9_script.substr(pos+3);
306
307 for (size_t pos = abc9_script.find("{W}"); pos != std::string::npos; pos = abc9_script.find("{W}", pos))
308 abc9_script = abc9_script.substr(0, pos) + wire_delay + abc9_script.substr(pos+3);
309
310 if (nomfs)
311 for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
312 abc9_script = abc9_script.erase(pos, strlen("&mfs"));
313
314 abc9_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
315 abc9_script = add_echos_to_abc9_cmd(abc9_script);
316
317 for (size_t i = 0; i+1 < abc9_script.size(); i++)
318 if (abc9_script[i] == ';' && abc9_script[i+1] == ' ')
319 abc9_script[i+1] = '\n';
320
321 FILE *f = fopen(stringf("%s/abc.script", tempdir_name.c_str()).c_str(), "wt");
322 fprintf(f, "%s\n", abc9_script.c_str());
323 fclose(f);
324
325 bool count_output = false;
326 for (auto port_name : module->ports) {
327 RTLIL::Wire *port_wire = module->wire(port_name);
328 log_assert(port_wire);
329 if (port_wire->port_output) {
330 count_output = true;
331 break;
332 }
333 }
334
335 log_push();
336
337 if (count_output)
338 {
339 handle_loops(design, module);
340
341 Pass::call(design, "aigmap -select");
342
343 //log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
344 // count_gates, GetSize(signal_list), count_input, count_output);
345
346 Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
347
348 std::string buffer;
349 std::ifstream ifs;
350 #if 0
351 buffer = stringf("%s/%s", tempdir_name.c_str(), "input.xaig");
352 ifs.open(buffer);
353 if (ifs.fail())
354 log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
355 buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
356 log_assert(!design->module(ID($__abc9__)));
357 {
358 AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
359 reader.parse_xaiger();
360 }
361 ifs.close();
362 Pass::call(design, stringf("write_verilog -noexpr -norename"));
363 design->remove(design->module(ID($__abc9__)));
364 #endif
365
366 // Now 'unexpose' those wires by undoing
367 // the expose operation -- remove them from PO/PI
368 // and re-connecting them back together
369 for (auto wire : module->wires()) {
370 auto it = wire->attributes.find(ID(abc9_scc_break));
371 if (it != wire->attributes.end()) {
372 wire->attributes.erase(it);
373 log_assert(wire->port_output);
374 wire->port_output = false;
375 RTLIL::Wire *i_wire = module->wire(wire->name.str() + ".abci");
376 log_assert(i_wire);
377 log_assert(i_wire->port_input);
378 i_wire->port_input = false;
379 module->connect(i_wire, wire);
380 }
381 }
382 module->fixup_ports();
383
384 log_header(design, "Executing ABC9.\n");
385
386 if (!lut_costs.empty()) {
387 buffer = stringf("%s/lutdefs.txt", tempdir_name.c_str());
388 f = fopen(buffer.c_str(), "wt");
389 if (f == NULL)
390 log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
391 for (int i = 0; i < GetSize(lut_costs); i++)
392 fprintf(f, "%d %d.00 1.00\n", i+1, lut_costs.at(i));
393 fclose(f);
394 }
395
396 buffer = stringf("%s -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
397 log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
398
399 #ifndef YOSYS_LINK_ABC
400 abc9_output_filter filt(tempdir_name, show_tempdir);
401 int ret = run_command(buffer, std::bind(&abc9_output_filter::next_line, filt, std::placeholders::_1));
402 #else
403 // These needs to be mutable, supposedly due to getopt
404 char *abc9_argv[5];
405 string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str());
406 abc9_argv[0] = strdup(exe_file.c_str());
407 abc9_argv[1] = strdup("-s");
408 abc9_argv[2] = strdup("-f");
409 abc9_argv[3] = strdup(tmp_script_name.c_str());
410 abc9_argv[4] = 0;
411 int ret = Abc_RealMain(4, abc9_argv);
412 free(abc9_argv[0]);
413 free(abc9_argv[1]);
414 free(abc9_argv[2]);
415 free(abc9_argv[3]);
416 #endif
417 if (ret != 0)
418 log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
419
420 buffer = stringf("%s/%s", tempdir_name.c_str(), "output.aig");
421 ifs.open(buffer, std::ifstream::binary);
422 if (ifs.fail())
423 log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
424
425 buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
426 log_assert(!design->module(ID($__abc9__)));
427
428 AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
429 reader.parse_xaiger(box_lookup);
430 ifs.close();
431
432 #if 0
433 Pass::call(design, stringf("write_verilog -noexpr -norename"));
434 #endif
435
436 log_header(design, "Re-integrating ABC9 results.\n");
437 RTLIL::Module *mapped_mod = design->module(ID($__abc9__));
438 if (mapped_mod == NULL)
439 log_error("ABC output file does not contain a module `$__abc9__'.\n");
440
441 pool<RTLIL::SigBit> output_bits;
442 for (auto &it : mapped_mod->wires_) {
443 RTLIL::Wire *w = it.second;
444 RTLIL::Wire *remap_wire = module->addWire(remap_name(w->name), GetSize(w));
445 if (markgroups) remap_wire->attributes[ID(abcgroup)] = map_autoidx;
446 if (w->port_output) {
447 RTLIL::Wire *wire = module->wire(w->name);
448 log_assert(wire);
449 for (int i = 0; i < GetSize(w); i++)
450 output_bits.insert({wire, i});
451 }
452 }
453
454 for (auto &it : module->connections_) {
455 auto &signal = it.first;
456 auto bits = signal.bits();
457 for (auto &b : bits)
458 if (output_bits.count(b))
459 b = module->addWire(NEW_ID);
460 signal = std::move(bits);
461 }
462
463 dict<IdString, bool> abc9_box;
464 vector<RTLIL::Cell*> boxes;
465 for (auto cell : module->selected_cells()) {
466 if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_))) {
467 module->remove(cell);
468 continue;
469 }
470 auto jt = abc9_box.find(cell->type);
471 if (jt == abc9_box.end()) {
472 RTLIL::Module* box_module = design->module(cell->type);
473 jt = abc9_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(abc9_box_id)))).first;
474 }
475 if (jt->second)
476 boxes.emplace_back(cell);
477 }
478
479 dict<SigBit, pool<IdString>> bit_drivers, bit_users;
480 TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
481 dict<RTLIL::Cell*,RTLIL::Cell*> not2drivers;
482 dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks;
483
484 std::map<IdString, int> cell_stats;
485 for (auto mapped_cell : mapped_mod->cells())
486 {
487 toposort.node(mapped_cell->name);
488
489 RTLIL::Cell *cell = nullptr;
490 if (mapped_cell->type == ID($_NOT_)) {
491 RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A);
492 RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y);
493 bit_users[a_bit].insert(mapped_cell->name);
494 bit_drivers[y_bit].insert(mapped_cell->name);
495
496 if (!a_bit.wire) {
497 mapped_cell->setPort(ID::Y, module->addWire(NEW_ID));
498 RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
499 log_assert(wire);
500 module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
501 }
502 else if (!lut_costs.empty() || !lut_file.empty()) {
503 RTLIL::Cell* driver_lut = nullptr;
504 // ABC can return NOT gates that drive POs
505 if (!a_bit.wire->port_input) {
506 // If it's not a NOT gate that that comes from a PI directly,
507 // find the driver LUT and clone that to guarantee that we won't
508 // increase the max logic depth
509 // (TODO: Optimise by not cloning unless will increase depth)
510 RTLIL::IdString driver_name;
511 if (GetSize(a_bit.wire) == 1)
512 driver_name = stringf("%s$lut", a_bit.wire->name.c_str());
513 else
514 driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset);
515 driver_lut = mapped_mod->cell(driver_name);
516 }
517
518 if (!driver_lut) {
519 // If a driver couldn't be found (could be from PI or box CI)
520 // then implement using a LUT
521 cell = module->addLut(remap_name(stringf("%s$lut", mapped_cell->name.c_str())),
522 RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
523 RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
524 RTLIL::Const::from_string("01"));
525 bit2sinks[cell->getPort(ID::A)].push_back(cell);
526 cell_stats[ID($lut)]++;
527 }
528 else
529 not2drivers[mapped_cell] = driver_lut;
530 continue;
531 }
532 else
533 log_abort();
534 if (cell && markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
535 continue;
536 }
537 cell_stats[mapped_cell->type]++;
538
539 RTLIL::Cell *existing_cell = nullptr;
540 if (mapped_cell->type.in(ID($lut), ID($__ABC9_FF_))) {
541 if (mapped_cell->type == ID($lut) &&
542 GetSize(mapped_cell->getPort(ID::A)) == 1 &&
543 mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
544 SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID::A).as_wire()->name));
545 SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID::Y).as_wire()->name));
546 module->connect(my_y, my_a);
547 if (markgroups) mapped_cell->attributes[ID(abcgroup)] = map_autoidx;
548 log_abort();
549 continue;
550 }
551 cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
552 }
553 else {
554 existing_cell = module->cell(mapped_cell->name);
555 log_assert(existing_cell);
556 cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
557 }
558
559 if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
560 if (existing_cell) {
561 cell->parameters = existing_cell->parameters;
562 cell->attributes = existing_cell->attributes;
563 }
564 else {
565 cell->parameters = mapped_cell->parameters;
566 cell->attributes = mapped_cell->attributes;
567 }
568
569 RTLIL::Module* box_module = design->module(mapped_cell->type);
570 auto abc9_flop = box_module && box_module->attributes.count("\\abc9_flop");
571 for (auto &conn : mapped_cell->connections()) {
572 RTLIL::SigSpec newsig;
573 for (auto c : conn.second.chunks()) {
574 if (c.width == 0)
575 continue;
576 //log_assert(c.width == 1);
577 if (c.wire)
578 c.wire = module->wires_.at(remap_name(c.wire->name));
579 newsig.append(c);
580 }
581 cell->setPort(conn.first, newsig);
582
583 if (!abc9_flop) {
584 if (cell->input(conn.first)) {
585 for (auto i : newsig)
586 bit2sinks[i].push_back(cell);
587 for (auto i : conn.second)
588 bit_users[i].insert(mapped_cell->name);
589 }
590 if (cell->output(conn.first))
591 for (auto i : conn.second)
592 bit_drivers[i].insert(mapped_cell->name);
593 }
594 }
595 }
596
597 for (auto existing_cell : boxes) {
598 Cell *cell = module->cell(remap_name(existing_cell->name));
599 if (cell) {
600 for (auto &conn : existing_cell->connections()) {
601 if (!conn.second.is_wire())
602 continue;
603 Wire *wire = conn.second.as_wire();
604 if (!wire->get_bool_attribute(ID(abc9_padding)))
605 continue;
606 cell->unsetPort(conn.first);
607 log_debug("Dropping padded port connection for %s (%s) .%s (%s )\n", log_id(cell), cell->type.c_str(), log_id(conn.first), log_signal(conn.second));
608 }
609 module->swap_names(cell, existing_cell);
610 }
611 module->remove(existing_cell);
612 }
613
614 // Copy connections (and rename) from mapped_mod to module
615 for (auto conn : mapped_mod->connections()) {
616 if (!conn.first.is_fully_const()) {
617 auto chunks = conn.first.chunks();
618 for (auto &c : chunks)
619 c.wire = module->wires_.at(remap_name(c.wire->name));
620 conn.first = std::move(chunks);
621 }
622 if (!conn.second.is_fully_const()) {
623 auto chunks = conn.second.chunks();
624 for (auto &c : chunks)
625 if (c.wire)
626 c.wire = module->wires_.at(remap_name(c.wire->name));
627 conn.second = std::move(chunks);
628 }
629 module->connect(conn);
630 }
631
632 for (auto &it : cell_stats)
633 log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
634 int in_wires = 0, out_wires = 0;
635
636 // Stitch in mapped_mod's inputs/outputs into module
637 for (auto port : mapped_mod->ports) {
638 RTLIL::Wire *w = mapped_mod->wire(port);
639 RTLIL::Wire *wire = module->wire(port);
640 log_assert(wire);
641 RTLIL::Wire *remap_wire = module->wire(remap_name(port));
642 RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
643 log_assert(GetSize(signal) >= GetSize(remap_wire));
644
645 RTLIL::SigSig conn;
646 if (w->port_output) {
647 conn.first = signal;
648 conn.second = remap_wire;
649 out_wires++;
650 module->connect(conn);
651 }
652 else if (w->port_input) {
653 conn.first = remap_wire;
654 conn.second = signal;
655 in_wires++;
656 module->connect(conn);
657 }
658 }
659
660 for (auto &it : bit_users)
661 if (bit_drivers.count(it.first))
662 for (auto driver_cell : bit_drivers.at(it.first))
663 for (auto user_cell : it.second)
664 toposort.edge(driver_cell, user_cell);
665 bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
666 log_assert(no_loops);
667
668 for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {
669 RTLIL::Cell *not_cell = mapped_mod->cell(*ii);
670 log_assert(not_cell);
671 if (not_cell->type != ID($_NOT_))
672 continue;
673 auto it = not2drivers.find(not_cell);
674 if (it == not2drivers.end())
675 continue;
676 RTLIL::Cell *driver_lut = it->second;
677 RTLIL::SigBit a_bit = not_cell->getPort(ID::A);
678 RTLIL::SigBit y_bit = not_cell->getPort(ID::Y);
679 RTLIL::Const driver_mask;
680
681 a_bit.wire = module->wires_.at(remap_name(a_bit.wire->name));
682 y_bit.wire = module->wires_.at(remap_name(y_bit.wire->name));
683
684 auto jt = bit2sinks.find(a_bit);
685 if (jt == bit2sinks.end())
686 goto clone_lut;
687
688 for (auto sink_cell : jt->second)
689 if (sink_cell->type != ID($lut))
690 goto clone_lut;
691
692 // Push downstream LUTs past inverter
693 for (auto sink_cell : jt->second) {
694 SigSpec A = sink_cell->getPort(ID::A);
695 RTLIL::Const mask = sink_cell->getParam(ID(LUT));
696 int index = 0;
697 for (; index < GetSize(A); index++)
698 if (A[index] == a_bit)
699 break;
700 log_assert(index < GetSize(A));
701 int i = 0;
702 while (i < GetSize(mask)) {
703 for (int j = 0; j < (1 << index); j++)
704 std::swap(mask[i+j], mask[i+j+(1 << index)]);
705 i += 1 << (index+1);
706 }
707 A[index] = y_bit;
708 sink_cell->setPort(ID::A, A);
709 sink_cell->setParam(ID(LUT), mask);
710 }
711
712 // Since we have rewritten all sinks (which we know
713 // to be only LUTs) to be after the inverter, we can
714 // go ahead and clone the LUT with the expectation
715 // that the original driving LUT will become dangling
716 // and get cleaned away
717 clone_lut:
718 driver_mask = driver_lut->getParam(ID(LUT));
719 for (auto &b : driver_mask.bits) {
720 if (b == RTLIL::State::S0) b = RTLIL::State::S1;
721 else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
722 }
723 auto cell = module->addLut(NEW_ID,
724 driver_lut->getPort(ID::A),
725 y_bit,
726 driver_mask);
727 for (auto &bit : cell->connections_.at(ID::A)) {
728 bit.wire = module->wires_.at(remap_name(bit.wire->name));
729 bit2sinks[bit].push_back(cell);
730 }
731 }
732
733 //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
734 log("ABC RESULTS: input signals: %8d\n", in_wires);
735 log("ABC RESULTS: output signals: %8d\n", out_wires);
736
737 design->remove(mapped_mod);
738 }
739 else
740 {
741 log("Don't call ABC as there is nothing to map.\n");
742 }
743
744 if (cleanup)
745 {
746 log("Removing temp directory.\n");
747 remove_directory(tempdir_name);
748 }
749
750 log_pop();
751 }
752
753 struct Abc9Pass : public Pass {
754 Abc9Pass() : Pass("abc9", "use ABC9 for technology mapping") { }
755 void help() YS_OVERRIDE
756 {
757 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
758 log("\n");
759 log(" abc9 [options] [selection]\n");
760 log("\n");
761 log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
762 log("library to a target architecture.\n");
763 log("\n");
764 log(" -exe <command>\n");
765 #ifdef ABCEXTERNAL
766 log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
767 #else
768 log(" use the specified command instead of \"<yosys-bindir>/yosys-abc\" to execute ABC.\n");
769 #endif
770 log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
771 log("\n");
772 log(" -script <file>\n");
773 log(" use the specified ABC script file instead of the default script.\n");
774 log("\n");
775 log(" if <file> starts with a plus sign (+), then the rest of the filename\n");
776 log(" string is interpreted as the command string to be passed to ABC. The\n");
777 log(" leading plus sign is removed and all commas (,) in the string are\n");
778 log(" replaced with blanks before the string is passed to ABC.\n");
779 log("\n");
780 log(" if no -script parameter is given, the following scripts are used:\n");
781 log("\n");
782 log(" for -lut/-luts (only one LUT size):\n");
783 log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT /*"; lutpack {S}"*/).c_str());
784 log("\n");
785 log(" for -lut/-luts (different LUT sizes):\n");
786 log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT).c_str());
787 log("\n");
788 log(" -fast\n");
789 log(" use different default scripts that are slightly faster (at the cost\n");
790 log(" of output quality):\n");
791 log("\n");
792 log(" for -lut/-luts:\n");
793 log("%s\n", fold_abc9_cmd(ABC_FAST_COMMAND_LUT).c_str());
794 log("\n");
795 log(" -D <picoseconds>\n");
796 log(" set delay target. the string {D} in the default scripts above is\n");
797 log(" replaced by this option when used, and an empty string otherwise\n");
798 log(" (indicating best possible delay).\n");
799 // log(" This also replaces 'dretime' with 'dretime; retime -o {D}' in the\n");
800 // log(" default scripts above.\n");
801 log("\n");
802 // log(" -S <num>\n");
803 // log(" maximum number of LUT inputs shared.\n");
804 // log(" (replaces {S} in the default scripts above, default: -S 1)\n");
805 // log("\n");
806 log(" -lut <width>\n");
807 log(" generate netlist using luts of (max) the specified width.\n");
808 log("\n");
809 log(" -lut <w1>:<w2>\n");
810 log(" generate netlist using luts of (max) the specified width <w2>. All\n");
811 log(" luts with width <= <w1> have constant cost. for luts larger than <w1>\n");
812 log(" the area cost doubles with each additional input bit. the delay cost\n");
813 log(" is still constant for all lut widths.\n");
814 log("\n");
815 log(" -lut <file>\n");
816 log(" pass this file with lut library to ABC.\n");
817 log("\n");
818 log(" -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..\n");
819 log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
820 log(" 2, 3, .. inputs.\n");
821 log("\n");
822 // log(" -dff\n");
823 // log(" also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many\n");
824 // log(" clock domains are automatically partitioned in clock domains and each\n");
825 // log(" domain is passed through ABC independently.\n");
826 // log("\n");
827 // log(" -clk [!]<clock-signal-name>[,[!]<enable-signal-name>]\n");
828 // log(" use only the specified clock domain. this is like -dff, but only FF\n");
829 // log(" cells that belong to the specified clock domain are used.\n");
830 // log("\n");
831 // log(" -keepff\n");
832 // log(" set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
833 // log(" them, for example for equivalence checking.)\n");
834 // log("\n");
835 log(" -nocleanup\n");
836 log(" when this option is used, the temporary files created by this pass\n");
837 log(" are not removed. this is useful for debugging.\n");
838 log("\n");
839 log(" -showtmp\n");
840 log(" print the temp dir name in log. usually this is suppressed so that the\n");
841 log(" command output is identical across runs.\n");
842 log("\n");
843 log(" -markgroups\n");
844 log(" set a 'abcgroup' attribute on all objects created by ABC. The value of\n");
845 log(" this attribute is a unique integer for each ABC process started. This\n");
846 log(" is useful for debugging the partitioning of clock domains.\n");
847 log("\n");
848 log(" -box <file>\n");
849 log(" pass this file with box library to ABC. Use with -lut.\n");
850 log("\n");
851 log("Note that this is a logic optimization pass within Yosys that is calling ABC\n");
852 log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
853 log("ABC on logic snippets extracted from your design. You will not get any useful\n");
854 log("output when passing an ABC script that writes a file. Instead write your full\n");
855 log("design as an XAIGER file with write_xaiger and then load that into ABC externally\n");
856 log("if you want to use ABC to convert your design into another format.\n");
857 log("\n");
858 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
859 log("Delay targets can also be specified on a per clock basis by attaching a\n");
860 log("'(* abc9_period = <int> *)' attribute onto clock wires (specifically, onto wires\n");
861 log("that appear inside any special '$abc9_clock' wires inserted by abc9_map.v). This\n");
862 log("can be achieved by modifying the source directly, or through a `setattr`\n");
863 log("invocation. Since such attributes cannot yet be propagated through a\n");
864 log("hierarchical design (whether or not it has been uniquified) it is recommended\n");
865 log("that the design be flattened when using this feature.\n");
866 log("\n");
867 log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
868 log("\n");
869 }
870 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
871 {
872 log_header(design, "Executing ABC9 pass (technology mapping using ABC9).\n");
873 log_push();
874
875 #ifdef ABCEXTERNAL
876 std::string exe_file = ABCEXTERNAL;
877 #else
878 std::string exe_file = proc_self_dirname() + "yosys-abc";
879 #endif
880 std::string script_file, clk_str, box_file, lut_file;
881 std::string delay_target, lutin_shared = "-S 1", wire_delay;
882 bool fast_mode = false, /*dff_mode = false,*/ keepff = false, cleanup = true;
883 bool show_tempdir = false;
884 bool nomfs = false;
885 vector<int> lut_costs;
886 markgroups = false;
887
888 #if 0
889 cleanup = false;
890 show_tempdir = true;
891 #endif
892
893 #ifdef _WIN32
894 #ifndef ABCEXTERNAL
895 if (!check_file_exists(exe_file + ".exe") && check_file_exists(proc_self_dirname() + "..\\yosys-abc.exe"))
896 exe_file = proc_self_dirname() + "..\\yosys-abc";
897 #endif
898 #endif
899
900 size_t argidx;
901 char pwd [PATH_MAX];
902 if (!getcwd(pwd, sizeof(pwd))) {
903 log_cmd_error("getcwd failed: %s\n", strerror(errno));
904 log_abort();
905 }
906 for (argidx = 1; argidx < args.size(); argidx++) {
907 std::string arg = args[argidx];
908 if (arg == "-exe" && argidx+1 < args.size()) {
909 exe_file = args[++argidx];
910 continue;
911 }
912 if (arg == "-script" && argidx+1 < args.size()) {
913 script_file = args[++argidx];
914 rewrite_filename(script_file);
915 if (!script_file.empty() && !is_absolute_path(script_file) && script_file[0] != '+')
916 script_file = std::string(pwd) + "/" + script_file;
917 continue;
918 }
919 if (arg == "-D" && argidx+1 < args.size()) {
920 delay_target = "-D " + args[++argidx];
921 continue;
922 }
923 //if (arg == "-S" && argidx+1 < args.size()) {
924 // lutin_shared = "-S " + args[++argidx];
925 // continue;
926 //}
927 if (arg == "-lut" && argidx+1 < args.size()) {
928 string arg = args[++argidx];
929 size_t pos = arg.find_first_of(':');
930 int lut_mode = 0, lut_mode2 = 0;
931 if (pos != string::npos) {
932 lut_mode = atoi(arg.substr(0, pos).c_str());
933 lut_mode2 = atoi(arg.substr(pos+1).c_str());
934 } else {
935 pos = arg.find_first_of('.');
936 if (pos != string::npos) {
937 lut_file = arg;
938 rewrite_filename(lut_file);
939 if (!lut_file.empty() && !is_absolute_path(lut_file))
940 lut_file = std::string(pwd) + "/" + lut_file;
941 }
942 else {
943 lut_mode = atoi(arg.c_str());
944 lut_mode2 = lut_mode;
945 }
946 }
947 lut_costs.clear();
948 for (int i = 0; i < lut_mode; i++)
949 lut_costs.push_back(1);
950 for (int i = lut_mode; i < lut_mode2; i++)
951 lut_costs.push_back(2 << (i - lut_mode));
952 continue;
953 }
954 if (arg == "-luts" && argidx+1 < args.size()) {
955 lut_costs.clear();
956 for (auto &tok : split_tokens(args[++argidx], ",")) {
957 auto parts = split_tokens(tok, ":");
958 if (GetSize(parts) == 0 && !lut_costs.empty())
959 lut_costs.push_back(lut_costs.back());
960 else if (GetSize(parts) == 1)
961 lut_costs.push_back(atoi(parts.at(0).c_str()));
962 else if (GetSize(parts) == 2)
963 while (GetSize(lut_costs) < atoi(parts.at(0).c_str()))
964 lut_costs.push_back(atoi(parts.at(1).c_str()));
965 else
966 log_cmd_error("Invalid -luts syntax.\n");
967 }
968 continue;
969 }
970 if (arg == "-fast") {
971 fast_mode = true;
972 continue;
973 }
974 //if (arg == "-dff") {
975 // dff_mode = true;
976 // continue;
977 //}
978 //if (arg == "-clk" && argidx+1 < args.size()) {
979 // clk_str = args[++argidx];
980 // dff_mode = true;
981 // continue;
982 //}
983 //if (arg == "-keepff") {
984 // keepff = true;
985 // continue;
986 //}
987 if (arg == "-nocleanup") {
988 cleanup = false;
989 continue;
990 }
991 if (arg == "-showtmp") {
992 show_tempdir = true;
993 continue;
994 }
995 if (arg == "-markgroups") {
996 markgroups = true;
997 continue;
998 }
999 if (arg == "-box" && argidx+1 < args.size()) {
1000 box_file = args[++argidx];
1001 continue;
1002 }
1003 if (arg == "-W" && argidx+1 < args.size()) {
1004 wire_delay = "-W " + args[++argidx];
1005 continue;
1006 }
1007 if (arg == "-nomfs") {
1008 nomfs = true;
1009 continue;
1010 }
1011 break;
1012 }
1013 extra_args(args, argidx, design);
1014
1015 // ABC expects a box file for XAIG
1016 if (box_file.empty())
1017 box_file = "+/dummy.box";
1018
1019 rewrite_filename(box_file);
1020 if (!box_file.empty() && !is_absolute_path(box_file))
1021 box_file = std::string(pwd) + "/" + box_file;
1022
1023 dict<int,IdString> box_lookup;
1024 for (auto m : design->modules()) {
1025 auto it = m->attributes.find(ID(abc9_box_id));
1026 if (it == m->attributes.end())
1027 continue;
1028 if (m->name.begins_with("$paramod"))
1029 continue;
1030 auto id = it->second.as_int();
1031 auto r = box_lookup.insert(std::make_pair(id, m->name));
1032 if (!r.second)
1033 log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
1034 log_id(m), id, log_id(r.first->second));
1035 log_assert(r.second);
1036
1037 RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
1038 for (auto p : m->ports) {
1039 auto w = m->wire(p);
1040 log_assert(w);
1041 if (w->attributes.count(ID(abc9_carry))) {
1042 if (w->port_input) {
1043 if (carry_in)
1044 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
1045 carry_in = w;
1046 }
1047 else if (w->port_output) {
1048 if (carry_out)
1049 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
1050 carry_out = w;
1051 }
1052 }
1053 }
1054 if (carry_in || carry_out) {
1055 if (carry_in && !carry_out)
1056 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
1057 if (!carry_in && carry_out)
1058 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
1059 // Make carry_in the last PI, and carry_out the last PO
1060 // since ABC requires it this way
1061 auto &ports = m->ports;
1062 for (auto it = ports.begin(); it != ports.end(); ) {
1063 RTLIL::Wire* w = m->wire(*it);
1064 log_assert(w);
1065 if (w == carry_in || w == carry_out) {
1066 it = ports.erase(it);
1067 continue;
1068 }
1069 if (w->port_id > carry_in->port_id)
1070 --w->port_id;
1071 if (w->port_id > carry_out->port_id)
1072 --w->port_id;
1073 log_assert(w->port_input || w->port_output);
1074 log_assert(ports[w->port_id-1] == w->name);
1075 ++it;
1076 }
1077 ports.push_back(carry_in->name);
1078 carry_in->port_id = ports.size();
1079 ports.push_back(carry_out->name);
1080 carry_out->port_id = ports.size();
1081 }
1082 }
1083
1084 for (auto module : design->selected_modules())
1085 {
1086 if (module->attributes.count(ID(abc9_box_id)))
1087 continue;
1088
1089 if (module->processes.size() > 0) {
1090 log("Skipping module %s as it contains processes.\n", log_id(module));
1091 continue;
1092 }
1093
1094 SigMap assign_map(module);
1095
1096 CellTypes ct(design);
1097
1098 std::vector<RTLIL::Cell*> all_cells = module->selected_cells();
1099 std::set<RTLIL::Cell*> unassigned_cells(all_cells.begin(), all_cells.end());
1100
1101 std::set<RTLIL::Cell*> expand_queue, next_expand_queue;
1102 std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
1103 std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
1104
1105 std::map<SigSpec, pool<RTLIL::IdString>> assigned_cells;
1106 std::map<RTLIL::Cell*, SigSpec> assigned_cells_reverse;
1107
1108 std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
1109 std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
1110
1111 typedef std::pair<IdString, SigSpec> ctrldomain_t;
1112 std::map<ctrldomain_t, int> mergeability_class;
1113
1114 for (auto cell : all_cells) {
1115 for (auto &conn : cell->connections())
1116 for (auto bit : assign_map(conn.second))
1117 if (bit.wire != nullptr) {
1118 cell_to_bit[cell].insert(bit);
1119 bit_to_cell[bit].insert(cell);
1120 if (ct.cell_input(cell->type, conn.first)) {
1121 cell_to_bit_up[cell].insert(bit);
1122 bit_to_cell_down[bit].insert(cell);
1123 }
1124 if (ct.cell_output(cell->type, conn.first)) {
1125 cell_to_bit_down[cell].insert(bit);
1126 bit_to_cell_up[bit].insert(cell);
1127 }
1128 }
1129
1130 auto inst_module = design->module(cell->type);
1131 if (!inst_module || !inst_module->attributes.count("\\abc9_flop"))
1132 continue;
1133
1134 Wire *abc9_clock_wire = module->wire(stringf("%s.$abc9_clock", cell->name.c_str()));
1135 if (abc9_clock_wire == NULL)
1136 log_error("'%s$abc9_clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
1137 SigSpec abc9_clock = assign_map(abc9_clock_wire);
1138
1139 Wire *abc9_control_wire = module->wire(stringf("%s.$abc9_control", cell->name.c_str()));
1140 if (abc9_control_wire == NULL)
1141 log_error("'%s$abc9_control' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
1142 SigSpec abc9_control = assign_map(abc9_control_wire);
1143
1144 unassigned_cells.erase(cell);
1145 expand_queue.insert(cell);
1146 expand_queue_up.insert(cell);
1147 expand_queue_down.insert(cell);
1148
1149 assigned_cells[abc9_clock].insert(cell->name);
1150 assigned_cells_reverse[cell] = abc9_clock;
1151
1152 ctrldomain_t key(cell->type, abc9_control);
1153 auto r = mergeability_class.emplace(key, mergeability_class.size() + 1);
1154 auto YS_ATTRIBUTE(unused) r2 = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
1155 log_assert(r2.second);
1156 }
1157
1158 while (!expand_queue_up.empty() || !expand_queue_down.empty())
1159 {
1160 if (!expand_queue_up.empty())
1161 {
1162 RTLIL::Cell *cell = *expand_queue_up.begin();
1163 SigSpec key = assigned_cells_reverse.at(cell);
1164 expand_queue_up.erase(cell);
1165
1166 for (auto bit : cell_to_bit_up[cell])
1167 for (auto c : bit_to_cell_up[bit])
1168 if (unassigned_cells.count(c) && !c->type.in("$__ABC9_FF_", "$__ABC9_ASYNC_")) {
1169 unassigned_cells.erase(c);
1170 next_expand_queue_up.insert(c);
1171 assigned_cells[key].insert(c->name);
1172 assigned_cells_reverse[c] = key;
1173 expand_queue.insert(c);
1174 }
1175 }
1176
1177 if (!expand_queue_down.empty())
1178 {
1179 RTLIL::Cell *cell = *expand_queue_down.begin();
1180 SigSpec key = assigned_cells_reverse.at(cell);
1181 expand_queue_down.erase(cell);
1182
1183 for (auto bit : cell_to_bit_down[cell])
1184 for (auto c : bit_to_cell_down[bit])
1185 if (unassigned_cells.count(c)) {
1186 unassigned_cells.erase(c);
1187 next_expand_queue_up.insert(c);
1188 assigned_cells[key].insert(c->name);
1189 assigned_cells_reverse[c] = key;
1190 expand_queue.insert(c);
1191 }
1192 }
1193
1194 if (expand_queue_up.empty() && expand_queue_down.empty()) {
1195 expand_queue_up.swap(next_expand_queue_up);
1196 expand_queue_down.swap(next_expand_queue_down);
1197 }
1198 }
1199
1200 while (!expand_queue.empty())
1201 {
1202 RTLIL::Cell *cell = *expand_queue.begin();
1203 SigSpec key = assigned_cells_reverse.at(cell);
1204 expand_queue.erase(cell);
1205
1206 for (auto bit : cell_to_bit.at(cell)) {
1207 for (auto c : bit_to_cell[bit])
1208 if (unassigned_cells.count(c)) {
1209 unassigned_cells.erase(c);
1210 next_expand_queue.insert(c);
1211 assigned_cells[key].insert(c->name);
1212 assigned_cells_reverse[c] = key;
1213 }
1214 bit_to_cell[bit].clear();
1215 }
1216
1217 if (expand_queue.empty())
1218 expand_queue.swap(next_expand_queue);
1219 }
1220
1221 SigSpec key;
1222 for (auto cell : unassigned_cells) {
1223 assigned_cells[key].insert(cell->name);
1224 assigned_cells_reverse[cell] = key;
1225 }
1226
1227 log_header(design, "Summary of detected clock domains:\n");
1228 for (auto &it : assigned_cells)
1229 log(" %d cells in clk=%s\n", GetSize(it.second), log_signal(it.first));
1230
1231 design->selection_stack.emplace_back(false);
1232 design->selected_active_module = module->name.str();
1233 for (auto &it : assigned_cells) {
1234 std::string target = delay_target;
1235 if (target.empty()) {
1236 for (auto b : assign_map(it.first))
1237 if (b.wire) {
1238 auto jt = b.wire->attributes.find("\\abc9_period");
1239 if (jt != b.wire->attributes.end()) {
1240 target = stringf("-D %d", jt->second.as_int());
1241 log("Target period = %s ps for clock domain %s\n", target.c_str(), log_signal(it.first));
1242 break;
1243 }
1244 }
1245 }
1246 RTLIL::Selection& sel = design->selection_stack.back();
1247 sel.selected_members[module->name] = std::move(it.second);
1248 abc9_module(design, module, script_file, exe_file, cleanup, lut_costs, false, "$",
1249 keepff, target, lutin_shared, fast_mode, show_tempdir,
1250 box_file, lut_file, wire_delay, box_lookup, nomfs);
1251 assign_map.set(module);
1252 }
1253 design->selection_stack.pop_back();
1254 design->selected_active_module.clear();
1255 }
1256
1257 log_pop();
1258 }
1259 } Abc9Pass;
1260
1261 PRIVATE_NAMESPACE_END