2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 // Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
23 // http://www.eecs.berkeley.edu/~alanmi/abc/
26 // Based on &flow3 - better QoR but more experimental
27 #define ABC_COMMAND_LUT "&st; &ps -l; &sweep -v; &scorr; " \
28 "&st; &if {W}; &save; &st; &syn2; &if {W} -v; &save; &load; "\
29 "&st; &if -g -K 6; &dch -f; &if {W} -v; &save; &load; "\
30 "&st; &if -g -K 6; &synch2; &if {W} -v; &save; &load; "\
33 #define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v; &mfs; &ps -l"
37 #define ABC_FAST_COMMAND_LUT "&st; &if {W} {D}"
39 #include "kernel/register.h"
40 #include "kernel/sigtools.h"
41 #include "kernel/celltypes.h"
42 #include "kernel/cost.h"
43 #include "kernel/log.h"
56 #include "frontends/aiger/aigerparse.h"
57 #include "kernel/utils.h"
60 extern "C" int Abc_RealMain(int argc
, char *argv
[]);
64 PRIVATE_NAMESPACE_BEGIN
69 inline std::string
remap_name(RTLIL::IdString abc9_name
)
71 return stringf("$abc$%d$%s", map_autoidx
, abc9_name
.c_str()+1);
74 std::string
add_echos_to_abc9_cmd(std::string str
)
76 std::string new_str
, token
;
77 for (size_t i
= 0; i
< str
.size(); i
++) {
80 while (i
+1 < str
.size() && str
[i
+1] == ' ')
82 new_str
+= "echo + " + token
+ " " + token
+ " ";
89 new_str
+= "echo + " + token
+ "; ";
96 std::string
fold_abc9_cmd(std::string str
)
98 std::string token
, new_str
= " ";
99 int char_counter
= 10;
101 for (size_t i
= 0; i
<= str
.size(); i
++) {
104 if (i
== str
.size() || str
[i
] == ';') {
105 if (char_counter
+ token
.size() > 75)
106 new_str
+= "\n ", char_counter
= 14;
107 new_str
+= token
, char_counter
+= token
.size();
115 std::string
replace_tempdir(std::string text
, std::string tempdir_name
, bool show_tempdir
)
121 size_t pos
= text
.find(tempdir_name
);
122 if (pos
== std::string::npos
)
124 text
= text
.substr(0, pos
) + "<abc-temp-dir>" + text
.substr(pos
+ GetSize(tempdir_name
));
127 std::string selfdir_name
= proc_self_dirname();
128 if (selfdir_name
!= "/") {
130 size_t pos
= text
.find(selfdir_name
);
131 if (pos
== std::string::npos
)
133 text
= text
.substr(0, pos
) + "<yosys-exe-dir>/" + text
.substr(pos
+ GetSize(selfdir_name
));
140 struct abc9_output_filter
143 int escape_seq_state
;
145 std::string tempdir_name
;
148 abc9_output_filter(std::string tempdir_name
, bool show_tempdir
) : tempdir_name(tempdir_name
), show_tempdir(show_tempdir
)
151 escape_seq_state
= 0;
154 void next_char(char ch
)
156 if (escape_seq_state
== 0 && ch
== '\033') {
157 escape_seq_state
= 1;
160 if (escape_seq_state
== 1) {
161 escape_seq_state
= ch
== '[' ? 2 : 0;
164 if (escape_seq_state
== 2) {
165 if ((ch
< '0' || '9' < ch
) && ch
!= ';')
166 escape_seq_state
= 0;
169 escape_seq_state
= 0;
175 log("ABC: %s\n", replace_tempdir(linebuf
, tempdir_name
, show_tempdir
).c_str());
176 got_cr
= false, linebuf
.clear();
180 got_cr
= false, linebuf
.clear();
184 void next_line(const std::string
&line
)
187 //if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
188 // log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
189 // pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???",
190 // po, po_map.count(po) ? po_map.at(po).c_str() : "???");
199 void abc9_module(RTLIL::Design
*design
, RTLIL::Module
*module
, std::string script_file
, std::string exe_file
,
200 vector
<int> lut_costs
, std::string delay_target
, std::string
/*lutin_shared*/, bool fast_mode
,
201 const std::vector
<RTLIL::Cell
*> &cells
, bool show_tempdir
, std::string box_file
, std::string lut_file
,
202 std::string wire_delay
, bool nomfs
, std::string tempdir_name
205 map_autoidx
= autoidx
++;
208 //log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
209 // module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
211 std::string abc9_script
;
213 if (!lut_costs
.empty()) {
214 abc9_script
+= stringf("read_lut %s/lutdefs.txt; ", tempdir_name
.c_str());
215 if (!box_file
.empty())
216 abc9_script
+= stringf("read_box %s; ", box_file
.c_str());
219 if (!lut_file
.empty()) {
220 abc9_script
+= stringf("read_lut %s; ", lut_file
.c_str());
221 if (!box_file
.empty())
222 abc9_script
+= stringf("read_box %s; ", box_file
.c_str());
227 abc9_script
+= stringf("&read %s/input.xaig; &ps; ", tempdir_name
.c_str());
229 if (!script_file
.empty()) {
230 if (script_file
[0] == '+') {
231 for (size_t i
= 1; i
< script_file
.size(); i
++)
232 if (script_file
[i
] == '\'')
233 abc9_script
+= "'\\''";
234 else if (script_file
[i
] == ',')
237 abc9_script
+= script_file
[i
];
239 abc9_script
+= stringf("source %s", script_file
.c_str());
240 } else if (!lut_costs
.empty() || !lut_file
.empty()) {
241 abc9_script
+= fast_mode
? ABC_FAST_COMMAND_LUT
: ABC_COMMAND_LUT
;
245 for (size_t pos
= abc9_script
.find("{D}"); pos
!= std::string::npos
; pos
= abc9_script
.find("{D}", pos
))
246 abc9_script
= abc9_script
.substr(0, pos
) + delay_target
+ abc9_script
.substr(pos
+3);
248 //for (size_t pos = abc9_script.find("{S}"); pos != std::string::npos; pos = abc9_script.find("{S}", pos))
249 // abc9_script = abc9_script.substr(0, pos) + lutin_shared + abc9_script.substr(pos+3);
251 for (size_t pos
= abc9_script
.find("{W}"); pos
!= std::string::npos
; pos
= abc9_script
.find("{W}", pos
))
252 abc9_script
= abc9_script
.substr(0, pos
) + wire_delay
+ abc9_script
.substr(pos
+3);
255 for (size_t pos
= abc9_script
.find("&mfs"); pos
!= std::string::npos
; pos
= abc9_script
.find("&mfs", pos
))
256 abc9_script
= abc9_script
.erase(pos
, strlen("&mfs"));
258 abc9_script
+= stringf("; &write -n %s/output.aig", tempdir_name
.c_str());
259 abc9_script
= add_echos_to_abc9_cmd(abc9_script
);
261 for (size_t i
= 0; i
+1 < abc9_script
.size(); i
++)
262 if (abc9_script
[i
] == ';' && abc9_script
[i
+1] == ' ')
263 abc9_script
[i
+1] = '\n';
265 FILE *f
= fopen(stringf("%s/abc.script", tempdir_name
.c_str()).c_str(), "wt");
266 fprintf(f
, "%s\n", abc9_script
.c_str());
269 int count_outputs
= design
->scratchpad_get_int("write_xaiger.num_outputs");
270 log("Extracted %d AND gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
271 design
->scratchpad_get_int("write_xaiger.num_ands"),
272 design
->scratchpad_get_int("write_xaiger.num_wires"),
273 design
->scratchpad_get_int("write_xaiger.num_inputs"),
276 if (count_outputs
> 0) {
280 buffer
= stringf("%s/%s", tempdir_name
.c_str(), "input.xaig");
283 log_error("Can't open ABC output file `%s'.\n", buffer
.c_str());
284 buffer
= stringf("%s/%s", tempdir_name
.c_str(), "input.sym");
285 log_assert(!design
->module(ID($__abc9__
)));
287 AigerReader
reader(design
, ifs
, ID($__abc9__
), "" /* clk_name */, buffer
.c_str() /* map_filename */, true /* wideports */);
288 reader
.parse_xaiger();
291 Pass::call_on_module(design
, design
->module(ID($__abc9__
)), stringf("write_verilog -noexpr -norename -selected"));
292 design
->remove(design
->module(ID($__abc9__
)));
295 log_header(design
, "Executing ABC9.\n");
297 if (!lut_costs
.empty()) {
298 buffer
= stringf("%s/lutdefs.txt", tempdir_name
.c_str());
299 f
= fopen(buffer
.c_str(), "wt");
301 log_error("Opening %s for writing failed: %s\n", buffer
.c_str(), strerror(errno
));
302 for (int i
= 0; i
< GetSize(lut_costs
); i
++)
303 fprintf(f
, "%d %d.00 1.00\n", i
+1, lut_costs
.at(i
));
307 buffer
= stringf("%s -s -f %s/abc.script 2>&1", exe_file
.c_str(), tempdir_name
.c_str());
308 log("Running ABC command: %s\n", replace_tempdir(buffer
, tempdir_name
, show_tempdir
).c_str());
310 #ifndef YOSYS_LINK_ABC
311 abc9_output_filter
filt(tempdir_name
, show_tempdir
);
312 int ret
= run_command(buffer
, std::bind(&abc9_output_filter::next_line
, filt
, std::placeholders::_1
));
314 // These needs to be mutable, supposedly due to getopt
316 string tmp_script_name
= stringf("%s/abc.script", tempdir_name
.c_str());
317 abc9_argv
[0] = strdup(exe_file
.c_str());
318 abc9_argv
[1] = strdup("-s");
319 abc9_argv
[2] = strdup("-f");
320 abc9_argv
[3] = strdup(tmp_script_name
.c_str());
322 int ret
= Abc_RealMain(4, abc9_argv
);
329 log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer
.c_str(), ret
);
331 buffer
= stringf("%s/%s", tempdir_name
.c_str(), "output.aig");
332 ifs
.open(buffer
, std::ifstream::binary
);
334 log_error("Can't open ABC output file `%s'.\n", buffer
.c_str());
336 buffer
= stringf("%s/%s", tempdir_name
.c_str(), "input.sym");
337 log_assert(!design
->module(ID($__abc9__
)));
339 AigerReader
reader(design
, ifs
, ID($__abc9__
), "" /* clk_name */, buffer
.c_str() /* map_filename */, true /* wideports */);
340 reader
.parse_xaiger();
344 Pass::call_on_module(design
, design
->module(ID($__abc9__
)), stringf("write_verilog -noexpr -norename -selected"));
347 log_header(design
, "Re-integrating ABC9 results.\n");
348 RTLIL::Module
*mapped_mod
= design
->module(ID($__abc9__
));
349 if (mapped_mod
== NULL
)
350 log_error("ABC output file does not contain a module `$__abc9__'.\n");
352 for (auto &it
: mapped_mod
->wires_
) {
353 RTLIL::Wire
*w
= it
.second
;
354 RTLIL::Wire
*remap_wire
= module
->addWire(remap_name(w
->name
), GetSize(w
));
355 if (markgroups
) remap_wire
->attributes
[ID(abcgroup
)] = map_autoidx
;
358 dict
<IdString
, bool> abc9_box
;
359 vector
<RTLIL::Cell
*> boxes
;
360 for (auto cell
: cells
) {
361 if (cell
->type
.in(ID($_AND_
), ID($_NOT_
), ID($__ABC9_FF_
))) {
362 module
->remove(cell
);
365 auto jt
= abc9_box
.find(cell
->type
);
366 if (jt
== abc9_box
.end()) {
367 RTLIL::Module
* box_module
= design
->module(cell
->type
);
368 jt
= abc9_box
.insert(std::make_pair(cell
->type
, box_module
&& box_module
->attributes
.count(ID(abc9_box_id
)))).first
;
371 auto kt
= cell
->attributes
.find("\\abc9_keep");
372 bool abc9_keep
= false;
373 if (kt
!= cell
->attributes
.end()) {
374 abc9_keep
= kt
->second
.as_bool();
375 cell
->attributes
.erase(kt
);
378 boxes
.emplace_back(cell
);
382 dict
<SigBit
, pool
<IdString
>> bit_drivers
, bit_users
;
383 TopoSort
<IdString
, RTLIL::sort_by_id_str
> toposort
;
384 dict
<RTLIL::Cell
*,RTLIL::Cell
*> not2drivers
;
385 dict
<SigBit
, std::vector
<RTLIL::Cell
*>> bit2sinks
;
387 std::map
<IdString
, int> cell_stats
;
388 for (auto mapped_cell
: mapped_mod
->cells())
390 toposort
.node(mapped_cell
->name
);
392 RTLIL::Cell
*cell
= nullptr;
393 if (mapped_cell
->type
== ID($_NOT_
)) {
394 RTLIL::SigBit a_bit
= mapped_cell
->getPort(ID::A
);
395 RTLIL::SigBit y_bit
= mapped_cell
->getPort(ID::Y
);
396 bit_users
[a_bit
].insert(mapped_cell
->name
);
397 bit_drivers
[y_bit
].insert(mapped_cell
->name
);
400 mapped_cell
->setPort(ID::Y
, module
->addWire(NEW_ID
));
401 RTLIL::Wire
*wire
= module
->wire(remap_name(y_bit
.wire
->name
));
403 module
->connect(RTLIL::SigBit(wire
, y_bit
.offset
), State::S1
);
405 else if (!lut_costs
.empty() || !lut_file
.empty()) {
406 RTLIL::Cell
* driver_lut
= nullptr;
407 // ABC can return NOT gates that drive POs
408 if (!a_bit
.wire
->port_input
) {
409 // If it's not a NOT gate that that comes from a PI directly,
410 // find the driver LUT and clone that to guarantee that we won't
411 // increase the max logic depth
412 // (TODO: Optimise by not cloning unless will increase depth)
413 RTLIL::IdString driver_name
;
414 if (GetSize(a_bit
.wire
) == 1)
415 driver_name
= stringf("%s$lut", a_bit
.wire
->name
.c_str());
417 driver_name
= stringf("%s[%d]$lut", a_bit
.wire
->name
.c_str(), a_bit
.offset
);
418 driver_lut
= mapped_mod
->cell(driver_name
);
422 // If a driver couldn't be found (could be from PI or box CI)
423 // then implement using a LUT
424 cell
= module
->addLut(remap_name(stringf("%s$lut", mapped_cell
->name
.c_str())),
425 RTLIL::SigBit(module
->wires_
.at(remap_name(a_bit
.wire
->name
)), a_bit
.offset
),
426 RTLIL::SigBit(module
->wires_
.at(remap_name(y_bit
.wire
->name
)), y_bit
.offset
),
427 RTLIL::Const::from_string("01"));
428 bit2sinks
[cell
->getPort(ID::A
)].push_back(cell
);
429 cell_stats
[ID($lut
)]++;
432 not2drivers
[mapped_cell
] = driver_lut
;
437 if (cell
&& markgroups
) cell
->attributes
[ID(abcgroup
)] = map_autoidx
;
440 cell_stats
[mapped_cell
->type
]++;
442 RTLIL::Cell
*existing_cell
= nullptr;
443 if (mapped_cell
->type
.in(ID($lut
), ID($__ABC9_FF_
))) {
444 if (mapped_cell
->type
== ID($lut
) &&
445 GetSize(mapped_cell
->getPort(ID::A
)) == 1 &&
446 mapped_cell
->getParam(ID(LUT
)) == RTLIL::Const::from_string("01")) {
447 SigSpec my_a
= module
->wires_
.at(remap_name(mapped_cell
->getPort(ID::A
).as_wire()->name
));
448 SigSpec my_y
= module
->wires_
.at(remap_name(mapped_cell
->getPort(ID::Y
).as_wire()->name
));
449 module
->connect(my_y
, my_a
);
450 if (markgroups
) mapped_cell
->attributes
[ID(abcgroup
)] = map_autoidx
;
454 cell
= module
->addCell(remap_name(mapped_cell
->name
), mapped_cell
->type
);
457 existing_cell
= module
->cell(mapped_cell
->name
);
458 log_assert(existing_cell
);
459 cell
= module
->addCell(remap_name(mapped_cell
->name
), mapped_cell
->type
);
462 if (markgroups
) cell
->attributes
[ID(abcgroup
)] = map_autoidx
;
464 cell
->parameters
= existing_cell
->parameters
;
465 cell
->attributes
= existing_cell
->attributes
;
468 cell
->parameters
= mapped_cell
->parameters
;
469 cell
->attributes
= mapped_cell
->attributes
;
472 RTLIL::Module
* box_module
= design
->module(mapped_cell
->type
);
473 auto abc9_flop
= box_module
&& box_module
->attributes
.count("\\abc9_flop");
474 for (auto &conn
: mapped_cell
->connections()) {
475 RTLIL::SigSpec newsig
;
476 for (auto c
: conn
.second
.chunks()) {
479 //log_assert(c.width == 1);
481 c
.wire
= module
->wires_
.at(remap_name(c
.wire
->name
));
484 cell
->setPort(conn
.first
, newsig
);
487 if (cell
->input(conn
.first
)) {
488 for (auto i
: newsig
)
489 bit2sinks
[i
].push_back(cell
);
490 for (auto i
: conn
.second
)
491 bit_users
[i
].insert(mapped_cell
->name
);
493 if (cell
->output(conn
.first
))
494 for (auto i
: conn
.second
)
495 bit_drivers
[i
].insert(mapped_cell
->name
);
500 for (auto existing_cell
: boxes
) {
501 Cell
*cell
= module
->cell(remap_name(existing_cell
->name
));
503 for (auto &conn
: existing_cell
->connections()) {
504 if (!conn
.second
.is_wire())
506 Wire
*wire
= conn
.second
.as_wire();
507 if (!wire
->get_bool_attribute(ID(abc9_padding
)))
509 cell
->unsetPort(conn
.first
);
510 log_debug("Dropping padded port connection for %s (%s) .%s (%s )\n", log_id(cell
), cell
->type
.c_str(), log_id(conn
.first
), log_signal(conn
.second
));
512 module
->swap_names(cell
, existing_cell
);
514 module
->remove(existing_cell
);
517 // Copy connections (and rename) from mapped_mod to module
518 for (auto conn
: mapped_mod
->connections()) {
519 if (!conn
.first
.is_fully_const()) {
520 auto chunks
= conn
.first
.chunks();
521 for (auto &c
: chunks
)
522 c
.wire
= module
->wires_
.at(remap_name(c
.wire
->name
));
523 conn
.first
= std::move(chunks
);
525 if (!conn
.second
.is_fully_const()) {
526 auto chunks
= conn
.second
.chunks();
527 for (auto &c
: chunks
)
529 c
.wire
= module
->wires_
.at(remap_name(c
.wire
->name
));
530 conn
.second
= std::move(chunks
);
532 module
->connect(conn
);
535 for (auto &it
: cell_stats
)
536 log("ABC RESULTS: %15s cells: %8d\n", it
.first
.c_str(), it
.second
);
537 int in_wires
= 0, out_wires
= 0;
539 // Stitch in mapped_mod's inputs/outputs into module
540 for (auto port
: mapped_mod
->ports
) {
541 RTLIL::Wire
*w
= mapped_mod
->wire(port
);
542 RTLIL::Wire
*wire
= module
->wire(port
);
544 RTLIL::Wire
*remap_wire
= module
->wire(remap_name(port
));
545 RTLIL::SigSpec signal
= RTLIL::SigSpec(wire
, 0, GetSize(remap_wire
));
546 log_assert(GetSize(signal
) >= GetSize(remap_wire
));
549 if (w
->port_output
) {
551 conn
.second
= remap_wire
;
553 module
->connect(conn
);
555 else if (w
->port_input
) {
556 conn
.first
= remap_wire
;
557 conn
.second
= signal
;
559 module
->connect(conn
);
563 for (auto &it
: bit_users
)
564 if (bit_drivers
.count(it
.first
))
565 for (auto driver_cell
: bit_drivers
.at(it
.first
))
566 for (auto user_cell
: it
.second
)
567 toposort
.edge(driver_cell
, user_cell
);
568 bool no_loops
YS_ATTRIBUTE(unused
) = toposort
.sort();
569 log_assert(no_loops
);
571 for (auto ii
= toposort
.sorted
.rbegin(); ii
!= toposort
.sorted
.rend(); ii
++) {
572 RTLIL::Cell
*not_cell
= mapped_mod
->cell(*ii
);
573 log_assert(not_cell
);
574 if (not_cell
->type
!= ID($_NOT_
))
576 auto it
= not2drivers
.find(not_cell
);
577 if (it
== not2drivers
.end())
579 RTLIL::Cell
*driver_lut
= it
->second
;
580 RTLIL::SigBit a_bit
= not_cell
->getPort(ID::A
);
581 RTLIL::SigBit y_bit
= not_cell
->getPort(ID::Y
);
582 RTLIL::Const driver_mask
;
584 a_bit
.wire
= module
->wires_
.at(remap_name(a_bit
.wire
->name
));
585 y_bit
.wire
= module
->wires_
.at(remap_name(y_bit
.wire
->name
));
587 auto jt
= bit2sinks
.find(a_bit
);
588 if (jt
== bit2sinks
.end())
591 for (auto sink_cell
: jt
->second
)
592 if (sink_cell
->type
!= ID($lut
))
595 // Push downstream LUTs past inverter
596 for (auto sink_cell
: jt
->second
) {
597 SigSpec A
= sink_cell
->getPort(ID::A
);
598 RTLIL::Const mask
= sink_cell
->getParam(ID(LUT
));
600 for (; index
< GetSize(A
); index
++)
601 if (A
[index
] == a_bit
)
603 log_assert(index
< GetSize(A
));
605 while (i
< GetSize(mask
)) {
606 for (int j
= 0; j
< (1 << index
); j
++)
607 std::swap(mask
[i
+j
], mask
[i
+j
+(1 << index
)]);
611 sink_cell
->setPort(ID::A
, A
);
612 sink_cell
->setParam(ID(LUT
), mask
);
615 // Since we have rewritten all sinks (which we know
616 // to be only LUTs) to be after the inverter, we can
617 // go ahead and clone the LUT with the expectation
618 // that the original driving LUT will become dangling
619 // and get cleaned away
621 driver_mask
= driver_lut
->getParam(ID(LUT
));
622 for (auto &b
: driver_mask
.bits
) {
623 if (b
== RTLIL::State::S0
) b
= RTLIL::State::S1
;
624 else if (b
== RTLIL::State::S1
) b
= RTLIL::State::S0
;
626 auto cell
= module
->addLut(NEW_ID
,
627 driver_lut
->getPort(ID::A
),
630 for (auto &bit
: cell
->connections_
.at(ID::A
)) {
631 bit
.wire
= module
->wires_
.at(remap_name(bit
.wire
->name
));
632 bit2sinks
[bit
].push_back(cell
);
636 //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
637 log("ABC RESULTS: input signals: %8d\n", in_wires
);
638 log("ABC RESULTS: output signals: %8d\n", out_wires
);
640 design
->remove(mapped_mod
);
644 // log("Don't call ABC as there is nothing to map.\n");
648 struct Abc9MapPass
: public Pass
{
649 Abc9MapPass() : Pass("abc9_map", "use ABC9 for technology mapping") { }
650 void help() YS_OVERRIDE
652 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
654 log(" abc9_map [options] [selection]\n");
656 log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
657 log("library to a target architecture.\n");
659 log(" -exe <command>\n");
661 log(" use the specified command instead of \"" ABCEXTERNAL
"\" to execute ABC.\n");
663 log(" use the specified command instead of \"<yosys-bindir>/yosys-abc\" to execute ABC.\n");
665 log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
667 log(" -script <file>\n");
668 log(" use the specified ABC script file instead of the default script.\n");
670 log(" if <file> starts with a plus sign (+), then the rest of the filename\n");
671 log(" string is interpreted as the command string to be passed to ABC. The\n");
672 log(" leading plus sign is removed and all commas (,) in the string are\n");
673 log(" replaced with blanks before the string is passed to ABC.\n");
675 log(" if no -script parameter is given, the following scripts are used:\n");
677 log(" for -lut/-luts (only one LUT size):\n");
678 log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT
/*"; lutpack {S}"*/).c_str());
680 log(" for -lut/-luts (different LUT sizes):\n");
681 log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT
).c_str());
684 log(" use different default scripts that are slightly faster (at the cost\n");
685 log(" of output quality):\n");
687 log(" for -lut/-luts:\n");
688 log("%s\n", fold_abc9_cmd(ABC_FAST_COMMAND_LUT
).c_str());
690 log(" -D <picoseconds>\n");
691 log(" set delay target. the string {D} in the default scripts above is\n");
692 log(" replaced by this option when used, and an empty string otherwise\n");
693 log(" (indicating best possible delay).\n");
694 // log(" This also replaces 'dretime' with 'dretime; retime -o {D}' in the\n");
695 // log(" default scripts above.\n");
697 // log(" -S <num>\n");
698 // log(" maximum number of LUT inputs shared.\n");
699 // log(" (replaces {S} in the default scripts above, default: -S 1)\n");
701 log(" -lut <width>\n");
702 log(" generate netlist using luts of (max) the specified width.\n");
704 log(" -lut <w1>:<w2>\n");
705 log(" generate netlist using luts of (max) the specified width <w2>. All\n");
706 log(" luts with width <= <w1> have constant cost. for luts larger than <w1>\n");
707 log(" the area cost doubles with each additional input bit. the delay cost\n");
708 log(" is still constant for all lut widths.\n");
710 log(" -lut <file>\n");
711 log(" pass this file with lut library to ABC.\n");
713 log(" -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..\n");
714 log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
715 log(" 2, 3, .. inputs.\n");
718 // log(" also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many\n");
719 // log(" clock domains are automatically partitioned in clock domains and each\n");
720 // log(" domain is passed through ABC independently.\n");
722 // log(" -clk [!]<clock-signal-name>[,[!]<enable-signal-name>]\n");
723 // log(" use only the specified clock domain. this is like -dff, but only FF\n");
724 // log(" cells that belong to the specified clock domain are used.\n");
726 // log(" -keepff\n");
727 // log(" set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
728 // log(" them, for example for equivalence checking.)\n");
731 log(" print the temp dir name in log. usually this is suppressed so that the\n");
732 log(" command output is identical across runs.\n");
734 log(" -markgroups\n");
735 log(" set a 'abcgroup' attribute on all objects created by ABC. The value of\n");
736 log(" this attribute is a unique integer for each ABC process started. This\n");
737 log(" is useful for debugging the partitioning of clock domains.\n");
739 log(" -box <file>\n");
740 log(" pass this file with box library to ABC. Use with -lut.\n");
742 log(" -tempdir <dir>\n");
743 log(" use this as the temp dir.\n");
745 log("Note that this is a logic optimization pass within Yosys that is calling ABC\n");
746 log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
747 log("ABC on logic snippets extracted from your design. You will not get any useful\n");
748 log("output when passing an ABC script that writes a file. Instead write your full\n");
749 log("design as BLIF file with write_blif and then load that into ABC externally if\n");
750 log("you want to use ABC to convert your design into another format.\n");
752 log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
755 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
757 log_header(design
, "Executing ABC9_MAP pass (technology mapping using ABC9).\n");
760 std::string exe_file
= ABCEXTERNAL
;
762 std::string exe_file
= proc_self_dirname() + "yosys-abc";
764 std::string script_file
, clk_str
, box_file
, lut_file
;
765 std::string delay_target
, lutin_shared
= "-S 1", wire_delay
;
766 std::string tempdir_name
;
767 bool fast_mode
= false;
768 bool show_tempdir
= false;
770 vector
<int> lut_costs
;
780 if (!check_file_exists(exe_file
+ ".exe") && check_file_exists(proc_self_dirname() + "..\\yosys-abc.exe"))
781 exe_file
= proc_self_dirname() + "..\\yosys-abc";
787 if (!getcwd(pwd
, sizeof(pwd
))) {
788 log_cmd_error("getcwd failed: %s\n", strerror(errno
));
791 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
792 std::string arg
= args
[argidx
];
793 if (arg
== "-exe" && argidx
+1 < args
.size()) {
794 exe_file
= args
[++argidx
];
797 if (arg
== "-script" && argidx
+1 < args
.size()) {
798 script_file
= args
[++argidx
];
799 rewrite_filename(script_file
);
800 if (!script_file
.empty() && !is_absolute_path(script_file
) && script_file
[0] != '+')
801 script_file
= std::string(pwd
) + "/" + script_file
;
804 if (arg
== "-D" && argidx
+1 < args
.size()) {
805 delay_target
= "-D " + args
[++argidx
];
808 //if (arg == "-S" && argidx+1 < args.size()) {
809 // lutin_shared = "-S " + args[++argidx];
812 if (arg
== "-lut" && argidx
+1 < args
.size()) {
813 string arg
= args
[++argidx
];
814 if (arg
.find_first_not_of("0123456789:") == std::string::npos
) {
815 size_t pos
= arg
.find_first_of(':');
816 int lut_mode
= 0, lut_mode2
= 0;
817 if (pos
!= string::npos
) {
818 lut_mode
= atoi(arg
.substr(0, pos
).c_str());
819 lut_mode2
= atoi(arg
.substr(pos
+1).c_str());
821 lut_mode
= atoi(arg
.c_str());
822 lut_mode2
= lut_mode
;
825 for (int i
= 0; i
< lut_mode
; i
++)
826 lut_costs
.push_back(1);
827 for (int i
= lut_mode
; i
< lut_mode2
; i
++)
828 lut_costs
.push_back(2 << (i
- lut_mode
));
832 rewrite_filename(lut_file
);
833 if (!lut_file
.empty() && !is_absolute_path(lut_file
) && lut_file
[0] != '+')
834 lut_file
= std::string(pwd
) + "/" + lut_file
;
838 if (arg
== "-luts" && argidx
+1 < args
.size()) {
840 for (auto &tok
: split_tokens(args
[++argidx
], ",")) {
841 auto parts
= split_tokens(tok
, ":");
842 if (GetSize(parts
) == 0 && !lut_costs
.empty())
843 lut_costs
.push_back(lut_costs
.back());
844 else if (GetSize(parts
) == 1)
845 lut_costs
.push_back(atoi(parts
.at(0).c_str()));
846 else if (GetSize(parts
) == 2)
847 while (GetSize(lut_costs
) < atoi(parts
.at(0).c_str()))
848 lut_costs
.push_back(atoi(parts
.at(1).c_str()));
850 log_cmd_error("Invalid -luts syntax.\n");
854 if (arg
== "-fast") {
858 if (arg
== "-showtmp") {
862 if (arg
== "-markgroups") {
866 if (arg
== "-box" && argidx
+1 < args
.size()) {
867 box_file
= args
[++argidx
];
870 if (arg
== "-W" && argidx
+1 < args
.size()) {
871 wire_delay
= "-W " + args
[++argidx
];
874 if (arg
== "-nomfs") {
878 if (arg
== "-tempdir" && argidx
+1 < args
.size()) {
879 tempdir_name
= args
[++argidx
];
884 extra_args(args
, argidx
, design
);
886 // ABC expects a box file for XAIG
887 if (box_file
.empty())
888 box_file
= "+/dummy.box";
890 rewrite_filename(box_file
);
891 if (!box_file
.empty() && !is_absolute_path(box_file
) && box_file
[0] != '+')
892 box_file
= std::string(pwd
) + "/" + box_file
;
894 if (tempdir_name
.empty())
895 log_cmd_error("abc9_map '-tempdir' option is mandatory.\n");
898 for (auto mod
: design
->selected_modules())
900 if (mod
->processes
.size() > 0) {
901 log("Skipping module %s as it contains processes.\n", log_id(mod
));
905 const std::vector
<RTLIL::Cell
*> all_cells
= mod
->selected_cells();
907 abc9_module(design
, mod
, script_file
, exe_file
, lut_costs
,
908 delay_target
, lutin_shared
, fast_mode
, all_cells
, show_tempdir
,
909 box_file
, lut_file
, wire_delay
, nomfs
, tempdir_name
);
914 PRIVATE_NAMESPACE_END