2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 // Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
23 // http://www.eecs.berkeley.edu/~alanmi/abc/
26 // Based on &flow3 - better QoR but more experimental
27 #define ABC_COMMAND_LUT "&st; &ps -l; &sweep -v; &scorr; " \
28 "&st; &if {W}; &save; &st; &syn2; &if {W} -v; &save; &load; "\
29 "&st; &if -g -K 6; &dch -f; &if {W} -v; &save; &load; "\
30 "&st; &if -g -K 6; &synch2; &if {W} -v; &save; &load; "\
33 #define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v; &mfs; &ps -l"
37 #define ABC_FAST_COMMAND_LUT "&st; &if {W} {D}"
39 #include "kernel/register.h"
40 #include "kernel/sigtools.h"
41 #include "kernel/celltypes.h"
42 #include "kernel/cost.h"
43 #include "kernel/log.h"
56 #include "frontends/aiger/aigerparse.h"
57 #include "kernel/utils.h"
60 extern "C" int Abc_RealMain(int argc
, char *argv
[]);
64 PRIVATE_NAMESPACE_BEGIN
69 inline std::string
remap_name(RTLIL::IdString abc9_name
)
71 return stringf("$abc$%d$%s", map_autoidx
, abc9_name
.c_str()+1);
74 std::string
add_echos_to_abc9_cmd(std::string str
)
76 std::string new_str
, token
;
77 for (size_t i
= 0; i
< str
.size(); i
++) {
80 while (i
+1 < str
.size() && str
[i
+1] == ' ')
82 new_str
+= "echo + " + token
+ " " + token
+ " ";
89 new_str
+= "echo + " + token
+ "; ";
96 std::string
fold_abc9_cmd(std::string str
)
98 std::string token
, new_str
= " ";
99 int char_counter
= 10;
101 for (size_t i
= 0; i
<= str
.size(); i
++) {
104 if (i
== str
.size() || str
[i
] == ';') {
105 if (char_counter
+ token
.size() > 75)
106 new_str
+= "\n ", char_counter
= 14;
107 new_str
+= token
, char_counter
+= token
.size();
115 std::string
replace_tempdir(std::string text
, std::string tempdir_name
, bool show_tempdir
)
121 size_t pos
= text
.find(tempdir_name
);
122 if (pos
== std::string::npos
)
124 text
= text
.substr(0, pos
) + "<abc-temp-dir>" + text
.substr(pos
+ GetSize(tempdir_name
));
127 std::string selfdir_name
= proc_self_dirname();
128 if (selfdir_name
!= "/") {
130 size_t pos
= text
.find(selfdir_name
);
131 if (pos
== std::string::npos
)
133 text
= text
.substr(0, pos
) + "<yosys-exe-dir>/" + text
.substr(pos
+ GetSize(selfdir_name
));
140 struct abc9_output_filter
143 int escape_seq_state
;
145 std::string tempdir_name
;
148 abc9_output_filter(std::string tempdir_name
, bool show_tempdir
) : tempdir_name(tempdir_name
), show_tempdir(show_tempdir
)
151 escape_seq_state
= 0;
154 void next_char(char ch
)
156 if (escape_seq_state
== 0 && ch
== '\033') {
157 escape_seq_state
= 1;
160 if (escape_seq_state
== 1) {
161 escape_seq_state
= ch
== '[' ? 2 : 0;
164 if (escape_seq_state
== 2) {
165 if ((ch
< '0' || '9' < ch
) && ch
!= ';')
166 escape_seq_state
= 0;
169 escape_seq_state
= 0;
175 log("ABC: %s\n", replace_tempdir(linebuf
, tempdir_name
, show_tempdir
).c_str());
176 got_cr
= false, linebuf
.clear();
180 got_cr
= false, linebuf
.clear();
184 void next_line(const std::string
&line
)
187 //if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
188 // log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
189 // pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???",
190 // po, po_map.count(po) ? po_map.at(po).c_str() : "???");
199 void abc9_module(RTLIL::Design
*design
, RTLIL::Module
*module
, std::string script_file
, std::string exe_file
,
200 vector
<int> lut_costs
, std::string delay_target
, std::string
/*lutin_shared*/, bool fast_mode
,
201 const std::vector
<RTLIL::Cell
*> &cells
, bool show_tempdir
, std::string box_file
, std::string lut_file
,
202 std::string wire_delay
, const dict
<int,IdString
> &box_lookup
, bool nomfs
, std::string tempdir_name
205 map_autoidx
= autoidx
++;
208 //log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
209 // module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
211 std::string abc9_script
;
213 if (!lut_costs
.empty()) {
214 abc9_script
+= stringf("read_lut %s/lutdefs.txt; ", tempdir_name
.c_str());
215 if (!box_file
.empty())
216 abc9_script
+= stringf("read_box %s; ", box_file
.c_str());
219 if (!lut_file
.empty()) {
220 abc9_script
+= stringf("read_lut %s; ", lut_file
.c_str());
221 if (!box_file
.empty())
222 abc9_script
+= stringf("read_box %s; ", box_file
.c_str());
227 abc9_script
+= stringf("&read %s/input.xaig; &ps; ", tempdir_name
.c_str());
229 if (!script_file
.empty()) {
230 if (script_file
[0] == '+') {
231 for (size_t i
= 1; i
< script_file
.size(); i
++)
232 if (script_file
[i
] == '\'')
233 abc9_script
+= "'\\''";
234 else if (script_file
[i
] == ',')
237 abc9_script
+= script_file
[i
];
239 abc9_script
+= stringf("source %s", script_file
.c_str());
240 } else if (!lut_costs
.empty() || !lut_file
.empty()) {
241 abc9_script
+= fast_mode
? ABC_FAST_COMMAND_LUT
: ABC_COMMAND_LUT
;
245 for (size_t pos
= abc9_script
.find("{D}"); pos
!= std::string::npos
; pos
= abc9_script
.find("{D}", pos
))
246 abc9_script
= abc9_script
.substr(0, pos
) + delay_target
+ abc9_script
.substr(pos
+3);
248 //for (size_t pos = abc9_script.find("{S}"); pos != std::string::npos; pos = abc9_script.find("{S}", pos))
249 // abc9_script = abc9_script.substr(0, pos) + lutin_shared + abc9_script.substr(pos+3);
251 for (size_t pos
= abc9_script
.find("{W}"); pos
!= std::string::npos
; pos
= abc9_script
.find("{W}", pos
))
252 abc9_script
= abc9_script
.substr(0, pos
) + wire_delay
+ abc9_script
.substr(pos
+3);
255 for (size_t pos
= abc9_script
.find("&mfs"); pos
!= std::string::npos
; pos
= abc9_script
.find("&mfs", pos
))
256 abc9_script
= abc9_script
.erase(pos
, strlen("&mfs"));
258 abc9_script
+= stringf("; &write -n %s/output.aig", tempdir_name
.c_str());
259 abc9_script
= add_echos_to_abc9_cmd(abc9_script
);
261 for (size_t i
= 0; i
+1 < abc9_script
.size(); i
++)
262 if (abc9_script
[i
] == ';' && abc9_script
[i
+1] == ' ')
263 abc9_script
[i
+1] = '\n';
265 FILE *f
= fopen(stringf("%s/abc.script", tempdir_name
.c_str()).c_str(), "wt");
266 fprintf(f
, "%s\n", abc9_script
.c_str());
271 int count_outputs
= design
->scratchpad_get_int("write_xaiger.num_outputs");
272 log("Extracted %d AND gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
273 design
->scratchpad_get_int("write_xaiger.num_ands"),
274 design
->scratchpad_get_int("write_xaiger.num_wires"),
275 design
->scratchpad_get_int("write_xaiger.num_inputs"),
278 if (count_outputs
> 0) {
282 buffer
= stringf("%s/%s", tempdir_name
.c_str(), "input.xaig");
285 log_error("Can't open ABC output file `%s'.\n", buffer
.c_str());
286 buffer
= stringf("%s/%s", tempdir_name
.c_str(), "input.sym");
287 log_assert(!design
->module(ID($__abc9__
)));
289 AigerReader
reader(design
, ifs
, ID($__abc9__
), "" /* clk_name */, buffer
.c_str() /* map_filename */, true /* wideports */);
290 reader
.parse_xaiger(box_lookup
);
293 Pass::call_on_module(design
, design
->module(ID($__abc9__
)), stringf("write_verilog -noexpr -norename -selected"));
294 design
->remove(design
->module(ID($__abc9__
)));
297 log_header(design
, "Executing ABC9.\n");
299 if (!lut_costs
.empty()) {
300 buffer
= stringf("%s/lutdefs.txt", tempdir_name
.c_str());
301 f
= fopen(buffer
.c_str(), "wt");
303 log_error("Opening %s for writing failed: %s\n", buffer
.c_str(), strerror(errno
));
304 for (int i
= 0; i
< GetSize(lut_costs
); i
++)
305 fprintf(f
, "%d %d.00 1.00\n", i
+1, lut_costs
.at(i
));
309 buffer
= stringf("%s -s -f %s/abc.script 2>&1", exe_file
.c_str(), tempdir_name
.c_str());
310 log("Running ABC command: %s\n", replace_tempdir(buffer
, tempdir_name
, show_tempdir
).c_str());
312 #ifndef YOSYS_LINK_ABC
313 abc9_output_filter
filt(tempdir_name
, show_tempdir
);
314 int ret
= run_command(buffer
, std::bind(&abc9_output_filter::next_line
, filt
, std::placeholders::_1
));
316 // These needs to be mutable, supposedly due to getopt
318 string tmp_script_name
= stringf("%s/abc.script", tempdir_name
.c_str());
319 abc9_argv
[0] = strdup(exe_file
.c_str());
320 abc9_argv
[1] = strdup("-s");
321 abc9_argv
[2] = strdup("-f");
322 abc9_argv
[3] = strdup(tmp_script_name
.c_str());
324 int ret
= Abc_RealMain(4, abc9_argv
);
331 log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer
.c_str(), ret
);
333 buffer
= stringf("%s/%s", tempdir_name
.c_str(), "output.aig");
334 ifs
.open(buffer
, std::ifstream::binary
);
336 log_error("Can't open ABC output file `%s'.\n", buffer
.c_str());
338 buffer
= stringf("%s/%s", tempdir_name
.c_str(), "input.sym");
339 log_assert(!design
->module(ID($__abc9__
)));
341 AigerReader
reader(design
, ifs
, ID($__abc9__
), "" /* clk_name */, buffer
.c_str() /* map_filename */, true /* wideports */);
342 reader
.parse_xaiger(box_lookup
);
346 Pass::call_on_module(design
, design
->module(ID($__abc9__
)), stringf("write_verilog -noexpr -norename -selected"));
349 log_header(design
, "Re-integrating ABC9 results.\n");
350 RTLIL::Module
*mapped_mod
= design
->module(ID($__abc9__
));
351 if (mapped_mod
== NULL
)
352 log_error("ABC output file does not contain a module `$__abc9__'.\n");
354 for (auto &it
: mapped_mod
->wires_
) {
355 RTLIL::Wire
*w
= it
.second
;
356 RTLIL::Wire
*remap_wire
= module
->addWire(remap_name(w
->name
), GetSize(w
));
357 if (markgroups
) remap_wire
->attributes
[ID(abcgroup
)] = map_autoidx
;
360 dict
<IdString
, bool> abc9_box
;
361 vector
<RTLIL::Cell
*> boxes
;
362 for (auto cell
: cells
) {
363 if (cell
->type
.in(ID($_AND_
), ID($_NOT_
), ID($__ABC9_FF_
))) {
364 module
->remove(cell
);
367 auto jt
= abc9_box
.find(cell
->type
);
368 if (jt
== abc9_box
.end()) {
369 RTLIL::Module
* box_module
= design
->module(cell
->type
);
370 jt
= abc9_box
.insert(std::make_pair(cell
->type
, box_module
&& box_module
->attributes
.count(ID(abc9_box_id
)))).first
;
373 auto kt
= cell
->attributes
.find("\\abc9_keep");
374 bool abc9_keep
= false;
375 if (kt
!= cell
->attributes
.end()) {
376 abc9_keep
= kt
->second
.as_bool();
377 cell
->attributes
.erase(kt
);
380 boxes
.emplace_back(cell
);
384 dict
<SigBit
, pool
<IdString
>> bit_drivers
, bit_users
;
385 TopoSort
<IdString
, RTLIL::sort_by_id_str
> toposort
;
386 dict
<RTLIL::Cell
*,RTLIL::Cell
*> not2drivers
;
387 dict
<SigBit
, std::vector
<RTLIL::Cell
*>> bit2sinks
;
389 std::map
<IdString
, int> cell_stats
;
390 for (auto mapped_cell
: mapped_mod
->cells())
392 toposort
.node(mapped_cell
->name
);
394 RTLIL::Cell
*cell
= nullptr;
395 if (mapped_cell
->type
== ID($_NOT_
)) {
396 RTLIL::SigBit a_bit
= mapped_cell
->getPort(ID::A
);
397 RTLIL::SigBit y_bit
= mapped_cell
->getPort(ID::Y
);
398 bit_users
[a_bit
].insert(mapped_cell
->name
);
399 bit_drivers
[y_bit
].insert(mapped_cell
->name
);
402 mapped_cell
->setPort(ID::Y
, module
->addWire(NEW_ID
));
403 RTLIL::Wire
*wire
= module
->wire(remap_name(y_bit
.wire
->name
));
405 module
->connect(RTLIL::SigBit(wire
, y_bit
.offset
), State::S1
);
407 else if (!lut_costs
.empty() || !lut_file
.empty()) {
408 RTLIL::Cell
* driver_lut
= nullptr;
409 // ABC can return NOT gates that drive POs
410 if (!a_bit
.wire
->port_input
) {
411 // If it's not a NOT gate that that comes from a PI directly,
412 // find the driver LUT and clone that to guarantee that we won't
413 // increase the max logic depth
414 // (TODO: Optimise by not cloning unless will increase depth)
415 RTLIL::IdString driver_name
;
416 if (GetSize(a_bit
.wire
) == 1)
417 driver_name
= stringf("%s$lut", a_bit
.wire
->name
.c_str());
419 driver_name
= stringf("%s[%d]$lut", a_bit
.wire
->name
.c_str(), a_bit
.offset
);
420 driver_lut
= mapped_mod
->cell(driver_name
);
424 // If a driver couldn't be found (could be from PI or box CI)
425 // then implement using a LUT
426 cell
= module
->addLut(remap_name(stringf("%s$lut", mapped_cell
->name
.c_str())),
427 RTLIL::SigBit(module
->wires_
.at(remap_name(a_bit
.wire
->name
)), a_bit
.offset
),
428 RTLIL::SigBit(module
->wires_
.at(remap_name(y_bit
.wire
->name
)), y_bit
.offset
),
429 RTLIL::Const::from_string("01"));
430 bit2sinks
[cell
->getPort(ID::A
)].push_back(cell
);
431 cell_stats
[ID($lut
)]++;
434 not2drivers
[mapped_cell
] = driver_lut
;
439 if (cell
&& markgroups
) cell
->attributes
[ID(abcgroup
)] = map_autoidx
;
442 cell_stats
[mapped_cell
->type
]++;
444 RTLIL::Cell
*existing_cell
= nullptr;
445 if (mapped_cell
->type
.in(ID($lut
), ID($__ABC9_FF_
))) {
446 if (mapped_cell
->type
== ID($lut
) &&
447 GetSize(mapped_cell
->getPort(ID::A
)) == 1 &&
448 mapped_cell
->getParam(ID(LUT
)) == RTLIL::Const::from_string("01")) {
449 SigSpec my_a
= module
->wires_
.at(remap_name(mapped_cell
->getPort(ID::A
).as_wire()->name
));
450 SigSpec my_y
= module
->wires_
.at(remap_name(mapped_cell
->getPort(ID::Y
).as_wire()->name
));
451 module
->connect(my_y
, my_a
);
452 if (markgroups
) mapped_cell
->attributes
[ID(abcgroup
)] = map_autoidx
;
456 cell
= module
->addCell(remap_name(mapped_cell
->name
), mapped_cell
->type
);
459 existing_cell
= module
->cell(mapped_cell
->name
);
460 log_assert(existing_cell
);
461 cell
= module
->addCell(remap_name(mapped_cell
->name
), mapped_cell
->type
);
464 if (markgroups
) cell
->attributes
[ID(abcgroup
)] = map_autoidx
;
466 cell
->parameters
= existing_cell
->parameters
;
467 cell
->attributes
= existing_cell
->attributes
;
470 cell
->parameters
= mapped_cell
->parameters
;
471 cell
->attributes
= mapped_cell
->attributes
;
474 RTLIL::Module
* box_module
= design
->module(mapped_cell
->type
);
475 auto abc9_flop
= box_module
&& box_module
->attributes
.count("\\abc9_flop");
476 for (auto &conn
: mapped_cell
->connections()) {
477 RTLIL::SigSpec newsig
;
478 for (auto c
: conn
.second
.chunks()) {
481 //log_assert(c.width == 1);
483 c
.wire
= module
->wires_
.at(remap_name(c
.wire
->name
));
486 cell
->setPort(conn
.first
, newsig
);
489 if (cell
->input(conn
.first
)) {
490 for (auto i
: newsig
)
491 bit2sinks
[i
].push_back(cell
);
492 for (auto i
: conn
.second
)
493 bit_users
[i
].insert(mapped_cell
->name
);
495 if (cell
->output(conn
.first
))
496 for (auto i
: conn
.second
)
497 bit_drivers
[i
].insert(mapped_cell
->name
);
502 for (auto existing_cell
: boxes
) {
503 Cell
*cell
= module
->cell(remap_name(existing_cell
->name
));
505 for (auto &conn
: existing_cell
->connections()) {
506 if (!conn
.second
.is_wire())
508 Wire
*wire
= conn
.second
.as_wire();
509 if (!wire
->get_bool_attribute(ID(abc9_padding
)))
511 cell
->unsetPort(conn
.first
);
512 log_debug("Dropping padded port connection for %s (%s) .%s (%s )\n", log_id(cell
), cell
->type
.c_str(), log_id(conn
.first
), log_signal(conn
.second
));
514 module
->swap_names(cell
, existing_cell
);
516 module
->remove(existing_cell
);
519 // Copy connections (and rename) from mapped_mod to module
520 for (auto conn
: mapped_mod
->connections()) {
521 if (!conn
.first
.is_fully_const()) {
522 auto chunks
= conn
.first
.chunks();
523 for (auto &c
: chunks
)
524 c
.wire
= module
->wires_
.at(remap_name(c
.wire
->name
));
525 conn
.first
= std::move(chunks
);
527 if (!conn
.second
.is_fully_const()) {
528 auto chunks
= conn
.second
.chunks();
529 for (auto &c
: chunks
)
531 c
.wire
= module
->wires_
.at(remap_name(c
.wire
->name
));
532 conn
.second
= std::move(chunks
);
534 module
->connect(conn
);
537 for (auto &it
: cell_stats
)
538 log("ABC RESULTS: %15s cells: %8d\n", it
.first
.c_str(), it
.second
);
539 int in_wires
= 0, out_wires
= 0;
541 // Stitch in mapped_mod's inputs/outputs into module
542 for (auto port
: mapped_mod
->ports
) {
543 RTLIL::Wire
*w
= mapped_mod
->wire(port
);
544 RTLIL::Wire
*wire
= module
->wire(port
);
546 RTLIL::Wire
*remap_wire
= module
->wire(remap_name(port
));
547 RTLIL::SigSpec signal
= RTLIL::SigSpec(wire
, 0, GetSize(remap_wire
));
548 log_assert(GetSize(signal
) >= GetSize(remap_wire
));
551 if (w
->port_output
) {
553 conn
.second
= remap_wire
;
555 module
->connect(conn
);
557 else if (w
->port_input
) {
558 conn
.first
= remap_wire
;
559 conn
.second
= signal
;
561 module
->connect(conn
);
565 for (auto &it
: bit_users
)
566 if (bit_drivers
.count(it
.first
))
567 for (auto driver_cell
: bit_drivers
.at(it
.first
))
568 for (auto user_cell
: it
.second
)
569 toposort
.edge(driver_cell
, user_cell
);
570 bool no_loops
YS_ATTRIBUTE(unused
) = toposort
.sort();
571 log_assert(no_loops
);
573 for (auto ii
= toposort
.sorted
.rbegin(); ii
!= toposort
.sorted
.rend(); ii
++) {
574 RTLIL::Cell
*not_cell
= mapped_mod
->cell(*ii
);
575 log_assert(not_cell
);
576 if (not_cell
->type
!= ID($_NOT_
))
578 auto it
= not2drivers
.find(not_cell
);
579 if (it
== not2drivers
.end())
581 RTLIL::Cell
*driver_lut
= it
->second
;
582 RTLIL::SigBit a_bit
= not_cell
->getPort(ID::A
);
583 RTLIL::SigBit y_bit
= not_cell
->getPort(ID::Y
);
584 RTLIL::Const driver_mask
;
586 a_bit
.wire
= module
->wires_
.at(remap_name(a_bit
.wire
->name
));
587 y_bit
.wire
= module
->wires_
.at(remap_name(y_bit
.wire
->name
));
589 auto jt
= bit2sinks
.find(a_bit
);
590 if (jt
== bit2sinks
.end())
593 for (auto sink_cell
: jt
->second
)
594 if (sink_cell
->type
!= ID($lut
))
597 // Push downstream LUTs past inverter
598 for (auto sink_cell
: jt
->second
) {
599 SigSpec A
= sink_cell
->getPort(ID::A
);
600 RTLIL::Const mask
= sink_cell
->getParam(ID(LUT
));
602 for (; index
< GetSize(A
); index
++)
603 if (A
[index
] == a_bit
)
605 log_assert(index
< GetSize(A
));
607 while (i
< GetSize(mask
)) {
608 for (int j
= 0; j
< (1 << index
); j
++)
609 std::swap(mask
[i
+j
], mask
[i
+j
+(1 << index
)]);
613 sink_cell
->setPort(ID::A
, A
);
614 sink_cell
->setParam(ID(LUT
), mask
);
617 // Since we have rewritten all sinks (which we know
618 // to be only LUTs) to be after the inverter, we can
619 // go ahead and clone the LUT with the expectation
620 // that the original driving LUT will become dangling
621 // and get cleaned away
623 driver_mask
= driver_lut
->getParam(ID(LUT
));
624 for (auto &b
: driver_mask
.bits
) {
625 if (b
== RTLIL::State::S0
) b
= RTLIL::State::S1
;
626 else if (b
== RTLIL::State::S1
) b
= RTLIL::State::S0
;
628 auto cell
= module
->addLut(NEW_ID
,
629 driver_lut
->getPort(ID::A
),
632 for (auto &bit
: cell
->connections_
.at(ID::A
)) {
633 bit
.wire
= module
->wires_
.at(remap_name(bit
.wire
->name
));
634 bit2sinks
[bit
].push_back(cell
);
638 //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
639 log("ABC RESULTS: input signals: %8d\n", in_wires
);
640 log("ABC RESULTS: output signals: %8d\n", out_wires
);
642 design
->remove(mapped_mod
);
646 // log("Don't call ABC as there is nothing to map.\n");
652 struct Abc9MapPass
: public Pass
{
653 Abc9MapPass() : Pass("abc9_map", "use ABC9 for technology mapping") { }
654 void help() YS_OVERRIDE
656 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
658 log(" abc9_map [options] [selection]\n");
660 log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
661 log("library to a target architecture.\n");
663 log(" -exe <command>\n");
665 log(" use the specified command instead of \"" ABCEXTERNAL
"\" to execute ABC.\n");
667 log(" use the specified command instead of \"<yosys-bindir>/yosys-abc\" to execute ABC.\n");
669 log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
671 log(" -script <file>\n");
672 log(" use the specified ABC script file instead of the default script.\n");
674 log(" if <file> starts with a plus sign (+), then the rest of the filename\n");
675 log(" string is interpreted as the command string to be passed to ABC. The\n");
676 log(" leading plus sign is removed and all commas (,) in the string are\n");
677 log(" replaced with blanks before the string is passed to ABC.\n");
679 log(" if no -script parameter is given, the following scripts are used:\n");
681 log(" for -lut/-luts (only one LUT size):\n");
682 log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT
/*"; lutpack {S}"*/).c_str());
684 log(" for -lut/-luts (different LUT sizes):\n");
685 log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT
).c_str());
688 log(" use different default scripts that are slightly faster (at the cost\n");
689 log(" of output quality):\n");
691 log(" for -lut/-luts:\n");
692 log("%s\n", fold_abc9_cmd(ABC_FAST_COMMAND_LUT
).c_str());
694 log(" -D <picoseconds>\n");
695 log(" set delay target. the string {D} in the default scripts above is\n");
696 log(" replaced by this option when used, and an empty string otherwise\n");
697 log(" (indicating best possible delay).\n");
698 // log(" This also replaces 'dretime' with 'dretime; retime -o {D}' in the\n");
699 // log(" default scripts above.\n");
701 // log(" -S <num>\n");
702 // log(" maximum number of LUT inputs shared.\n");
703 // log(" (replaces {S} in the default scripts above, default: -S 1)\n");
705 log(" -lut <width>\n");
706 log(" generate netlist using luts of (max) the specified width.\n");
708 log(" -lut <w1>:<w2>\n");
709 log(" generate netlist using luts of (max) the specified width <w2>. All\n");
710 log(" luts with width <= <w1> have constant cost. for luts larger than <w1>\n");
711 log(" the area cost doubles with each additional input bit. the delay cost\n");
712 log(" is still constant for all lut widths.\n");
714 log(" -lut <file>\n");
715 log(" pass this file with lut library to ABC.\n");
717 log(" -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..\n");
718 log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
719 log(" 2, 3, .. inputs.\n");
722 // log(" also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many\n");
723 // log(" clock domains are automatically partitioned in clock domains and each\n");
724 // log(" domain is passed through ABC independently.\n");
726 // log(" -clk [!]<clock-signal-name>[,[!]<enable-signal-name>]\n");
727 // log(" use only the specified clock domain. this is like -dff, but only FF\n");
728 // log(" cells that belong to the specified clock domain are used.\n");
730 // log(" -keepff\n");
731 // log(" set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
732 // log(" them, for example for equivalence checking.)\n");
735 log(" print the temp dir name in log. usually this is suppressed so that the\n");
736 log(" command output is identical across runs.\n");
738 log(" -markgroups\n");
739 log(" set a 'abcgroup' attribute on all objects created by ABC. The value of\n");
740 log(" this attribute is a unique integer for each ABC process started. This\n");
741 log(" is useful for debugging the partitioning of clock domains.\n");
743 log(" -box <file>\n");
744 log(" pass this file with box library to ABC. Use with -lut.\n");
746 log(" -tempdir <dir>\n");
747 log(" use this as the temp dir.\n");
749 log("Note that this is a logic optimization pass within Yosys that is calling ABC\n");
750 log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
751 log("ABC on logic snippets extracted from your design. You will not get any useful\n");
752 log("output when passing an ABC script that writes a file. Instead write your full\n");
753 log("design as BLIF file with write_blif and then load that into ABC externally if\n");
754 log("you want to use ABC to convert your design into another format.\n");
756 log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
759 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
761 log_header(design
, "Executing ABC9_MAP pass (technology mapping using ABC9).\n");
765 std::string exe_file
= ABCEXTERNAL
;
767 std::string exe_file
= proc_self_dirname() + "yosys-abc";
769 std::string script_file
, clk_str
, box_file
, lut_file
;
770 std::string delay_target
, lutin_shared
= "-S 1", wire_delay
;
771 std::string tempdir_name
;
772 bool fast_mode
= false;
773 bool show_tempdir
= false;
775 vector
<int> lut_costs
;
785 if (!check_file_exists(exe_file
+ ".exe") && check_file_exists(proc_self_dirname() + "..\\yosys-abc.exe"))
786 exe_file
= proc_self_dirname() + "..\\yosys-abc";
792 if (!getcwd(pwd
, sizeof(pwd
))) {
793 log_cmd_error("getcwd failed: %s\n", strerror(errno
));
796 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
797 std::string arg
= args
[argidx
];
798 if (arg
== "-exe" && argidx
+1 < args
.size()) {
799 exe_file
= args
[++argidx
];
802 if (arg
== "-script" && argidx
+1 < args
.size()) {
803 script_file
= args
[++argidx
];
804 rewrite_filename(script_file
);
805 if (!script_file
.empty() && !is_absolute_path(script_file
) && script_file
[0] != '+')
806 script_file
= std::string(pwd
) + "/" + script_file
;
809 if (arg
== "-D" && argidx
+1 < args
.size()) {
810 delay_target
= "-D " + args
[++argidx
];
813 //if (arg == "-S" && argidx+1 < args.size()) {
814 // lutin_shared = "-S " + args[++argidx];
817 if (arg
== "-lut" && argidx
+1 < args
.size()) {
818 string arg
= args
[++argidx
];
819 if (arg
.find_first_not_of("0123456789:") == std::string::npos
) {
820 size_t pos
= arg
.find_first_of(':');
821 int lut_mode
= 0, lut_mode2
= 0;
822 if (pos
!= string::npos
) {
823 lut_mode
= atoi(arg
.substr(0, pos
).c_str());
824 lut_mode2
= atoi(arg
.substr(pos
+1).c_str());
826 lut_mode
= atoi(arg
.c_str());
827 lut_mode2
= lut_mode
;
830 for (int i
= 0; i
< lut_mode
; i
++)
831 lut_costs
.push_back(1);
832 for (int i
= lut_mode
; i
< lut_mode2
; i
++)
833 lut_costs
.push_back(2 << (i
- lut_mode
));
837 rewrite_filename(lut_file
);
838 if (!lut_file
.empty() && !is_absolute_path(lut_file
) && lut_file
[0] != '+')
839 lut_file
= std::string(pwd
) + "/" + lut_file
;
843 if (arg
== "-luts" && argidx
+1 < args
.size()) {
845 for (auto &tok
: split_tokens(args
[++argidx
], ",")) {
846 auto parts
= split_tokens(tok
, ":");
847 if (GetSize(parts
) == 0 && !lut_costs
.empty())
848 lut_costs
.push_back(lut_costs
.back());
849 else if (GetSize(parts
) == 1)
850 lut_costs
.push_back(atoi(parts
.at(0).c_str()));
851 else if (GetSize(parts
) == 2)
852 while (GetSize(lut_costs
) < atoi(parts
.at(0).c_str()))
853 lut_costs
.push_back(atoi(parts
.at(1).c_str()));
855 log_cmd_error("Invalid -luts syntax.\n");
859 if (arg
== "-fast") {
863 if (arg
== "-showtmp") {
867 if (arg
== "-markgroups") {
871 if (arg
== "-box" && argidx
+1 < args
.size()) {
872 box_file
= args
[++argidx
];
875 if (arg
== "-W" && argidx
+1 < args
.size()) {
876 wire_delay
= "-W " + args
[++argidx
];
879 if (arg
== "-nomfs") {
883 if (arg
== "-tempdir" && argidx
+1 < args
.size()) {
884 tempdir_name
= args
[++argidx
];
889 extra_args(args
, argidx
, design
);
891 // ABC expects a box file for XAIG
892 if (box_file
.empty())
893 box_file
= "+/dummy.box";
895 rewrite_filename(box_file
);
896 if (!box_file
.empty() && !is_absolute_path(box_file
) && box_file
[0] != '+')
897 box_file
= std::string(pwd
) + "/" + box_file
;
899 if (tempdir_name
.empty())
900 log_cmd_error("abc9_map '-tempdir' option is mandatory.\n");
902 dict
<int,IdString
> box_lookup
;
903 for (auto m
: design
->modules()) {
904 auto it
= m
->attributes
.find(ID(abc9_box_id
));
905 if (it
== m
->attributes
.end())
907 if (m
->name
.begins_with("$paramod"))
909 auto id
= it
->second
.as_int();
910 auto r
= box_lookup
.insert(std::make_pair(id
, m
->name
));
912 log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
913 log_id(m
), id
, log_id(r
.first
->second
));
914 log_assert(r
.second
);
916 RTLIL::Wire
*carry_in
= nullptr, *carry_out
= nullptr;
917 for (auto p
: m
->ports
) {
920 if (w
->attributes
.count(ID(abc9_carry
))) {
923 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m
));
926 else if (w
->port_output
) {
928 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m
));
933 if (carry_in
|| carry_out
) {
934 if (carry_in
&& !carry_out
)
935 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m
));
936 if (!carry_in
&& carry_out
)
937 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m
));
938 // Make carry_in the last PI, and carry_out the last PO
939 // since ABC requires it this way
940 auto &ports
= m
->ports
;
941 for (auto it
= ports
.begin(); it
!= ports
.end(); ) {
942 RTLIL::Wire
* w
= m
->wire(*it
);
944 if (w
== carry_in
|| w
== carry_out
) {
945 it
= ports
.erase(it
);
948 if (w
->port_id
> carry_in
->port_id
)
950 if (w
->port_id
> carry_out
->port_id
)
952 log_assert(w
->port_input
|| w
->port_output
);
953 log_assert(ports
[w
->port_id
-1] == w
->name
);
956 ports
.push_back(carry_in
->name
);
957 carry_in
->port_id
= ports
.size();
958 ports
.push_back(carry_out
->name
);
959 carry_out
->port_id
= ports
.size();
963 for (auto mod
: design
->selected_modules())
965 if (mod
->processes
.size() > 0) {
966 log("Skipping module %s as it contains processes.\n", log_id(mod
));
970 const std::vector
<RTLIL::Cell
*> all_cells
= mod
->selected_cells();
972 abc9_module(design
, mod
, script_file
, exe_file
, lut_costs
,
973 delay_target
, lutin_shared
, fast_mode
, all_cells
, show_tempdir
,
974 box_file
, lut_file
, wire_delay
, box_lookup
, nomfs
, tempdir_name
);
981 PRIVATE_NAMESPACE_END