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dcb8a8a78901190466a2a0a3c0f9092a3975fb9e
[yosys.git] / passes / techmap / abc9_ops.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/utils.h"
24
25 USING_YOSYS_NAMESPACE
26 PRIVATE_NAMESPACE_BEGIN
27
28 void break_scc(RTLIL::Module *module)
29 {
30 // For every unique SCC found, (arbitrarily) find the first
31 // cell in the component, and convert all wires driven by
32 // its output ports into a new PO, and drive its previous
33 // sinks with a new PI
34 pool<RTLIL::Const> ids_seen;
35 for (auto cell : module->selected_cells()) {
36 auto it = cell->attributes.find(ID(abc9_scc_id));
37 if (it == cell->attributes.end())
38 continue;
39 auto r = ids_seen.insert(it->second);
40 cell->attributes.erase(it);
41 if (!r.second)
42 continue;
43 for (auto &c : cell->connections_) {
44 if (c.second.is_fully_const()) continue;
45 if (cell->output(c.first)) {
46 SigBit b = c.second.as_bit();
47 Wire *w = b.wire;
48 if (w->port_input) {
49 // In this case, hopefully the loop break has been already created
50 // Get the non-prefixed wire
51 Wire *wo = module->wire(stringf("%s.abco", b.wire->name.c_str()));
52 log_assert(wo != nullptr);
53 log_assert(wo->port_output);
54 log_assert(b.offset < GetSize(wo));
55 c.second = RTLIL::SigBit(wo, b.offset);
56 }
57 else {
58 // Create a new output/input loop break
59 w->port_input = true;
60 w = module->wire(stringf("%s.abco", w->name.c_str()));
61 if (!w) {
62 w = module->addWire(stringf("%s.abco", b.wire->name.c_str()), GetSize(b.wire));
63 w->port_output = true;
64 }
65 else {
66 log_assert(w->port_input);
67 log_assert(b.offset < GetSize(w));
68 }
69 w->set_bool_attribute(ID(abc9_scc_break));
70 c.second = RTLIL::SigBit(w, b.offset);
71 }
72 }
73 }
74 }
75
76 module->fixup_ports();
77 }
78
79 void unbreak_scc(RTLIL::Module *module)
80 {
81 // Now 'unexpose' those wires by undoing
82 // the expose operation -- remove them from PO/PI
83 // and re-connecting them back together
84 for (auto wire : module->wires()) {
85 auto it = wire->attributes.find(ID(abc9_scc_break));
86 if (it != wire->attributes.end()) {
87 wire->attributes.erase(it);
88 log_assert(wire->port_output);
89 wire->port_output = false;
90 std::string name = wire->name.str();
91 RTLIL::Wire *i_wire = module->wire(name.substr(0, GetSize(name) - 5));
92 log_assert(i_wire);
93 log_assert(i_wire->port_input);
94 i_wire->port_input = false;
95 module->connect(i_wire, wire);
96 }
97 }
98 module->fixup_ports();
99 }
100
101 void prep_dff(RTLIL::Module *module)
102 {
103 auto design = module->design;
104 log_assert(design);
105
106 SigMap assign_map(module);
107
108 typedef SigSpec clkdomain_t;
109 dict<clkdomain_t, int> clk_to_mergeability;
110
111 //if (dff_mode)
112 for (auto cell : module->selected_cells()) {
113 if (cell->type != "$__ABC9_FF_")
114 continue;
115
116 Wire *abc9_clock_wire = module->wire(stringf("%s.clock", cell->name.c_str()));
117 if (abc9_clock_wire == NULL)
118 log_error("'%s.clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
119 SigSpec abc9_clock = assign_map(abc9_clock_wire);
120
121 clkdomain_t key(abc9_clock);
122
123 auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
124 auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
125 log_assert(r2.second);
126
127 Wire *abc9_init_wire = module->wire(stringf("%s.init", cell->name.c_str()));
128 if (abc9_init_wire == NULL)
129 log_error("'%s.init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
130 log_assert(GetSize(abc9_init_wire) == 1);
131 SigSpec abc9_init = assign_map(abc9_init_wire);
132 if (!abc9_init.is_fully_const())
133 log_error("'%s.init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
134 r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
135 log_assert(r2.second);
136 }
137 //else
138 // for (auto cell : module->selected_cells()) {
139 // auto inst_module = design->module(cell->type);
140 // if (!inst_module || !inst_module->get_bool_attribute("\\abc9_flop"))
141 // continue;
142 // cell->set_bool_attribute("\\abc9_keep");
143 // }
144
145 RTLIL::Module *holes_module = design->module(stringf("%s$holes", module->name.c_str()));
146 if (holes_module) {
147 dict<SigSig, SigSig> replace;
148 for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
149 auto cell = it->second;
150 if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
151 "$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
152 SigBit D = cell->getPort("\\D");
153 SigBit Q = cell->getPort("\\Q");
154 // Remove the DFF cell from what needs to be a combinatorial box
155 it = holes_module->cells_.erase(it);
156 Wire *port;
157 if (GetSize(Q.wire) == 1)
158 port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
159 else
160 port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
161 log_assert(port);
162 // Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;"
163 // in order to extract the combinatorial control logic that feeds the box
164 // (i.e. clock enable, synchronous reset, etc.)
165 replace.insert(std::make_pair(SigSig(port,Q), SigSig(port,D)));
166 // Since `flatten` above would have created wires named "<cell>.Q",
167 // extract the pre-techmap cell name
168 auto pos = Q.wire->name.str().rfind(".");
169 log_assert(pos != std::string::npos);
170 IdString driver = Q.wire->name.substr(0, pos);
171 // And drive the signal that was previously driven by "DFF.Q" (typically
172 // used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
173 // wire (which itself is driven an input port) we inserted above
174 Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
175 log_assert(currQ);
176 holes_module->connect(Q, currQ);
177 }
178 else
179 ++it;
180 }
181
182 for (auto &conn : holes_module->connections_) {
183 auto it = replace.find(conn);
184 if (it != replace.end())
185 conn = it->second;
186 }
187 }
188 }
189
190 void prep_holes(RTLIL::Module *module)
191 {
192 auto design = module->design;
193 log_assert(design);
194
195 SigMap sigmap(module);
196
197 // TODO: Speed up toposort -- ultimately we care about
198 // box ordering, but not individual AIG cells
199 dict<SigBit, pool<IdString>> bit_drivers, bit_users;
200 TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
201 bool abc9_box_seen = false;
202
203 for (auto cell : module->selected_cells()) {
204 if (cell->type == "$_NOT_")
205 {
206 SigBit A = sigmap(cell->getPort("\\A").as_bit());
207 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
208 toposort.node(cell->name);
209 bit_users[A].insert(cell->name);
210 bit_drivers[Y].insert(cell->name);
211 continue;
212 }
213
214 if (cell->type == "$_AND_")
215 {
216 SigBit A = sigmap(cell->getPort("\\A").as_bit());
217 SigBit B = sigmap(cell->getPort("\\B").as_bit());
218 SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
219 toposort.node(cell->name);
220 bit_users[A].insert(cell->name);
221 bit_users[B].insert(cell->name);
222 bit_drivers[Y].insert(cell->name);
223 continue;
224 }
225
226 if (cell->type == "$__ABC9_FF_")
227 continue;
228
229 RTLIL::Module* inst_module = design->module(cell->type);
230 if (inst_module) {
231 if (!inst_module->attributes.count("\\abc9_box_id") || cell->get_bool_attribute("\\abc9_keep"))
232 continue;
233
234 for (const auto &conn : cell->connections()) {
235 auto port_wire = inst_module->wire(conn.first);
236 // Ignore inout for the sake of topographical ordering
237 if (port_wire->port_input && !port_wire->port_output)
238 for (auto bit : sigmap(conn.second))
239 bit_users[bit].insert(cell->name);
240 if (port_wire->port_output)
241 for (auto bit : sigmap(conn.second))
242 bit_drivers[bit].insert(cell->name);
243 }
244
245 abc9_box_seen = true;
246
247 toposort.node(cell->name);
248 }
249 }
250
251 if (!abc9_box_seen)
252 return;
253
254 for (auto &it : bit_users)
255 if (bit_drivers.count(it.first))
256 for (auto driver_cell : bit_drivers.at(it.first))
257 for (auto user_cell : it.second)
258 toposort.edge(driver_cell, user_cell);
259
260 #if 0
261 toposort.analyze_loops = true;
262 #endif
263 bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
264 #if 0
265 unsigned i = 0;
266 for (auto &it : toposort.loops) {
267 log(" loop %d\n", i++);
268 for (auto cell_name : it) {
269 auto cell = module->cell(cell_name);
270 log_assert(cell);
271 log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
272 }
273 }
274 #endif
275 log_assert(no_loops);
276
277 vector<Cell*> box_list;
278 for (auto cell_name : toposort.sorted) {
279 RTLIL::Cell *cell = module->cell(cell_name);
280 log_assert(cell);
281
282 RTLIL::Module* box_module = design->module(cell->type);
283 if (!box_module || !box_module->attributes.count("\\abc9_box_id")
284 || cell->get_bool_attribute("\\abc9_keep"))
285 continue;
286
287 bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
288
289 // Fully pad all unused input connections of this box cell with S0
290 // Fully pad all undriven output connections of this box cell with anonymous wires
291 // NB: Assume box_module->ports are sorted alphabetically
292 // (as RTLIL::Module::fixup_ports() would do)
293 for (const auto &port_name : box_module->ports) {
294 RTLIL::Wire* w = box_module->wire(port_name);
295 log_assert(w);
296 auto it = cell->connections_.find(port_name);
297 if (w->port_input) {
298 RTLIL::SigSpec rhs;
299 if (it != cell->connections_.end()) {
300 if (GetSize(it->second) < GetSize(w))
301 it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second)));
302 rhs = it->second;
303 }
304 else {
305 rhs = RTLIL::SigSpec(State::S0, GetSize(w));
306 cell->setPort(port_name, rhs);
307 }
308 }
309 if (w->port_output) {
310 RTLIL::SigSpec rhs;
311 auto it = cell->connections_.find(w->name);
312 if (it != cell->connections_.end()) {
313 if (GetSize(it->second) < GetSize(w))
314 it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
315 rhs = it->second;
316 }
317 else {
318 Wire *wire = module->addWire(NEW_ID, GetSize(w));
319 if (blackbox)
320 wire->set_bool_attribute(ID(abc9_padding));
321 rhs = wire;
322 cell->setPort(port_name, rhs);
323 }
324 }
325 }
326
327 box_list.emplace_back(cell);
328 }
329 log_assert(!box_list.empty());
330
331 RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
332 log_assert(holes_module);
333 holes_module->set_bool_attribute("\\abc9_holes");
334
335 dict<IdString, Cell*> cell_cache;
336
337 int port_id = 1;
338 for (auto cell : box_list) {
339 RTLIL::Module* orig_box_module = design->module(cell->type);
340 log_assert(orig_box_module);
341 IdString derived_name = orig_box_module->derive(design, cell->parameters);
342 RTLIL::Module* box_module = design->module(derived_name);
343 if (box_module->has_processes())
344 Pass::call_on_module(design, box_module, "proc");
345
346 int box_inputs = 0;
347 auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
348 Cell *holes_cell = r.first->second;
349 if (r.second && box_module->get_bool_attribute("\\whitebox")) {
350 holes_cell = holes_module->addCell(cell->name, cell->type);
351 holes_cell->parameters = cell->parameters;
352 r.first->second = holes_cell;
353
354 // Since Module::derive() will create a new module, there
355 // is a chance that the ports will be alphabetically ordered
356 // again, which is a problem when carry-chains are involved.
357 // Inherit the port ordering from the original module here...
358 // (and set the port_id below, when iterating through those)
359 log_assert(GetSize(box_module->ports) == GetSize(orig_box_module->ports));
360 box_module->ports = orig_box_module->ports;
361 }
362
363 // NB: Assume box_module->ports are sorted alphabetically
364 // (as RTLIL::Module::fixup_ports() would do)
365 int box_port_id = 1;
366 for (const auto &port_name : box_module->ports) {
367 RTLIL::Wire *w = box_module->wire(port_name);
368 log_assert(w);
369 if (r.second)
370 w->port_id = box_port_id++;
371 RTLIL::Wire *holes_wire;
372 RTLIL::SigSpec port_sig;
373 if (w->port_input)
374 for (int i = 0; i < GetSize(w); i++) {
375 box_inputs++;
376 holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
377 if (!holes_wire) {
378 holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
379 holes_wire->port_input = true;
380 holes_wire->port_id = port_id++;
381 holes_module->ports.push_back(holes_wire->name);
382 }
383 if (holes_cell)
384 port_sig.append(holes_wire);
385 }
386 if (w->port_output)
387 for (int i = 0; i < GetSize(w); i++) {
388 if (GetSize(w) == 1)
389 holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(w->name)));
390 else
391 holes_wire = holes_module->addWire(stringf("$abc%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
392 holes_wire->port_output = true;
393 holes_wire->port_id = port_id++;
394 holes_module->ports.push_back(holes_wire->name);
395 if (holes_cell)
396 port_sig.append(holes_wire);
397 else
398 holes_module->connect(holes_wire, State::S0);
399 }
400 if (!port_sig.empty()) {
401 if (r.second)
402 holes_cell->setPort(w->name, port_sig);
403 else
404 holes_module->connect(holes_cell->getPort(w->name), port_sig);
405 }
406 }
407
408 // For flops only, create an extra 1-bit input that drives a new wire
409 // called "<cell>.$abc9_currQ" that is used below
410 if (box_module->get_bool_attribute("\\abc9_flop")) {
411 log_assert(holes_cell);
412
413 box_inputs++;
414 Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
415 if (!holes_wire) {
416 holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
417 holes_wire->port_input = true;
418 holes_wire->port_id = port_id++;
419 holes_module->ports.push_back(holes_wire->name);
420 }
421 Wire *w = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
422 holes_module->connect(w, holes_wire);
423 }
424 }
425 }
426
427 struct Abc9OpsPass : public Pass {
428 Abc9OpsPass() : Pass("abc9_ops", "helper functions for ABC9") { }
429 void help() YS_OVERRIDE
430 {
431 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
432 log("\n");
433 log(" abc9_ops [options] [selection]\n");
434 log("\n");
435 }
436 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
437 {
438 log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n");
439 log_push();
440
441 bool break_scc_mode = false;
442 bool unbreak_scc_mode = false;
443 bool prep_dff_mode = false;
444 bool prep_holes_mode = false;
445
446 size_t argidx;
447 for (argidx = 1; argidx < args.size(); argidx++) {
448 std::string arg = args[argidx];
449 if (arg == "-break_scc") {
450 break_scc_mode = true;
451 continue;
452 }
453 if (arg == "-unbreak_scc") {
454 unbreak_scc_mode = true;
455 continue;
456 }
457 if (arg == "-prep_dff") {
458 prep_dff_mode = true;
459 continue;
460 }
461 if (arg == "-prep_holes") {
462 prep_holes_mode = true;
463 continue;
464 }
465 break;
466 }
467 extra_args(args, argidx, design);
468
469 for (auto mod : design->selected_modules()) {
470 if (mod->get_blackbox_attribute())
471 continue;
472 if (mod->get_bool_attribute("\\abc9_holes"))
473 continue;
474
475 if (mod->processes.size() > 0) {
476 log("Skipping module %s as it contains processes.\n", log_id(mod));
477 continue;
478 }
479
480 if (break_scc_mode)
481 break_scc(mod);
482 if (unbreak_scc_mode)
483 unbreak_scc(mod);
484 if (prep_dff_mode)
485 prep_dff(mod);
486 if (prep_holes_mode)
487 prep_holes(mod);
488 }
489 }
490 } Abc9OpsPass;
491
492 PRIVATE_NAMESPACE_END