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Auto-generate .box/.lut files from specify blocks
[yosys.git] / passes / techmap / abc9_ops.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/utils.h"
24 #include "kernel/celltypes.h"
25
26 USING_YOSYS_NAMESPACE
27 PRIVATE_NAMESPACE_BEGIN
28
29 int map_autoidx;
30
31 inline std::string remap_name(RTLIL::IdString abc9_name)
32 {
33 return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
34 }
35
36 void check(RTLIL::Design *design)
37 {
38 dict<IdString,IdString> box_lookup;
39 for (auto m : design->modules()) {
40 if (m->name.begins_with("$paramod"))
41 continue;
42
43 auto flop = m->get_bool_attribute(ID(abc9_flop));
44 auto it = m->attributes.find(ID(abc9_box_id));
45 if (!flop) {
46 if (it == m->attributes.end())
47 continue;
48 auto id = it->second.as_int();
49 auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
50 if (!r.second)
51 log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
52 log_id(m), id, log_id(r.first->second));
53 }
54
55 // Make carry in the last PI, and carry out the last PO
56 // since ABC requires it this way
57 IdString carry_in, carry_out;
58 for (const auto &port_name : m->ports) {
59 auto w = m->wire(port_name);
60 log_assert(w);
61 if (w->get_bool_attribute("\\abc9_carry")) {
62 if (w->port_input) {
63 if (carry_in != IdString())
64 log_error("Module '%s' contains more than one (* abc9_carry *) input port.\n", log_id(m));
65 carry_in = port_name;
66 }
67 if (w->port_output) {
68 if (carry_out != IdString())
69 log_error("Module '%s' contains more than one (* abc9_carry *) output port.\n", log_id(m));
70 carry_out = port_name;
71 }
72 }
73
74 auto it = w->attributes.find("\\abc9_arrival");
75 if (it != w->attributes.end()) {
76 int count = 0;
77 if (it->second.flags == 0) {
78 if (it->second.as_int() < 0)
79 log_error("%s.%s has negative arrival value %d!\n", log_id(m), log_id(port_name),
80 it->second.as_int());
81 count++;
82 }
83 else
84 for (const auto &tok : split_tokens(it->second.decode_string())) {
85 if (tok.find_first_not_of("0123456789") != std::string::npos)
86 log_error("%s.%s has non-integer arrival value '%s'!\n", log_id(m), log_id(port_name),
87 tok.c_str());
88 if (atoi(tok.c_str()) < 0)
89 log_error("%s.%s has negative arrival value %s!\n", log_id(m), log_id(port_name),
90 tok.c_str());
91 count++;
92 }
93 if (count > 1 && count != GetSize(w))
94 log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(m), log_id(port_name),
95 GetSize(w), log_signal(it->second), count);
96 }
97
98 it = w->attributes.find("\\abc9_required");
99 if (it != w->attributes.end()) {
100 int count = 0;
101 if (it->second.flags == 0) {
102 if (it->second.as_int() < 0)
103 log_error("%s.%s has negative required value %d!\n", log_id(m), log_id(port_name),
104 it->second.as_int());
105 count++;
106 }
107 else
108 for (const auto &tok : split_tokens(it->second.decode_string())) {
109 if (tok.find_first_not_of("0123456789") != std::string::npos)
110 log_error("%s.%s has non-integer required value '%s'!\n", log_id(m), log_id(port_name),
111 tok.c_str());
112 if (atoi(tok.c_str()) < 0)
113 log_error("%s.%s has negative required value %s!\n", log_id(m), log_id(port_name),
114 tok.c_str());
115 count++;
116 }
117 if (count > 1 && count != GetSize(w))
118 log_error("%s.%s is %d bits wide but abc9_required = %s has %d value(s)!\n", log_id(m), log_id(port_name),
119 GetSize(w), log_signal(it->second), count);
120 }
121 }
122
123 if (carry_in != IdString() && carry_out == IdString())
124 log_error("Module '%s' contains an (* abc9_carry *) input port but no output port.\n", log_id(m));
125 if (carry_in == IdString() && carry_out != IdString())
126 log_error("Module '%s' contains an (* abc9_carry *) output port but no input port.\n", log_id(m));
127
128 if (flop) {
129 int num_outputs = 0;
130 for (auto port_name : m->ports) {
131 auto wire = m->wire(port_name);
132 if (wire->port_output) num_outputs++;
133 }
134 if (num_outputs != 1)
135 log_error("Module '%s' with (* abc9_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs);
136 }
137 }
138 }
139
140 void mark_scc(RTLIL::Module *module)
141 {
142 // For every unique SCC found, (arbitrarily) find the first
143 // cell in the component, and convert all wires driven by
144 // its output ports into a new PO, and drive its previous
145 // sinks with a new PI
146 pool<RTLIL::Const> ids_seen;
147 for (auto cell : module->cells()) {
148 auto it = cell->attributes.find(ID(abc9_scc_id));
149 if (it == cell->attributes.end())
150 continue;
151 auto id = it->second;
152 auto r = ids_seen.insert(id);
153 cell->attributes.erase(it);
154 if (!r.second)
155 continue;
156 for (auto &c : cell->connections_) {
157 if (c.second.is_fully_const()) continue;
158 if (cell->output(c.first)) {
159 SigBit b = c.second.as_bit();
160 Wire *w = b.wire;
161 w->set_bool_attribute(ID::keep);
162 w->attributes[ID(abc9_scc_id)] = id.as_int();
163 }
164 }
165 }
166
167 module->fixup_ports();
168 }
169
170 void prep_dff(RTLIL::Module *module)
171 {
172 auto design = module->design;
173 log_assert(design);
174
175 SigMap assign_map(module);
176
177 typedef SigSpec clkdomain_t;
178 dict<clkdomain_t, int> clk_to_mergeability;
179
180 for (auto cell : module->cells()) {
181 if (cell->type != "$__ABC9_FF_")
182 continue;
183
184 Wire *abc9_clock_wire = module->wire(stringf("%s.clock", cell->name.c_str()));
185 if (abc9_clock_wire == NULL)
186 log_error("'%s.clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
187 SigSpec abc9_clock = assign_map(abc9_clock_wire);
188
189 clkdomain_t key(abc9_clock);
190
191 auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
192 auto r2 = cell->attributes.insert(ID(abc9_mergeability));;
193 log_assert(r2.second);
194 r2.first->second = r.first->second;
195 }
196
197 RTLIL::Module *holes_module = design->module(stringf("%s$holes", module->name.c_str()));
198 if (holes_module) {
199 SigMap sigmap(holes_module);
200
201 dict<SigSpec, SigSpec> replace;
202 for (auto cell : holes_module->cells().to_vector()) {
203 if (!cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
204 "$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_"))
205 continue;
206 SigBit D = cell->getPort("\\D");
207 SigBit Q = cell->getPort("\\Q");
208 // Emulate async control embedded inside $_DFF_* cell with mux in front of D
209 if (cell->type.in("$_DFF_NN0_", "$_DFF_PN0_"))
210 D = holes_module->MuxGate(NEW_ID, State::S0, D, cell->getPort("\\R"));
211 else if (cell->type.in("$_DFF_NN1_", "$_DFF_PN1_"))
212 D = holes_module->MuxGate(NEW_ID, State::S1, D, cell->getPort("\\R"));
213 else if (cell->type.in("$_DFF_NP0_", "$_DFF_PP0_"))
214 D = holes_module->MuxGate(NEW_ID, D, State::S0, cell->getPort("\\R"));
215 else if (cell->type.in("$_DFF_NP1_", "$_DFF_PP1_"))
216 D = holes_module->MuxGate(NEW_ID, D, State::S1, cell->getPort("\\R"));
217 // Remove the $_DFF_* cell from what needs to be a combinatorial box
218 holes_module->remove(cell);
219 Wire *port;
220 if (GetSize(Q.wire) == 1)
221 port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
222 else
223 port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
224 log_assert(port);
225 // Prepare to replace "assign <port> = $_DFF_*.Q;" with "assign <port> = $_DFF_*.D;"
226 // in order to extract just the combinatorial control logic that feeds the box
227 // (i.e. clock enable, synchronous reset, etc.)
228 replace.insert(std::make_pair(Q,D));
229 // Since `flatten` above would have created wires named "<cell>.Q",
230 // extract the pre-techmap cell name
231 auto pos = Q.wire->name.str().rfind(".");
232 log_assert(pos != std::string::npos);
233 IdString driver = Q.wire->name.substr(0, pos);
234 // And drive the signal that was previously driven by "DFF.Q" (typically
235 // used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
236 // wire (which itself is driven an by input port) we inserted above
237 Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
238 log_assert(currQ);
239 holes_module->connect(Q, currQ);
240 }
241
242 for (auto &conn : holes_module->connections_)
243 conn.second = replace.at(sigmap(conn.second), conn.second);
244 }
245 }
246
247 void prep_xaiger(RTLIL::Module *module, bool dff)
248 {
249 auto design = module->design;
250 log_assert(design);
251
252 SigMap sigmap(module);
253
254 dict<SigBit, pool<IdString>> bit_drivers, bit_users;
255 TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
256 dict<IdString, std::vector<IdString>> box_ports;
257
258 for (auto cell : module->cells()) {
259 if (cell->type == "$__ABC9_FF_")
260 continue;
261 if (cell->has_keep_attr())
262 continue;
263
264 auto inst_module = module->design->module(cell->type);
265 bool abc9_flop = inst_module && inst_module->get_bool_attribute("\\abc9_flop");
266 if (abc9_flop && !dff)
267 continue;
268
269 if ((inst_module && inst_module->get_bool_attribute("\\abc9_box")) || abc9_flop) {
270 auto r = box_ports.insert(cell->type);
271 if (r.second) {
272 // Make carry in the last PI, and carry out the last PO
273 // since ABC requires it this way
274 IdString carry_in, carry_out;
275 for (const auto &port_name : inst_module->ports) {
276 auto w = inst_module->wire(port_name);
277 log_assert(w);
278 if (w->get_bool_attribute("\\abc9_carry")) {
279 log_assert(w->port_input != w->port_output);
280 if (w->port_input)
281 carry_in = port_name;
282 else if (w->port_output)
283 carry_out = port_name;
284 }
285 else
286 r.first->second.push_back(port_name);
287 }
288 if (carry_in != IdString()) {
289 r.first->second.push_back(carry_in);
290 r.first->second.push_back(carry_out);
291 }
292 }
293 }
294 else if (!yosys_celltypes.cell_known(cell->type))
295 continue;
296
297 // TODO: Speed up toposort -- we care about box ordering only
298 for (auto conn : cell->connections()) {
299 if (cell->input(conn.first))
300 for (auto bit : sigmap(conn.second))
301 bit_users[bit].insert(cell->name);
302
303 if (cell->output(conn.first) && !abc9_flop)
304 for (auto bit : sigmap(conn.second))
305 bit_drivers[bit].insert(cell->name);
306 }
307 toposort.node(cell->name);
308 }
309
310 if (box_ports.empty())
311 return;
312
313 for (auto &it : bit_users)
314 if (bit_drivers.count(it.first))
315 for (auto driver_cell : bit_drivers.at(it.first))
316 for (auto user_cell : it.second)
317 toposort.edge(driver_cell, user_cell);
318
319 if (ys_debug(1))
320 toposort.analyze_loops = true;
321
322 bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
323
324 if (ys_debug(1)) {
325 unsigned i = 0;
326 for (auto &it : toposort.loops) {
327 log(" loop %d\n", i++);
328 for (auto cell_name : it) {
329 auto cell = module->cell(cell_name);
330 log_assert(cell);
331 log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
332 }
333 }
334 }
335
336 log_assert(no_loops);
337
338 RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
339 log_assert(holes_module);
340 holes_module->set_bool_attribute("\\abc9_holes");
341
342 dict<IdString, Cell*> cell_cache;
343
344 int port_id = 1, box_count = 0;
345 for (auto cell_name : toposort.sorted) {
346 RTLIL::Cell *cell = module->cell(cell_name);
347 log_assert(cell);
348
349 RTLIL::Module* box_module = design->module(cell->type);
350 if (!box_module || (!box_module->get_bool_attribute("\\abc9_box") && !box_module->get_bool_attribute("\\abc9_flop")))
351 continue;
352
353 cell->attributes["\\abc9_box_seq"] = box_count++;
354
355 IdString derived_type = box_module->derive(design, cell->parameters);
356 box_module = design->module(derived_type);
357
358 auto r = cell_cache.insert(derived_type);
359 auto &holes_cell = r.first->second;
360 if (r.second) {
361 if (box_module->has_processes())
362 Pass::call_on_module(design, box_module, "proc");
363
364 if (box_module->get_bool_attribute("\\whitebox")) {
365 holes_cell = holes_module->addCell(cell->name, derived_type);
366
367 if (box_module->has_processes())
368 Pass::call_on_module(design, box_module, "proc");
369
370 int box_inputs = 0;
371 for (auto port_name : box_ports.at(cell->type)) {
372 RTLIL::Wire *w = box_module->wire(port_name);
373 log_assert(w);
374 log_assert(!w->port_input || !w->port_output);
375 auto &conn = holes_cell->connections_[port_name];
376 if (w->port_input) {
377 for (int i = 0; i < GetSize(w); i++) {
378 box_inputs++;
379 RTLIL::Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
380 if (!holes_wire) {
381 holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
382 holes_wire->port_input = true;
383 holes_wire->port_id = port_id++;
384 holes_module->ports.push_back(holes_wire->name);
385 }
386 conn.append(holes_wire);
387 }
388 }
389 else if (w->port_output)
390 conn = holes_module->addWire(stringf("%s.%s", derived_type.c_str(), log_id(port_name)), GetSize(w));
391 }
392
393 // For flops only, create an extra 1-bit input that drives a new wire
394 // called "<cell>.abc9_ff.Q" that is used below
395 if (box_module->get_bool_attribute("\\abc9_flop")) {
396 box_inputs++;
397 Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
398 if (!holes_wire) {
399 holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
400 holes_wire->port_input = true;
401 holes_wire->port_id = port_id++;
402 holes_module->ports.push_back(holes_wire->name);
403 }
404 Wire *Q = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
405 holes_module->connect(Q, holes_wire);
406 }
407 }
408 else // box_module is a blackbox
409 log_assert(holes_cell == nullptr);
410 }
411
412 for (auto port_name : box_ports.at(cell->type)) {
413 RTLIL::Wire *w = box_module->wire(port_name);
414 log_assert(w);
415 if (!w->port_output)
416 continue;
417 Wire *holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(port_name)), GetSize(w));
418 holes_wire->port_output = true;
419 holes_wire->port_id = port_id++;
420 holes_module->ports.push_back(holes_wire->name);
421 if (holes_cell) // whitebox
422 holes_module->connect(holes_wire, holes_cell->getPort(port_name));
423 else // blackbox
424 holes_module->connect(holes_wire, Const(State::S0, GetSize(w)));
425 }
426 }
427 }
428
429 void prep_delays(RTLIL::Design *design)
430 {
431 pool<Module*> flops;
432 std::vector<Cell*> cells;
433 dict<IdString,dict<IdString,std::vector<int>>> requireds_cache;
434 for (auto module : design->selected_modules()) {
435 if (module->processes.size() > 0) {
436 log("Skipping module %s as it contains processes.\n", log_id(module));
437 continue;
438 }
439
440 cells.clear();
441 for (auto cell : module->cells()) {
442 if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_), ID($__ABC9_DELAY)))
443 continue;
444
445 RTLIL::Module* inst_module = module->design->module(cell->type);
446 if (!inst_module)
447 continue;
448 if (!inst_module->get_blackbox_attribute())
449 continue;
450 if (inst_module->get_bool_attribute(ID(abc9_flop))) {
451 IdString derived_type = inst_module->derive(design, cell->parameters);
452 inst_module = design->module(derived_type);
453 log_assert(inst_module);
454 flops.insert(inst_module);
455 continue; // because all flop required times
456 // will be captured in the flop box
457 }
458 if (inst_module->attributes.count(ID(abc9_box)))
459 continue;
460 cells.emplace_back(cell);
461 }
462
463 for (auto cell : cells) {
464 RTLIL::Module* inst_module = module->design->module(cell->type);
465 log_assert(inst_module);
466 auto &cell_requireds = requireds_cache[cell->type];
467 for (auto &conn : cell->connections_) {
468 auto port_wire = inst_module->wire(conn.first);
469 if (!port_wire->port_input)
470 continue;
471
472 auto r = cell_requireds.insert(conn.first);
473 auto &requireds = r.first->second;
474 if (r.second) {
475 auto it = port_wire->attributes.find("\\abc9_required");
476 if (it == port_wire->attributes.end())
477 continue;
478 if (it->second.flags == 0) {
479 int delay = it->second.as_int();
480 requireds.emplace_back(delay);
481 }
482 else
483 for (const auto &tok : split_tokens(it->second.decode_string())) {
484 int delay = atoi(tok.c_str());
485 requireds.push_back(delay);
486 }
487 }
488
489 if (requireds.empty())
490 continue;
491
492 SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
493 auto it = requireds.begin();
494 for (int i = 0; i < GetSize(conn.second); ++i) {
495 #ifndef NDEBUG
496 if (ys_debug(1)) {
497 static std::set<std::pair<IdString,IdString>> seen;
498 if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), requireds[i]);
499 }
500 #endif
501 auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
502 box->setPort(ID(I), conn.second[i]);
503 box->setPort(ID(O), O[i]);
504 box->setParam(ID(DELAY), *it);
505 if (requireds.size() > 1)
506 it++;
507 conn.second[i] = O[i];
508 }
509 }
510 }
511 }
512
513 int abc9_box_id = design->scratchpad_get_int("abc9_ops.box_id");
514 std::stringstream ss;
515 for (auto flop_module : flops) {
516 int num_inputs = 0, num_outputs = 0;
517 for (auto port_name : flop_module->ports) {
518 auto wire = flop_module->wire(port_name);
519 log_assert(GetSize(wire) == 1);
520 if (wire->port_input) num_inputs++;
521 if (wire->port_output) num_outputs++;
522 }
523 log_assert(num_outputs == 1);
524
525 auto r = flop_module->attributes.insert(ID(abc9_box_id));
526 if (r.second)
527 r.first->second = ++abc9_box_id;
528
529 ss << log_id(flop_module) << " " << r.first->second.as_int();
530 ss << " " << (flop_module->get_bool_attribute(ID::whitebox) ? "1" : "0");
531 ss << " " << num_inputs+1 << " " << num_outputs << std::endl;
532
533 ss << "#";
534 bool first = true;
535 for (auto port_name : flop_module->ports) {
536 auto wire = flop_module->wire(port_name);
537 if (!wire->port_input)
538 continue;
539 if (first)
540 first = false;
541 else
542 ss << " ";
543 ss << log_id(wire);
544 }
545 ss << " abc9_ff.Q" << std::endl;
546
547 first = true;
548 for (auto port_name : flop_module->ports) {
549 auto wire = flop_module->wire(port_name);
550 if (!wire->port_input)
551 continue;
552 if (first)
553 first = false;
554 else
555 ss << " ";
556 ss << wire->attributes.at("\\abc9_required", 0).as_int();
557 }
558 // Last input is 'abc9_ff.Q'
559 ss << " 0" << std::endl << std::endl;
560 }
561 design->scratchpad_set_string("abc9_ops.box_library.flops", ss.str());
562 design->scratchpad_set_int("abc9_ops.box_id", abc9_box_id);
563 }
564
565 void prep_lut(RTLIL::Design *design, int maxlut)
566 {
567 std::stringstream ss;
568 std::vector<std::pair<int, std::string>> table;
569 for (auto module : design->modules()) {
570 auto it = module->attributes.find(ID(abc9_lut));
571 if (it == module->attributes.end())
572 continue;
573 SigBit o;
574 std::vector<int> specify;
575 for (auto cell : module->cells()) {
576 if (cell->type != ID($specify2))
577 continue;
578 log_assert(cell->getParam(ID(SRC_WIDTH)) == 1);
579 log_assert(cell->getParam(ID(DST_WIDTH)) == 1);
580 SigBit s = cell->getPort(ID(SRC));
581 SigBit d = cell->getPort(ID(DST));
582 log_assert(s.wire->port_input);
583 log_assert(d.wire->port_output);
584 if (o == SigBit())
585 o = d;
586 else
587 log_assert(o == d);
588 int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
589 int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
590 specify.push_back(std::max(rise_max,fall_max));
591 }
592 if (maxlut && GetSize(specify) > maxlut)
593 continue;
594 std::sort(specify.begin(), specify.end());
595 ss.str("");
596 ss << "# " << module->name.str() << std::endl;
597 ss << GetSize(specify) << " " << it->second.as_int();
598 for (auto i : specify)
599 ss << " " << i;
600 ss << std::endl;
601 table.emplace_back(GetSize(specify), ss.str());
602 }
603 // ABC expects ascending size
604 std::sort(table.begin(), table.end());
605 ss.str("");
606 for (auto &i : table)
607 ss << i.second;
608 design->scratchpad_set_string("abc9_ops.lut_library", ss.str());
609 }
610
611 void write_lut(RTLIL::Module *module, const std::string &dst) {
612 std::ofstream ofs(dst);
613 log_assert(ofs.is_open());
614 ofs << module->design->scratchpad_get_string("abc9_ops.lut_library");
615 ofs.close();
616 }
617
618 void prep_box(RTLIL::Design *design)
619 {
620 std::stringstream ss;
621 ss << design->scratchpad_get_string("abc9_ops.box_library.flops", ss.str());
622
623 int abc9_box_id = design->scratchpad_get_int("abc9_ops.box_id");
624 for (auto module : design->modules()) {
625 auto it = module->attributes.find(ID(abc9_box));
626 if (it == module->attributes.end())
627 continue;
628 module->attributes.erase(it);
629 log_assert(!module->attributes.count(ID(abc9_box_id)));
630
631 dict<std::pair<SigBit,SigBit>, std::string> table;
632 std::vector<SigBit> inputs;
633 std::vector<SigBit> outputs;
634 for (auto port_name : module->ports) {
635 auto wire = module->wire(port_name);
636 if (wire->port_input)
637 for (int i = 0; i < GetSize(wire); i++)
638 inputs.emplace_back(wire, i);
639 if (wire->port_output)
640 for (int i = 0; i < GetSize(wire); i++)
641 outputs.emplace_back(wire, i);
642 }
643 for (auto cell : module->cells()) {
644 if (cell->type != ID($specify2))
645 continue;
646 auto src = cell->getPort(ID(SRC));
647 auto dst = cell->getPort(ID(DST));
648 for (const auto &c : src.chunks())
649 if (!c.wire->port_input)
650 log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
651 for (const auto &c : dst.chunks())
652 if (!c.wire->port_output)
653 log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
654 int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
655 int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
656 int max = std::max(rise_max,fall_max);
657 for (auto s : src)
658 for (auto d : dst) {
659 auto r = table.insert(std::make_pair(s,d));
660 log_assert(r.second);
661 r.first->second = std::to_string(max);
662 }
663 }
664 auto r = module->attributes.insert(ID(abc9_box_id));
665 log_assert(r.second);
666 r.first->second = ++abc9_box_id;
667 ss << log_id(module) << " " << abc9_box_id;
668 ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
669 ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl;
670 bool first = true;
671 ss << "#";
672 for (const auto &i : inputs) {
673 if (first)
674 first = false;
675 else
676 ss << " ";
677 if (GetSize(i.wire) == 1)
678 ss << log_id(i.wire);
679 else
680 ss << log_id(i.wire) << "[" << i.offset << "]";
681 }
682 ss << std::endl;
683 for (const auto &o : outputs) {
684 first = true;
685 for (const auto &i : inputs) {
686 if (first)
687 first = false;
688 else
689 ss << " ";
690 ss << table.at(std::make_pair(i,o), "-");
691 }
692 ss << " # ";
693 if (GetSize(o.wire) == 1)
694 ss << log_id(o.wire);
695 else
696 ss << log_id(o.wire) << "[" << o.offset << "]";
697 ss << std::endl;
698
699 }
700 ss << std::endl;
701 }
702
703 design->scratchpad_set_string("abc9_ops.box_library", ss.str());
704 design->scratchpad_set_int("abc9_ops.box_id", abc9_box_id);
705 }
706
707 void write_box(RTLIL::Module *module, const std::string &dst) {
708 std::ofstream ofs(dst);
709 log_assert(ofs.is_open());
710 ofs << module->design->scratchpad_get_string("abc9_ops.box_library");
711 // ABC expects at least one box
712 if (ofs.tellp() == 0)
713 ofs << "(dummy) 1 0 0 0";
714 ofs.close();
715 }
716
717 void reintegrate(RTLIL::Module *module)
718 {
719 auto design = module->design;
720 log_assert(design);
721
722 map_autoidx = autoidx++;
723
724 RTLIL::Module *mapped_mod = design->module(stringf("%s$abc9", module->name.c_str()));
725 if (mapped_mod == NULL)
726 log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module));
727
728 for (auto w : mapped_mod->wires())
729 module->addWire(remap_name(w->name), GetSize(w));
730
731 dict<IdString,std::vector<IdString>> box_ports;
732
733 for (auto m : design->modules()) {
734 if (!m->attributes.count(ID(abc9_box_id)))
735 continue;
736
737 auto r = box_ports.insert(m->name);
738 if (!r.second)
739 continue;
740
741 // Make carry in the last PI, and carry out the last PO
742 // since ABC requires it this way
743 IdString carry_in, carry_out;
744 for (const auto &port_name : m->ports) {
745 auto w = m->wire(port_name);
746 log_assert(w);
747 if (w->get_bool_attribute("\\abc9_carry")) {
748 log_assert(w->port_input != w->port_output);
749 if (w->port_input)
750 carry_in = port_name;
751 else if (w->port_output)
752 carry_out = port_name;
753 }
754 else
755 r.first->second.push_back(port_name);
756 }
757
758 if (carry_in != IdString()) {
759 r.first->second.push_back(carry_in);
760 r.first->second.push_back(carry_out);
761 }
762 }
763
764 std::vector<Cell*> boxes;
765 for (auto cell : module->cells().to_vector()) {
766 if (cell->has_keep_attr())
767 continue;
768 if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_)))
769 module->remove(cell);
770 else if (cell->attributes.erase("\\abc9_box_seq"))
771 boxes.emplace_back(cell);
772 }
773
774 dict<SigBit, pool<IdString>> bit_drivers, bit_users;
775 TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
776 dict<RTLIL::Cell*,RTLIL::Cell*> not2drivers;
777 dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks;
778
779 std::map<IdString, int> cell_stats;
780 for (auto mapped_cell : mapped_mod->cells())
781 {
782 // TODO: Speed up toposort -- we care about NOT ordering only
783 toposort.node(mapped_cell->name);
784
785 if (mapped_cell->type == ID($_NOT_)) {
786 RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A);
787 RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y);
788 bit_users[a_bit].insert(mapped_cell->name);
789 // Ignore inouts for topo ordering
790 if (y_bit.wire && !(y_bit.wire->port_input && y_bit.wire->port_output))
791 bit_drivers[y_bit].insert(mapped_cell->name);
792
793 if (!a_bit.wire) {
794 mapped_cell->setPort(ID::Y, module->addWire(NEW_ID));
795 RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
796 log_assert(wire);
797 module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
798 }
799 else {
800 RTLIL::Cell* driver_lut = nullptr;
801 // ABC can return NOT gates that drive POs
802 if (!a_bit.wire->port_input) {
803 // If it's not a NOT gate that that comes from a PI directly,
804 // find the driver LUT and clone that to guarantee that we won't
805 // increase the max logic depth
806 // (TODO: Optimise by not cloning unless will increase depth)
807 RTLIL::IdString driver_name;
808 if (GetSize(a_bit.wire) == 1)
809 driver_name = stringf("$lut%s", a_bit.wire->name.c_str());
810 else
811 driver_name = stringf("$lut%s[%d]", a_bit.wire->name.c_str(), a_bit.offset);
812 driver_lut = mapped_mod->cell(driver_name);
813 }
814
815 if (!driver_lut) {
816 // If a driver couldn't be found (could be from PI or box CI)
817 // then implement using a LUT
818 RTLIL::Cell *cell = module->addLut(remap_name(stringf("$lut%s", mapped_cell->name.c_str())),
819 RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
820 RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
821 RTLIL::Const::from_string("01"));
822 bit2sinks[cell->getPort(ID::A)].push_back(cell);
823 cell_stats[ID($lut)]++;
824 }
825 else
826 not2drivers[mapped_cell] = driver_lut;
827 }
828 continue;
829 }
830
831 if (mapped_cell->type.in(ID($lut), ID($__ABC9_FF_))) {
832 RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
833 cell->parameters = mapped_cell->parameters;
834 cell->attributes = mapped_cell->attributes;
835
836 for (auto &mapped_conn : mapped_cell->connections()) {
837 RTLIL::SigSpec newsig;
838 for (auto c : mapped_conn.second.chunks()) {
839 if (c.width == 0)
840 continue;
841 //log_assert(c.width == 1);
842 if (c.wire)
843 c.wire = module->wires_.at(remap_name(c.wire->name));
844 newsig.append(c);
845 }
846 cell->setPort(mapped_conn.first, newsig);
847
848 if (cell->input(mapped_conn.first)) {
849 for (auto i : newsig)
850 bit2sinks[i].push_back(cell);
851 for (auto i : mapped_conn.second)
852 bit_users[i].insert(mapped_cell->name);
853 }
854 if (cell->output(mapped_conn.first))
855 for (auto i : mapped_conn.second)
856 // Ignore inouts for topo ordering
857 if (i.wire && !(i.wire->port_input && i.wire->port_output))
858 bit_drivers[i].insert(mapped_cell->name);
859 }
860 }
861 else {
862 RTLIL::Cell *existing_cell = module->cell(mapped_cell->name);
863 if (!existing_cell)
864 log_error("Cannot find existing box cell with name '%s' in original design.\n", log_id(mapped_cell));
865
866 if (existing_cell->type == ID($__ABC9_DELAY)) {
867 SigBit I = mapped_cell->getPort(ID(i));
868 SigBit O = mapped_cell->getPort(ID(o));
869 if (I.wire)
870 I.wire = module->wires_.at(remap_name(I.wire->name));
871 log_assert(O.wire);
872 O.wire = module->wires_.at(remap_name(O.wire->name));
873 module->connect(O, I);
874 continue;
875 }
876
877 RTLIL::Module* box_module = design->module(existing_cell->type);
878 IdString derived_type = box_module->derive(design, existing_cell->parameters);
879 RTLIL::Module* derived_module = design->module(derived_type);
880 log_assert(derived_module);
881 log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int()));
882 mapped_cell->type = existing_cell->type;
883
884 RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
885 cell->parameters = existing_cell->parameters;
886 cell->attributes = existing_cell->attributes;
887 module->swap_names(cell, existing_cell);
888
889 auto jt = mapped_cell->connections_.find("\\i");
890 log_assert(jt != mapped_cell->connections_.end());
891 SigSpec inputs = std::move(jt->second);
892 mapped_cell->connections_.erase(jt);
893 jt = mapped_cell->connections_.find("\\o");
894 log_assert(jt != mapped_cell->connections_.end());
895 SigSpec outputs = std::move(jt->second);
896 mapped_cell->connections_.erase(jt);
897
898 auto abc9_flop = box_module->attributes.count("\\abc9_flop");
899 if (!abc9_flop) {
900 for (const auto &i : inputs)
901 bit_users[i].insert(mapped_cell->name);
902 for (const auto &i : outputs)
903 // Ignore inouts for topo ordering
904 if (i.wire && !(i.wire->port_input && i.wire->port_output))
905 bit_drivers[i].insert(mapped_cell->name);
906 }
907
908 int input_count = 0, output_count = 0;
909 for (const auto &port_name : box_ports.at(derived_type)) {
910 RTLIL::Wire *w = box_module->wire(port_name);
911 log_assert(w);
912
913 SigSpec sig;
914 if (w->port_input) {
915 sig = inputs.extract(input_count, GetSize(w));
916 input_count += GetSize(w);
917 }
918 if (w->port_output) {
919 sig = outputs.extract(output_count, GetSize(w));
920 output_count += GetSize(w);
921 }
922
923 SigSpec newsig;
924 for (auto c : sig.chunks()) {
925 if (c.width == 0)
926 continue;
927 //log_assert(c.width == 1);
928 if (c.wire)
929 c.wire = module->wires_.at(remap_name(c.wire->name));
930 newsig.append(c);
931 }
932 cell->setPort(port_name, newsig);
933
934 if (w->port_input && !abc9_flop)
935 for (const auto &i : newsig)
936 bit2sinks[i].push_back(cell);
937 }
938 }
939
940 cell_stats[mapped_cell->type]++;
941 }
942
943 for (auto cell : boxes)
944 module->remove(cell);
945
946 // Copy connections (and rename) from mapped_mod to module
947 for (auto conn : mapped_mod->connections()) {
948 if (!conn.first.is_fully_const()) {
949 auto chunks = conn.first.chunks();
950 for (auto &c : chunks)
951 c.wire = module->wires_.at(remap_name(c.wire->name));
952 conn.first = std::move(chunks);
953 }
954 if (!conn.second.is_fully_const()) {
955 auto chunks = conn.second.chunks();
956 for (auto &c : chunks)
957 if (c.wire)
958 c.wire = module->wires_.at(remap_name(c.wire->name));
959 conn.second = std::move(chunks);
960 }
961 module->connect(conn);
962 }
963
964 for (auto &it : cell_stats)
965 log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
966 int in_wires = 0, out_wires = 0;
967
968 // Stitch in mapped_mod's inputs/outputs into module
969 for (auto port : mapped_mod->ports) {
970 RTLIL::Wire *mapped_wire = mapped_mod->wire(port);
971 RTLIL::Wire *wire = module->wire(port);
972 log_assert(wire);
973 if (wire->attributes.erase(ID(abc9_scc_id))) {
974 auto r YS_ATTRIBUTE(unused) = wire->attributes.erase(ID::keep);
975 log_assert(r);
976 }
977 RTLIL::Wire *remap_wire = module->wire(remap_name(port));
978 RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire));
979 log_assert(GetSize(signal) >= GetSize(remap_wire));
980
981 RTLIL::SigSig conn;
982 if (mapped_wire->port_output) {
983 conn.first = signal;
984 conn.second = remap_wire;
985 out_wires++;
986 module->connect(conn);
987 }
988 else if (mapped_wire->port_input) {
989 conn.first = remap_wire;
990 conn.second = signal;
991 in_wires++;
992 module->connect(conn);
993 }
994 }
995
996 // ABC9 will return $_NOT_ gates in its mapping (since they are
997 // treated as being "free"), in particular driving primary
998 // outputs (real primary outputs, or cells treated as blackboxes)
999 // or driving box inputs.
1000 // Instead of just mapping those $_NOT_ gates into 2-input $lut-s
1001 // at an area and delay cost, see if it is possible to push
1002 // this $_NOT_ into the driving LUT, or into all sink LUTs.
1003 // When this is not possible, (i.e. this signal drives two primary
1004 // outputs, only one of which is complemented) and when the driver
1005 // is a LUT, then clone the LUT so that it can be inverted without
1006 // increasing depth/delay.
1007 for (auto &it : bit_users)
1008 if (bit_drivers.count(it.first))
1009 for (auto driver_cell : bit_drivers.at(it.first))
1010 for (auto user_cell : it.second)
1011 toposort.edge(driver_cell, user_cell);
1012 bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
1013 log_assert(no_loops);
1014
1015 for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {
1016 RTLIL::Cell *not_cell = mapped_mod->cell(*ii);
1017 log_assert(not_cell);
1018 if (not_cell->type != ID($_NOT_))
1019 continue;
1020 auto it = not2drivers.find(not_cell);
1021 if (it == not2drivers.end())
1022 continue;
1023 RTLIL::Cell *driver_lut = it->second;
1024 RTLIL::SigBit a_bit = not_cell->getPort(ID::A);
1025 RTLIL::SigBit y_bit = not_cell->getPort(ID::Y);
1026 RTLIL::Const driver_mask;
1027
1028 a_bit.wire = module->wires_.at(remap_name(a_bit.wire->name));
1029 y_bit.wire = module->wires_.at(remap_name(y_bit.wire->name));
1030
1031 auto jt = bit2sinks.find(a_bit);
1032 if (jt == bit2sinks.end())
1033 goto clone_lut;
1034
1035 for (auto sink_cell : jt->second)
1036 if (sink_cell->type != ID($lut))
1037 goto clone_lut;
1038
1039 // Push downstream LUTs past inverter
1040 for (auto sink_cell : jt->second) {
1041 SigSpec A = sink_cell->getPort(ID::A);
1042 RTLIL::Const mask = sink_cell->getParam(ID(LUT));
1043 int index = 0;
1044 for (; index < GetSize(A); index++)
1045 if (A[index] == a_bit)
1046 break;
1047 log_assert(index < GetSize(A));
1048 int i = 0;
1049 while (i < GetSize(mask)) {
1050 for (int j = 0; j < (1 << index); j++)
1051 std::swap(mask[i+j], mask[i+j+(1 << index)]);
1052 i += 1 << (index+1);
1053 }
1054 A[index] = y_bit;
1055 sink_cell->setPort(ID::A, A);
1056 sink_cell->setParam(ID(LUT), mask);
1057 }
1058
1059 // Since we have rewritten all sinks (which we know
1060 // to be only LUTs) to be after the inverter, we can
1061 // go ahead and clone the LUT with the expectation
1062 // that the original driving LUT will become dangling
1063 // and get cleaned away
1064 clone_lut:
1065 driver_mask = driver_lut->getParam(ID(LUT));
1066 for (auto &b : driver_mask.bits) {
1067 if (b == RTLIL::State::S0) b = RTLIL::State::S1;
1068 else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
1069 }
1070 auto cell = module->addLut(NEW_ID,
1071 driver_lut->getPort(ID::A),
1072 y_bit,
1073 driver_mask);
1074 for (auto &bit : cell->connections_.at(ID::A)) {
1075 bit.wire = module->wires_.at(remap_name(bit.wire->name));
1076 bit2sinks[bit].push_back(cell);
1077 }
1078 }
1079
1080 //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
1081 log("ABC RESULTS: input signals: %8d\n", in_wires);
1082 log("ABC RESULTS: output signals: %8d\n", out_wires);
1083
1084 design->remove(mapped_mod);
1085 }
1086
1087 struct Abc9OpsPass : public Pass {
1088 Abc9OpsPass() : Pass("abc9_ops", "helper functions for ABC9") { }
1089 void help() YS_OVERRIDE
1090 {
1091 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1092 log("\n");
1093 log(" abc9_ops [options] [selection]\n");
1094 log("\n");
1095 log("This pass contains a set of supporting operations for use during ABC technology\n");
1096 log("mapping, and is expected to be called in conjunction with other operations from\n");
1097 log("the `abc9' script pass. Only fully-selected modules are supported.\n");
1098 log("\n");
1099 log(" -check\n");
1100 log(" check that the design is valid, e.g. (* abc9_box_id *) values are unique,\n");
1101 log(" (* abc9_carry *) is only given for one input/output port, etc.\n");
1102 log("\n");
1103 log(" -prep_delays\n");
1104 log(" insert `$__ABC9_DELAY' blackbox cells into the design to account for\n");
1105 log(" certain delays, e.g. (* abc9_required *) values.\n");
1106 log("\n");
1107 log(" -mark_scc\n");
1108 log(" for an arbitrarily chosen cell in each unique SCC of each selected module\n");
1109 log(" (tagged with an (* abc9_scc_id = <int> *) attribute), temporarily mark all\n");
1110 log(" wires driven by this cell's outputs with a (* keep *) attribute in order\n");
1111 log(" to break the SCC. this temporary attribute will be removed on -reintegrate.\n");
1112 log("\n");
1113 log(" -prep_xaiger\n");
1114 log(" prepare the design for XAIGER output. this includes computing the\n");
1115 log(" topological ordering of ABC9 boxes, as well as preparing the\n");
1116 log(" '<module-name>$holes' module that contains the logic behaviour of ABC9\n");
1117 log(" whiteboxes.\n");
1118 log("\n");
1119 log(" -dff\n");
1120 log(" consider flop cells (those instantiating modules marked with (* abc9_flop *)\n");
1121 log(" during -prep_xaiger.\n");
1122 log("\n");
1123 log(" -prep_dff\n");
1124 log(" compute the clock domain and initial value of each flop in the design.\n");
1125 log(" process the '$holes' module to support clock-enable functionality.\n");
1126 log("\n");
1127 log(" -prep_lut <maxlut>\n");
1128 log(" pre-compute the lut library by analysing all modules marked with\n");
1129 log(" (* abc9_lut=<area> *).\n");
1130 log("\n");
1131 log(" -write_lut <dst>\n");
1132 log(" write the pre-computed lut library to <dst>.\n");
1133 log("\n");
1134 log(" -prep_box\n");
1135 log(" pre-compute the box library by analysing all modules marked with\n");
1136 log(" (* abc9_box *)\n");
1137 log("\n");
1138 log(" -write_box <dst>\n");
1139 log(" write the pre-computed box library to <dst>.\n");
1140 log("\n");
1141 log(" -reintegrate\n");
1142 log(" for each selected module, re-intergrate the module '<module-name>$abc9'\n");
1143 log(" by first recovering ABC9 boxes, and then stitching in the remaining primary\n");
1144 log(" inputs and outputs.\n");
1145 log("\n");
1146 }
1147 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1148 {
1149 log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n");
1150
1151 bool check_mode = false;
1152 bool prep_delays_mode = false;
1153 bool mark_scc_mode = false;
1154 bool prep_dff_mode = false;
1155 bool prep_xaiger_mode = false;
1156 bool prep_lut_mode = false;
1157 bool prep_box_mode = false;
1158 bool reintegrate_mode = false;
1159 bool dff_mode = false;
1160 std::string write_lut_dst;
1161 int maxlut = 0;
1162 std::string write_box_dst;
1163
1164 size_t argidx;
1165 for (argidx = 1; argidx < args.size(); argidx++) {
1166 std::string arg = args[argidx];
1167 if (arg == "-check") {
1168 check_mode = true;
1169 continue;
1170 }
1171 if (arg == "-mark_scc") {
1172 mark_scc_mode = true;
1173 continue;
1174 }
1175 if (arg == "-prep_dff") {
1176 prep_dff_mode = true;
1177 continue;
1178 }
1179 if (arg == "-prep_xaiger") {
1180 prep_xaiger_mode = true;
1181 continue;
1182 }
1183 if (arg == "-prep_delays") {
1184 prep_delays_mode = true;
1185 continue;
1186 }
1187 if (arg == "-prep_lut" && argidx+1 < args.size()) {
1188 prep_lut_mode = true;
1189 maxlut = atoi(args[++argidx].c_str());
1190 continue;
1191 }
1192 if (arg == "-maxlut" && argidx+1 < args.size()) {
1193 continue;
1194 }
1195 if (arg == "-write_lut" && argidx+1 < args.size()) {
1196 write_lut_dst = args[++argidx];
1197 rewrite_filename(write_lut_dst);
1198 continue;
1199 }
1200 if (arg == "-prep_box") {
1201 prep_box_mode = true;
1202 continue;
1203 }
1204 if (arg == "-write_box" && argidx+1 < args.size()) {
1205 write_box_dst = args[++argidx];
1206 rewrite_filename(write_box_dst);
1207 continue;
1208 }
1209 if (arg == "-reintegrate") {
1210 reintegrate_mode = true;
1211 continue;
1212 }
1213 if (arg == "-dff") {
1214 dff_mode = true;
1215 continue;
1216 }
1217 break;
1218 }
1219 extra_args(args, argidx, design);
1220
1221 if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || prep_lut_mode || prep_box_mode || !write_lut_dst.empty() || !write_box_dst.empty() || reintegrate_mode))
1222 log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff,lut,box}, -write_{lut,box}, -reintegrate must be specified.\n");
1223
1224 if (dff_mode && !prep_xaiger_mode)
1225 log_cmd_error("'-dff' option is only relevant for -prep_xaiger.\n");
1226
1227 if (check_mode)
1228 check(design);
1229 if (prep_delays_mode)
1230 prep_delays(design);
1231 if (prep_lut_mode)
1232 prep_lut(design, maxlut);
1233 if (prep_box_mode)
1234 prep_box(design);
1235
1236 for (auto mod : design->selected_modules()) {
1237 if (mod->get_bool_attribute("\\abc9_holes"))
1238 continue;
1239
1240 if (mod->processes.size() > 0) {
1241 log("Skipping module %s as it contains processes.\n", log_id(mod));
1242 continue;
1243 }
1244
1245 if (!design->selected_whole_module(mod))
1246 log_error("Can't handle partially selected module %s!\n", log_id(mod));
1247
1248 if (!write_lut_dst.empty())
1249 write_lut(mod, write_lut_dst);
1250 if (!write_box_dst.empty())
1251 write_box(mod, write_box_dst);
1252 if (mark_scc_mode)
1253 mark_scc(mod);
1254 if (prep_dff_mode)
1255 prep_dff(mod);
1256 if (prep_xaiger_mode)
1257 prep_xaiger(mod, dff_mode);
1258 if (reintegrate_mode)
1259 reintegrate(mod);
1260 }
1261 }
1262 } Abc9OpsPass;
1263
1264 PRIVATE_NAMESPACE_END