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Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
[yosys.git] / passes / techmap / abc9_ops.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/utils.h"
24 #include "kernel/celltypes.h"
25
26 USING_YOSYS_NAMESPACE
27 PRIVATE_NAMESPACE_BEGIN
28
29 void break_scc(RTLIL::Module *module)
30 {
31 // For every unique SCC found, (arbitrarily) find the first
32 // cell in the component, and convert all wires driven by
33 // its output ports into a new PO, and drive its previous
34 // sinks with a new PI
35 pool<RTLIL::Const> ids_seen;
36 for (auto cell : module->selected_cells()) {
37 auto it = cell->attributes.find(ID(abc9_scc_id));
38 if (it == cell->attributes.end())
39 continue;
40 auto r = ids_seen.insert(it->second);
41 cell->attributes.erase(it);
42 if (!r.second)
43 continue;
44 for (auto &c : cell->connections_) {
45 if (c.second.is_fully_const()) continue;
46 if (cell->output(c.first)) {
47 SigBit b = c.second.as_bit();
48 Wire *w = b.wire;
49 if (w->port_input) {
50 // In this case, hopefully the loop break has been already created
51 // Get the non-prefixed wire
52 Wire *wo = module->wire(stringf("%s.abco", b.wire->name.c_str()));
53 log_assert(wo != nullptr);
54 log_assert(wo->port_output);
55 log_assert(b.offset < GetSize(wo));
56 c.second = RTLIL::SigBit(wo, b.offset);
57 }
58 else {
59 // Create a new output/input loop break
60 w->port_input = true;
61 w = module->wire(stringf("%s.abco", w->name.c_str()));
62 if (!w) {
63 w = module->addWire(stringf("%s.abco", b.wire->name.c_str()), GetSize(b.wire));
64 w->port_output = true;
65 }
66 else {
67 log_assert(w->port_input);
68 log_assert(b.offset < GetSize(w));
69 }
70 w->set_bool_attribute(ID(abc9_scc_break));
71 c.second = RTLIL::SigBit(w, b.offset);
72 }
73 }
74 }
75 }
76
77 module->fixup_ports();
78 }
79
80 void unbreak_scc(RTLIL::Module *module)
81 {
82 // Now 'unexpose' those wires by undoing
83 // the expose operation -- remove them from PO/PI
84 // and re-connecting them back together
85 for (auto wire : module->wires()) {
86 auto it = wire->attributes.find(ID(abc9_scc_break));
87 if (it != wire->attributes.end()) {
88 wire->attributes.erase(it);
89 log_assert(wire->port_output);
90 wire->port_output = false;
91 std::string name = wire->name.str();
92 RTLIL::Wire *i_wire = module->wire(name.substr(0, GetSize(name) - 5));
93 log_assert(i_wire);
94 log_assert(i_wire->port_input);
95 i_wire->port_input = false;
96 module->connect(i_wire, wire);
97 }
98 }
99 module->fixup_ports();
100 }
101
102 void prep_dff(RTLIL::Module *module)
103 {
104 auto design = module->design;
105 log_assert(design);
106
107 SigMap assign_map(module);
108
109 typedef SigSpec clkdomain_t;
110 dict<clkdomain_t, int> clk_to_mergeability;
111
112 for (auto cell : module->selected_cells()) {
113 if (cell->type != "$__ABC9_FF_")
114 continue;
115
116 Wire *abc9_clock_wire = module->wire(stringf("%s.clock", cell->name.c_str()));
117 if (abc9_clock_wire == NULL)
118 log_error("'%s.clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
119 SigSpec abc9_clock = assign_map(abc9_clock_wire);
120
121 clkdomain_t key(abc9_clock);
122
123 auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
124 auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
125 log_assert(r2.second);
126
127 Wire *abc9_init_wire = module->wire(stringf("%s.init", cell->name.c_str()));
128 if (abc9_init_wire == NULL)
129 log_error("'%s.init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
130 log_assert(GetSize(abc9_init_wire) == 1);
131 SigSpec abc9_init = assign_map(abc9_init_wire);
132 if (!abc9_init.is_fully_const())
133 log_error("'%s.init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
134 r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
135 log_assert(r2.second);
136 }
137
138 RTLIL::Module *holes_module = design->module(stringf("%s$holes", module->name.c_str()));
139 if (holes_module) {
140 dict<SigSig, SigSig> replace;
141 for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
142 auto cell = it->second;
143 if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
144 "$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
145 SigBit D = cell->getPort("\\D");
146 SigBit Q = cell->getPort("\\Q");
147 // Remove the DFF cell from what needs to be a combinatorial box
148 it = holes_module->cells_.erase(it);
149 Wire *port;
150 if (GetSize(Q.wire) == 1)
151 port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
152 else
153 port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
154 log_assert(port);
155 // Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;"
156 // in order to extract the combinatorial control logic that feeds the box
157 // (i.e. clock enable, synchronous reset, etc.)
158 replace.insert(std::make_pair(SigSig(port,Q), SigSig(port,D)));
159 // Since `flatten` above would have created wires named "<cell>.Q",
160 // extract the pre-techmap cell name
161 auto pos = Q.wire->name.str().rfind(".");
162 log_assert(pos != std::string::npos);
163 IdString driver = Q.wire->name.substr(0, pos);
164 // And drive the signal that was previously driven by "DFF.Q" (typically
165 // used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
166 // wire (which itself is driven an input port) we inserted above
167 Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
168 log_assert(currQ);
169 holes_module->connect(Q, currQ);
170 }
171 else
172 ++it;
173 }
174
175 for (auto &conn : holes_module->connections_) {
176 auto it = replace.find(conn);
177 if (it != replace.end())
178 conn = it->second;
179 }
180 }
181 }
182
183 void prep_holes(RTLIL::Module *module, bool dff)
184 {
185 auto design = module->design;
186 log_assert(design);
187
188 SigMap sigmap(module);
189
190 dict<SigBit, pool<IdString>> bit_drivers, bit_users;
191 TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
192 bool abc9_box_seen = false;
193
194 for (auto cell : module->selected_cells()) {
195 if (cell->type == "$__ABC9_FF_")
196 continue;
197
198 auto inst_module = module->design->module(cell->type);
199 bool abc9_box = inst_module && inst_module->attributes.count("\\abc9_box_id");
200 bool abc9_flop = false;
201 if (abc9_box) {
202 abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
203 if (abc9_flop && !dff)
204 continue;
205 abc9_box_seen = abc9_box;
206 }
207 else if (!yosys_celltypes.cell_known(cell->type))
208 continue;
209
210 for (auto conn : cell->connections()) {
211 if (cell->input(conn.first))
212 for (auto bit : sigmap(conn.second))
213 bit_users[bit].insert(cell->name);
214
215 if (cell->output(conn.first) && !abc9_flop)
216 for (auto bit : sigmap(conn.second))
217 bit_drivers[bit].insert(cell->name);
218 }
219
220 toposort.node(cell->name);
221 }
222
223 if (!abc9_box_seen)
224 return;
225
226 for (auto &it : bit_users)
227 if (bit_drivers.count(it.first))
228 for (auto driver_cell : bit_drivers.at(it.first))
229 for (auto user_cell : it.second)
230 toposort.edge(driver_cell, user_cell);
231
232 #if 0
233 toposort.analyze_loops = true;
234 #endif
235 bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
236 #if 0
237 unsigned i = 0;
238 for (auto &it : toposort.loops) {
239 log(" loop %d\n", i++);
240 for (auto cell_name : it) {
241 auto cell = module->cell(cell_name);
242 log_assert(cell);
243 log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
244 }
245 }
246 #endif
247 log_assert(no_loops);
248
249 vector<Cell*> box_list;
250 for (auto cell_name : toposort.sorted) {
251 RTLIL::Cell *cell = module->cell(cell_name);
252 log_assert(cell);
253
254 RTLIL::Module* box_module = design->module(cell->type);
255 if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
256 continue;
257 cell->attributes["\\abc9_box_seq"] = box_list.size();
258 box_list.emplace_back(cell);
259 }
260 log_assert(!box_list.empty());
261
262 RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
263 log_assert(holes_module);
264 holes_module->set_bool_attribute("\\abc9_holes");
265
266 dict<IdString, Cell*> cell_cache;
267 dict<IdString, std::vector<IdString>> box_ports;
268
269 int port_id = 1;
270 for (auto cell : box_list) {
271 RTLIL::Module* orig_box_module = design->module(cell->type);
272 log_assert(orig_box_module);
273 IdString derived_name = orig_box_module->derive(design, cell->parameters);
274 RTLIL::Module* box_module = design->module(derived_name);
275 if (box_module->has_processes())
276 Pass::call_on_module(design, box_module, "proc");
277
278 int box_inputs = 0;
279 auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
280 Cell *holes_cell = r.first->second;
281 if (r.second && box_module->get_bool_attribute("\\whitebox")) {
282 holes_cell = holes_module->addCell(cell->name, cell->type);
283 holes_cell->parameters = cell->parameters;
284 r.first->second = holes_cell;
285 }
286
287 auto r2 = box_ports.insert(cell->type);
288 if (r2.second) {
289 // Make carry in the last PI, and carry out the last PO
290 // since ABC requires it this way
291 IdString carry_in, carry_out;
292 for (const auto &port_name : box_module->ports) {
293 auto w = box_module->wire(port_name);
294 log_assert(w);
295 if (w->get_bool_attribute("\\abc9_carry")) {
296 if (w->port_input) {
297 if (carry_in != IdString())
298 log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
299 carry_in = port_name;
300 }
301 if (w->port_output) {
302 if (carry_out != IdString())
303 log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
304 carry_out = port_name;
305 }
306 }
307 else
308 r2.first->second.push_back(port_name);
309 }
310
311 if (carry_in != IdString() && carry_out == IdString())
312 log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
313 if (carry_in == IdString() && carry_out != IdString())
314 log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
315 if (carry_in != IdString()) {
316 r2.first->second.push_back(carry_in);
317 r2.first->second.push_back(carry_out);
318 }
319 }
320
321 for (const auto &port_name : box_ports.at(cell->type)) {
322 RTLIL::Wire *w = box_module->wire(port_name);
323 log_assert(w);
324 RTLIL::Wire *holes_wire;
325 RTLIL::SigSpec port_sig;
326 if (w->port_input)
327 for (int i = 0; i < GetSize(w); i++) {
328 box_inputs++;
329 holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
330 if (!holes_wire) {
331 holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
332 holes_wire->port_input = true;
333 holes_wire->port_id = port_id++;
334 holes_module->ports.push_back(holes_wire->name);
335 }
336 if (holes_cell)
337 port_sig.append(holes_wire);
338 }
339 if (w->port_output)
340 for (int i = 0; i < GetSize(w); i++) {
341 if (GetSize(w) == 1)
342 holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(w->name)));
343 else
344 holes_wire = holes_module->addWire(stringf("$abc%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
345 holes_wire->port_output = true;
346 holes_wire->port_id = port_id++;
347 holes_module->ports.push_back(holes_wire->name);
348 if (holes_cell)
349 port_sig.append(holes_wire);
350 else
351 holes_module->connect(holes_wire, State::S0);
352 }
353 if (!port_sig.empty()) {
354 if (r.second)
355 holes_cell->setPort(w->name, port_sig);
356 else
357 holes_module->connect(holes_cell->getPort(w->name), port_sig);
358 }
359 }
360
361 // For flops only, create an extra 1-bit input that drives a new wire
362 // called "<cell>.$abc9_currQ" that is used below
363 if (box_module->get_bool_attribute("\\abc9_flop")) {
364 log_assert(holes_cell);
365
366 box_inputs++;
367 Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
368 if (!holes_wire) {
369 holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
370 holes_wire->port_input = true;
371 holes_wire->port_id = port_id++;
372 holes_module->ports.push_back(holes_wire->name);
373 }
374 Wire *w = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
375 holes_module->connect(w, holes_wire);
376 }
377 }
378 }
379
380 struct Abc9OpsPass : public Pass {
381 Abc9OpsPass() : Pass("abc9_ops", "helper functions for ABC9") { }
382 void help() YS_OVERRIDE
383 {
384 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
385 log("\n");
386 log(" abc9_ops [options] [selection]\n");
387 log("\n");
388 }
389 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
390 {
391 log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n");
392
393 bool break_scc_mode = false;
394 bool unbreak_scc_mode = false;
395 bool prep_dff_mode = false;
396 bool prep_holes_mode = false;
397 bool dff_mode = false;
398
399 size_t argidx;
400 for (argidx = 1; argidx < args.size(); argidx++) {
401 std::string arg = args[argidx];
402 if (arg == "-break_scc") {
403 break_scc_mode = true;
404 continue;
405 }
406 if (arg == "-unbreak_scc") {
407 unbreak_scc_mode = true;
408 continue;
409 }
410 if (arg == "-prep_dff") {
411 prep_dff_mode = true;
412 continue;
413 }
414 if (arg == "-prep_holes") {
415 prep_holes_mode = true;
416 continue;
417 }
418 if (arg == "-dff") {
419 dff_mode = true;
420 continue;
421 }
422 break;
423 }
424 extra_args(args, argidx, design);
425
426 for (auto mod : design->selected_modules()) {
427 if (mod->get_blackbox_attribute())
428 continue;
429 if (mod->get_bool_attribute("\\abc9_holes"))
430 continue;
431
432 if (mod->processes.size() > 0) {
433 log("Skipping module %s as it contains processes.\n", log_id(mod));
434 continue;
435 }
436
437 if (break_scc_mode)
438 break_scc(mod);
439 if (unbreak_scc_mode)
440 unbreak_scc(mod);
441 if (prep_dff_mode)
442 prep_dff(mod);
443 if (prep_holes_mode)
444 prep_holes(mod, dff_mode);
445 }
446 }
447 } Abc9OpsPass;
448
449 PRIVATE_NAMESPACE_END