passes/techmap/attrmvcp.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21 #include "kernel/sigtools.h"
  22
  23 USING_YOSYS_NAMESPACE
  24 PRIVATE_NAMESPACE_BEGIN
  25
  26 struct AttrmvcpPass : public Pass {
  27         AttrmvcpPass() : Pass("attrmvcp", "move or copy attributes from wires to driving cells") { }
  28         void help() YS_OVERRIDE
  29         {
  30                 log("\n");
  31                 log("    attrmvcp [options] [selection]\n");
  32                 log("\n");
  33                 log("Move or copy attributes on wires to the cells driving them.\n");
  34                 log("\n");
  35                 log("    -copy\n");
  36                 log("        By default, attributes are moved. This will only add\n");
  37                 log("        the attribute to the cell, without removing it from\n");
  38                 log("        the wire.\n");
  39                 log("\n");
  40                 log("    -purge\n");
  41                 log("        If no selected cell consumes the attribute, then it is\n");
  42                 log("        left on the wire by default. This option will cause the\n");
  43                 log("        attribute to be removed from the wire, even if no selected\n");
  44                 log("        cell takes it.\n");
  45                 log("\n");
  46                 log("    -driven\n");
  47                 log("        By default, attriburtes are moved to the cell driving the\n");
  48                 log("        wire. With this option set it will be moved to the cell\n");
  49                 log("        driven by the wire instead.\n");
  50                 log("\n");
  51                 log("    -attr <attrname>\n");
  52                 log("        Move or copy this attribute. This option can be used\n");
  53                 log("        multiple times.\n");
  54                 log("\n");
  55         }
  56         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  57         {
  58                 log_header(design, "Executing ATTRMVCP pass (move or copy attributes).\n");
  59
  60                 bool copy_mode = false;
  61                 bool driven_mode = false;
  62                 bool purge_mode = false;
  63                 pool<IdString> attrnames;
  64
  65                 size_t argidx;
  66                 for (argidx = 1; argidx < args.size(); argidx++)
  67                 {
  68                         std::string arg = args[argidx];
  69                         if (arg == "-copy") {
  70                                 copy_mode = true;
  71                                 continue;
  72                         }
  73                         if (arg == "-driven") {
  74                                 driven_mode = true;
  75                                 continue;
  76                         }
  77                         if (arg == "-purge") {
  78                                 purge_mode = true;
  79                                 continue;
  80                         }
  81                         if (arg == "-attr" && argidx+1 < args.size()) {
  82                                 attrnames.insert(RTLIL::escape_id(args[++argidx]));
  83                                 continue;
  84                         }
  85                         break;
  86                 }
  87                 extra_args(args, argidx, design);
  88
  89                 for (auto module : design->selected_modules())
  90                 {
  91                         dict<SigBit, pool<Cell*>> net2cells;
  92                         SigMap sigmap(module);
  93
  94                         for (auto cell : module->selected_cells())
  95                         for (auto &conn : cell->connections())
  96                         {
  97                                 if (driven_mode) {
  98                                         if (cell->input(conn.first))
  99                                                 for (auto bit : sigmap(conn.second))
 100                                                         net2cells[bit].insert(cell);
 101                                 } else {
 102                                         if (cell->output(conn.first))
 103                                                 for (auto bit : sigmap(conn.second))
 104                                                         net2cells[bit].insert(cell);
 105                                 }
 106                         }
 107
 108                         for (auto wire : module->selected_wires())
 109                         {
 110                                 dict<IdString, Const> new_attributes;
 111
 112                                 for (auto attr : wire->attributes)
 113                                 {
 114                                         bool did_something = false;
 115
 116                                         if (!attrnames.count(attr.first)) {
 117                                                 new_attributes[attr.first] = attr.second;
 118                                                 continue;
 119                                         }
 120
 121                                         for (auto bit : sigmap(wire))
 122                                                 if (net2cells.count(bit))
 123                                                         for (auto cell : net2cells.at(bit)) {
 124                                                                 log("Moving attribute %s=%s from %s.%s to %s.%s.\n", log_id(attr.first), log_const(attr.second),
 125                                                                                 log_id(module), log_id(wire), log_id(module), log_id(cell));
 126                                                                 cell->attributes[attr.first] = attr.second;
 127                                                                 did_something = true;
 128                                                         }
 129
 130                                         if (!purge_mode && !did_something)
 131                                                 new_attributes[attr.first] = attr.second;
 132                                 }
 133
 134                                 if (!copy_mode)
 135                                         wire->attributes.swap(new_attributes);
 136                         }
 137                 }
 138         }
 139 } AttrmvcpPass;
 140
 141 PRIVATE_NAMESPACE_END