passes/techmap/dff2dffs.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *  Copyright (C) 2018  David Shah <dave@ds0.me>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 #include "kernel/yosys.h"
  22 #include "kernel/sigtools.h"
  23
  24 USING_YOSYS_NAMESPACE
  25 PRIVATE_NAMESPACE_BEGIN
  26
  27 struct Dff2dffsPass : public Pass {
  28         Dff2dffsPass() : Pass("dff2dffs", "process sync set/reset with SR over CE priority") { }
  29         void help() YS_OVERRIDE
  30         {
  31                 log("\n");
  32                 log("    dff2dffs [options] [selection]\n");
  33                 log("\n");
  34                 log("Merge synchronous set/reset $_MUX_ cells to create $__DFFS_[NP][NP][01], to be run before\n");
  35                 log("dff2dffe for SR over CE priority.\n");
  36                 log("\n");
  37         }
  38         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  39         {
  40                 log_header(design, "Executing dff2dffs pass (merge synchronous set/reset into FF cells).\n");
  41
  42                 size_t argidx;
  43                 for (argidx = 1; argidx < args.size(); argidx++)
  44                 {
  45                         // if (args[argidx] == "-singleton") {
  46                         //      singleton_mode = true;
  47                         //      continue;
  48                         // }
  49                         break;
  50                 }
  51                 extra_args(args, argidx, design);
  52
  53                 pool<IdString> dff_types;
  54                 dff_types.insert("$_DFF_N_");
  55                 dff_types.insert("$_DFF_P_");
  56
  57                 for (auto module : design->selected_modules())
  58                 {
  59                         log("Merging set/reset $_MUX_ cells into DFFs in %s.\n", log_id(module));
  60
  61                         SigMap sigmap(module);
  62                         dict<SigBit, Cell*> sr_muxes;
  63                         vector<Cell*> ff_cells;
  64
  65                         for (auto cell : module->selected_cells())
  66                         {
  67                                 if (dff_types.count(cell->type)) {
  68                                         ff_cells.push_back(cell);
  69                                         continue;
  70                                 }
  71
  72                                 if (cell->type != "$_MUX_")
  73                                         continue;
  74
  75                                 SigBit bit_a = sigmap(cell->getPort("\\A"));
  76                                 SigBit bit_b = sigmap(cell->getPort("\\B"));
  77
  78                                 if (bit_a.wire == nullptr || bit_b.wire == nullptr)
  79                                         sr_muxes[sigmap(cell->getPort("\\Y"))] = cell;
  80                         }
  81
  82                         for (auto cell : ff_cells)
  83                         {
  84                                 SigSpec sig_d = cell->getPort("\\D");
  85
  86                                 if (GetSize(sig_d) < 1)
  87                                         continue;
  88
  89                                 SigBit bit_d = sigmap(sig_d[0]);
  90
  91                                 if (sr_muxes.count(bit_d) == 0)
  92                                         continue;
  93
  94                                 Cell *mux_cell = sr_muxes.at(bit_d);
  95                                 SigBit bit_a = sigmap(mux_cell->getPort("\\A"));
  96                                 SigBit bit_b = sigmap(mux_cell->getPort("\\B"));
  97                                 SigBit bit_s = sigmap(mux_cell->getPort("\\S"));
  98
  99                                 log("  Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
 100                                                 log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
 101
 102                                 SigBit sr_val, sr_sig;
 103                                 bool invert_sr;
 104                                 sr_sig = bit_s;
 105                                 if (bit_a.wire == nullptr) {
 106                                         bit_d = bit_b;
 107                                         sr_val = bit_a;
 108                                         invert_sr = true;
 109                                 } else {
 110                                         log_assert(bit_b.wire == nullptr);
 111                                         bit_d = bit_a;
 112                                         sr_val = bit_b;
 113                                         invert_sr = false;
 114                                 }
 115
 116                                 if (sr_val == State::S1) {
 117                                         if (cell->type == "$_DFF_N_") {
 118                                                 if (invert_sr) cell->type = "$__DFFS_NN1_";
 119                                                 else cell->type = "$__DFFS_NP1_";
 120                                         } else {
 121                                                 log_assert(cell->type == "$_DFF_P_");
 122                                                 if (invert_sr) cell->type = "$__DFFS_PN1_";
 123                                                 else cell->type = "$__DFFS_PP1_";
 124                                         }
 125                                 } else {
 126                                         if (cell->type == "$_DFF_N_") {
 127                                                 if (invert_sr) cell->type = "$__DFFS_NN0_";
 128                                                 else cell->type = "$__DFFS_NP0_";
 129                                         } else {
 130                                                 log_assert(cell->type == "$_DFF_P_");
 131                                                 if (invert_sr) cell->type = "$__DFFS_PN0_";
 132                                                 else cell->type = "$__DFFS_PP0_";
 133                                         }
 134                                 }
 135                                 cell->setPort("\\R", sr_sig);
 136                                 cell->setPort("\\D", bit_d);
 137                         }
 138                 }
 139         }
 140 } Dff2dffsPass;
 141
 142 PRIVATE_NAMESPACE_END