2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/sigtools.h"
22 #include "kernel/log.h"
23 #include "libs/subcircuit/subcircuit.h"
30 PRIVATE_NAMESPACE_BEGIN
34 class SubCircuitSolver
: public SubCircuit::Solver
37 bool ignore_parameters
;
38 std::set
<std::pair
<RTLIL::IdString
, RTLIL::IdString
>> ignored_parameters
;
39 std::set
<RTLIL::IdString
> cell_attr
, wire_attr
;
41 SubCircuitSolver() : ignore_parameters(false)
45 bool compareAttributes(const std::set
<RTLIL::IdString
> &attr
, const dict
<RTLIL::IdString
, RTLIL::Const
> &needleAttr
, const dict
<RTLIL::IdString
, RTLIL::Const
> &haystackAttr
)
47 for (auto &it
: attr
) {
48 size_t nc
= needleAttr
.count(it
), hc
= haystackAttr
.count(it
);
49 if (nc
!= hc
|| (nc
> 0 && needleAttr
.at(it
) != haystackAttr
.at(it
)))
55 RTLIL::Const
unified_param(RTLIL::IdString cell_type
, RTLIL::IdString param
, RTLIL::Const value
)
57 if (cell_type
.substr(0, 1) != "$" || cell_type
.substr(0, 2) == "$_")
60 #define param_bool(_n) if (param == _n) return value.as_bool();
61 param_bool("\\ARST_POLARITY");
62 param_bool("\\A_SIGNED");
63 param_bool("\\B_SIGNED");
64 param_bool("\\CLK_ENABLE");
65 param_bool("\\CLK_POLARITY");
66 param_bool("\\CLR_POLARITY");
67 param_bool("\\EN_POLARITY");
68 param_bool("\\SET_POLARITY");
69 param_bool("\\TRANSPARENT");
72 #define param_int(_n) if (param == _n) return value.as_int();
74 param_int("\\A_WIDTH")
75 param_int("\\B_WIDTH")
76 param_int("\\CTRL_IN_WIDTH")
77 param_int("\\CTRL_OUT_WIDTH")
79 param_int("\\PRIORITY")
80 param_int("\\RD_PORTS")
82 param_int("\\STATE_BITS")
83 param_int("\\STATE_NUM")
84 param_int("\\STATE_NUM_LOG2")
85 param_int("\\STATE_RST")
86 param_int("\\S_WIDTH")
87 param_int("\\TRANS_NUM")
89 param_int("\\WR_PORTS")
90 param_int("\\Y_WIDTH")
96 virtual bool userCompareNodes(const std::string
&, const std::string
&, void *needleUserData
,
97 const std::string
&, const std::string
&, void *haystackUserData
, const std::map
<std::string
, std::string
> &portMapping
)
99 RTLIL::Cell
*needleCell
= (RTLIL::Cell
*) needleUserData
;
100 RTLIL::Cell
*haystackCell
= (RTLIL::Cell
*) haystackUserData
;
102 if (!needleCell
|| !haystackCell
) {
103 log_assert(!needleCell
&& !haystackCell
);
107 if (!ignore_parameters
) {
108 std::map
<RTLIL::IdString
, RTLIL::Const
> needle_param
, haystack_param
;
109 for (auto &it
: needleCell
->parameters
)
110 if (!ignored_parameters
.count(std::pair
<RTLIL::IdString
, RTLIL::IdString
>(needleCell
->type
, it
.first
)))
111 needle_param
[it
.first
] = unified_param(needleCell
->type
, it
.first
, it
.second
);
112 for (auto &it
: haystackCell
->parameters
)
113 if (!ignored_parameters
.count(std::pair
<RTLIL::IdString
, RTLIL::IdString
>(haystackCell
->type
, it
.first
)))
114 haystack_param
[it
.first
] = unified_param(haystackCell
->type
, it
.first
, it
.second
);
115 if (needle_param
!= haystack_param
)
119 if (cell_attr
.size() > 0 && !compareAttributes(cell_attr
, needleCell
->attributes
, haystackCell
->attributes
))
122 if (wire_attr
.size() > 0)
124 RTLIL::Wire
*lastNeedleWire
= NULL
;
125 RTLIL::Wire
*lastHaystackWire
= NULL
;
126 dict
<RTLIL::IdString
, RTLIL::Const
> emptyAttr
;
128 for (auto &conn
: needleCell
->connections())
130 RTLIL::SigSpec needleSig
= conn
.second
;
131 RTLIL::SigSpec haystackSig
= haystackCell
->getPort(portMapping
.at(conn
.first
.str()));
133 for (int i
= 0; i
< min(needleSig
.size(), haystackSig
.size()); i
++) {
134 RTLIL::Wire
*needleWire
= needleSig
[i
].wire
, *haystackWire
= haystackSig
[i
].wire
;
135 if (needleWire
!= lastNeedleWire
|| haystackWire
!= lastHaystackWire
)
136 if (!compareAttributes(wire_attr
, needleWire
? needleWire
->attributes
: emptyAttr
, haystackWire
? haystackWire
->attributes
: emptyAttr
))
138 lastNeedleWire
= needleWire
, lastHaystackWire
= haystackWire
;
148 std::string cell
, port
;
152 bool module2graph(SubCircuit::Graph
&graph
, RTLIL::Module
*mod
, bool constports
, RTLIL::Design
*sel
= NULL
,
153 int max_fanout
= -1, std::set
<std::pair
<RTLIL::IdString
, RTLIL::IdString
>> *split
= NULL
)
156 std::map
<RTLIL::SigBit
, bit_ref_t
> sig_bit_ref
;
158 if (sel
&& !sel
->selected(mod
)) {
159 log(" Skipping module %s as it is not selected.\n", id2cstr(mod
->name
));
163 if (mod
->processes
.size() > 0) {
164 log(" Skipping module %s as it contains unprocessed processes.\n", id2cstr(mod
->name
));
169 graph
.createNode("$const$0", "$const$0", NULL
, true);
170 graph
.createNode("$const$1", "$const$1", NULL
, true);
171 graph
.createNode("$const$x", "$const$x", NULL
, true);
172 graph
.createNode("$const$z", "$const$z", NULL
, true);
173 graph
.createPort("$const$0", "\\Y", 1);
174 graph
.createPort("$const$1", "\\Y", 1);
175 graph
.createPort("$const$x", "\\Y", 1);
176 graph
.createPort("$const$z", "\\Y", 1);
177 graph
.markExtern("$const$0", "\\Y", 0);
178 graph
.markExtern("$const$1", "\\Y", 0);
179 graph
.markExtern("$const$x", "\\Y", 0);
180 graph
.markExtern("$const$z", "\\Y", 0);
183 std::map
<std::pair
<RTLIL::Wire
*, int>, int> sig_use_count
;
185 for (auto &cell_it
: mod
->cells_
)
187 RTLIL::Cell
*cell
= cell_it
.second
;
188 if (!sel
|| sel
->selected(mod
, cell
))
189 for (auto &conn
: cell
->connections()) {
190 RTLIL::SigSpec conn_sig
= conn
.second
;
191 sigmap
.apply(conn_sig
);
192 for (auto &bit
: conn_sig
)
193 if (bit
.wire
!= NULL
)
194 sig_use_count
[std::pair
<RTLIL::Wire
*, int>(bit
.wire
, bit
.offset
)]++;
198 // create graph nodes from cells
199 for (auto &cell_it
: mod
->cells_
)
201 RTLIL::Cell
*cell
= cell_it
.second
;
202 if (sel
&& !sel
->selected(mod
, cell
))
205 std::string type
= cell
->type
.str();
206 if (sel
== NULL
&& type
.substr(0, 2) == "\\$")
207 type
= type
.substr(1);
208 graph
.createNode(cell
->name
.str(), type
, (void*)cell
);
210 for (auto &conn
: cell
->connections())
212 graph
.createPort(cell
->name
.str(), conn
.first
.str(), conn
.second
.size());
214 if (split
&& split
->count(std::pair
<RTLIL::IdString
, RTLIL::IdString
>(cell
->type
, conn
.first
)) > 0)
217 RTLIL::SigSpec conn_sig
= conn
.second
;
218 sigmap
.apply(conn_sig
);
220 for (int i
= 0; i
< conn_sig
.size(); i
++)
222 auto &bit
= conn_sig
[i
];
224 if (bit
.wire
== NULL
) {
226 std::string node
= "$const$x";
227 if (bit
== RTLIL::State::S0
) node
= "$const$0";
228 if (bit
== RTLIL::State::S1
) node
= "$const$1";
229 if (bit
== RTLIL::State::Sz
) node
= "$const$z";
230 graph
.createConnection(cell
->name
.str(), conn
.first
.str(), i
, node
, "\\Y", 0);
232 graph
.createConstant(cell
->name
.str(), conn
.first
.str(), i
, int(bit
.data
));
236 if (max_fanout
> 0 && sig_use_count
[std::pair
<RTLIL::Wire
*, int>(bit
.wire
, bit
.offset
)] > max_fanout
)
239 if (sel
&& !sel
->selected(mod
, bit
.wire
))
242 if (sig_bit_ref
.count(bit
) == 0) {
243 bit_ref_t
&bit_ref
= sig_bit_ref
[bit
];
244 bit_ref
.cell
= cell
->name
.str();
245 bit_ref
.port
= conn
.first
.str();
249 bit_ref_t
&bit_ref
= sig_bit_ref
[bit
];
250 graph
.createConnection(bit_ref
.cell
, bit_ref
.port
, bit_ref
.bit
, cell
->name
.str(), conn
.first
.str(), i
);
255 // mark external signals (used in non-selected cells)
256 for (auto &cell_it
: mod
->cells_
)
258 RTLIL::Cell
*cell
= cell_it
.second
;
259 if (sel
&& !sel
->selected(mod
, cell
))
260 for (auto &conn
: cell
->connections())
262 RTLIL::SigSpec conn_sig
= conn
.second
;
263 sigmap
.apply(conn_sig
);
265 for (auto &bit
: conn_sig
)
266 if (sig_bit_ref
.count(bit
) != 0) {
267 bit_ref_t
&bit_ref
= sig_bit_ref
[bit
];
268 graph
.markExtern(bit_ref
.cell
, bit_ref
.port
, bit_ref
.bit
);
273 // mark external signals (used in module ports)
274 for (auto &wire_it
: mod
->wires_
)
276 RTLIL::Wire
*wire
= wire_it
.second
;
277 if (wire
->port_id
> 0)
279 RTLIL::SigSpec
conn_sig(wire
);
280 sigmap
.apply(conn_sig
);
282 for (auto &bit
: conn_sig
)
283 if (sig_bit_ref
.count(bit
) != 0) {
284 bit_ref_t
&bit_ref
= sig_bit_ref
[bit
];
285 graph
.markExtern(bit_ref
.cell
, bit_ref
.port
, bit_ref
.bit
);
294 RTLIL::Cell
*replace(RTLIL::Module
*needle
, RTLIL::Module
*haystack
, SubCircuit::Solver::Result
&match
)
296 SigMap
sigmap(needle
);
297 SigSet
<std::pair
<RTLIL::IdString
, int>> sig2port
;
300 RTLIL::Cell
*cell
= haystack
->addCell(stringf("$extract$%s$%d", needle
->name
.c_str(), autoidx
++), needle
->name
);
303 for (auto &it
: needle
->wires_
) {
304 RTLIL::Wire
*wire
= it
.second
;
305 if (wire
->port_id
> 0) {
306 for (int i
= 0; i
< wire
->width
; i
++)
307 sig2port
.insert(sigmap(RTLIL::SigSpec(wire
, i
)), std::pair
<RTLIL::IdString
, int>(wire
->name
, i
));
308 cell
->setPort(wire
->name
, RTLIL::SigSpec(RTLIL::State::Sz
, wire
->width
));
312 // delete replaced cells and connect new ports
313 for (auto &it
: match
.mappings
)
315 auto &mapping
= it
.second
;
316 RTLIL::Cell
*needle_cell
= (RTLIL::Cell
*)mapping
.needleUserData
;
317 RTLIL::Cell
*haystack_cell
= (RTLIL::Cell
*)mapping
.haystackUserData
;
319 if (needle_cell
== NULL
)
322 for (auto &conn
: needle_cell
->connections()) {
323 RTLIL::SigSpec sig
= sigmap(conn
.second
);
324 if (mapping
.portMapping
.count(conn
.first
.str()) > 0 && sig2port
.has(sigmap(sig
))) {
325 for (int i
= 0; i
< sig
.size(); i
++)
326 for (auto &port
: sig2port
.find(sig
[i
])) {
327 RTLIL::SigSpec bitsig
= haystack_cell
->getPort(mapping
.portMapping
[conn
.first
.str()]).extract(i
, 1);
328 RTLIL::SigSpec new_sig
= cell
->getPort(port
.first
);
329 new_sig
.replace(port
.second
, bitsig
);
330 cell
->setPort(port
.first
, new_sig
);
335 haystack
->remove(haystack_cell
);
341 bool compareSortNeedleList(RTLIL::Module
*left
, RTLIL::Module
*right
)
343 int left_idx
= 0, right_idx
= 0;
344 if (left
->attributes
.count("\\extract_order") > 0)
345 left_idx
= left
->attributes
.at("\\extract_order").as_int();
346 if (right
->attributes
.count("\\extract_order") > 0)
347 right_idx
= right
->attributes
.at("\\extract_order").as_int();
348 if (left_idx
!= right_idx
)
349 return left_idx
< right_idx
;
350 return left
->name
< right
->name
;
353 struct ExtractPass
: public Pass
{
354 ExtractPass() : Pass("extract", "find subcircuits and replace them with cells") { }
355 void help() YS_OVERRIDE
357 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
359 log(" extract -map <map_file> [options] [selection]\n");
360 log(" extract -mine <out_file> [options] [selection]\n");
362 log("This pass looks for subcircuits that are isomorphic to any of the modules\n");
363 log("in the given map file and replaces them with instances of this modules. The\n");
364 log("map file can be a Verilog source file (*.v) or an ilang file (*.il).\n");
366 log(" -map <map_file>\n");
367 log(" use the modules in this file as reference. This option can be used\n");
368 log(" multiple times.\n");
370 log(" -map %%<design-name>\n");
371 log(" use the modules in this in-memory design as reference. This option can\n");
372 log(" be used multiple times.\n");
375 log(" print debug output while analyzing\n");
377 log(" -constports\n");
378 log(" also find instances with constant drivers. this may be much\n");
379 log(" slower than the normal operation.\n");
381 log(" -nodefaultswaps\n");
382 log(" normally builtin port swapping rules for internal cells are used per\n");
383 log(" default. This turns that off, so e.g. 'a^b' does not match 'b^a'\n");
384 log(" when this option is used.\n");
386 log(" -compat <needle_type> <haystack_type>\n");
387 log(" Per default, the cells in the map file (needle) must have the\n");
388 log(" type as the cells in the active design (haystack). This option\n");
389 log(" can be used to register additional pairs of types that should\n");
390 log(" match. This option can be used multiple times.\n");
392 log(" -swap <needle_type> <port1>,<port2>[,...]\n");
393 log(" Register a set of swappable ports for a needle cell type.\n");
394 log(" This option can be used multiple times.\n");
396 log(" -perm <needle_type> <port1>,<port2>[,...] <portA>,<portB>[,...]\n");
397 log(" Register a valid permutation of swappable ports for a needle\n");
398 log(" cell type. This option can be used multiple times.\n");
400 log(" -cell_attr <attribute_name>\n");
401 log(" Attributes on cells with the given name must match.\n");
403 log(" -wire_attr <attribute_name>\n");
404 log(" Attributes on wires with the given name must match.\n");
406 log(" -ignore_parameters\n");
407 log(" Do not use parameters when matching cells.\n");
409 log(" -ignore_param <cell_type> <parameter_name>\n");
410 log(" Do not use this parameter when matching cells.\n");
412 log("This pass does not operate on modules with unprocessed processes in it.\n");
413 log("(I.e. the 'proc' pass should be used first to convert processes to netlists.)\n");
415 log("This pass can also be used for mining for frequent subcircuits. In this mode\n");
416 log("the following options are to be used instead of the -map option.\n");
418 log(" -mine <out_file>\n");
419 log(" mine for frequent subcircuits and write them to the given ilang file\n");
421 log(" -mine_cells_span <min> <max>\n");
422 log(" only mine for subcircuits with the specified number of cells\n");
423 log(" default value: 3 5\n");
425 log(" -mine_min_freq <num>\n");
426 log(" only mine for subcircuits with at least the specified number of matches\n");
427 log(" default value: 10\n");
429 log(" -mine_limit_matches_per_module <num>\n");
430 log(" when calculating the number of matches for a subcircuit, don't count\n");
431 log(" more than the specified number of matches per module\n");
433 log(" -mine_max_fanout <num>\n");
434 log(" don't consider internal signals with more than <num> connections\n");
436 log("The modules in the map file may have the attribute 'extract_order' set to an\n");
437 log("integer value. Then this value is used to determine the order in which the pass\n");
438 log("tries to map the modules to the design (ascending, default value is 0).\n");
440 log("See 'help techmap' for a pass that does the opposite thing.\n");
443 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
445 log_header(design
, "Executing EXTRACT pass (map subcircuits to cells).\n");
448 SubCircuitSolver solver
;
450 std::vector
<std::string
> map_filenames
;
451 std::string mine_outfile
;
452 bool constports
= false;
453 bool nodefaultswaps
= false;
455 bool mine_mode
= false;
456 int mine_cells_min
= 3;
457 int mine_cells_max
= 5;
458 int mine_min_freq
= 10;
459 int mine_limit_mod
= -1;
460 int mine_max_fanout
= -1;
461 std::set
<std::pair
<RTLIL::IdString
, RTLIL::IdString
>> mine_split
;
464 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
465 if (args
[argidx
] == "-map" && argidx
+1 < args
.size()) {
467 log_cmd_error("You cannot mix -map and -mine.\n");
468 map_filenames
.push_back(args
[++argidx
]);
471 if (args
[argidx
] == "-mine" && argidx
+1 < args
.size()) {
472 if (!map_filenames
.empty())
473 log_cmd_error("You cannot mix -map and -mine.\n");
474 mine_outfile
= args
[++argidx
];
478 if (args
[argidx
] == "-mine_cells_span" && argidx
+2 < args
.size()) {
479 mine_cells_min
= atoi(args
[++argidx
].c_str());
480 mine_cells_max
= atoi(args
[++argidx
].c_str());
483 if (args
[argidx
] == "-mine_min_freq" && argidx
+1 < args
.size()) {
484 mine_min_freq
= atoi(args
[++argidx
].c_str());
487 if (args
[argidx
] == "-mine_limit_matches_per_module" && argidx
+1 < args
.size()) {
488 mine_limit_mod
= atoi(args
[++argidx
].c_str());
491 if (args
[argidx
] == "-mine_split" && argidx
+2 < args
.size()) {
492 mine_split
.insert(std::pair
<RTLIL::IdString
, RTLIL::IdString
>(RTLIL::escape_id(args
[argidx
+1]), RTLIL::escape_id(args
[argidx
+2])));
496 if (args
[argidx
] == "-mine_max_fanout" && argidx
+1 < args
.size()) {
497 mine_max_fanout
= atoi(args
[++argidx
].c_str());
500 if (args
[argidx
] == "-verbose") {
504 if (args
[argidx
] == "-constports") {
508 if (args
[argidx
] == "-nodefaultswaps") {
509 nodefaultswaps
= true;
512 if (args
[argidx
] == "-compat" && argidx
+2 < args
.size()) {
513 std::string needle_type
= RTLIL::escape_id(args
[++argidx
]);
514 std::string haystack_type
= RTLIL::escape_id(args
[++argidx
]);
515 solver
.addCompatibleTypes(needle_type
, haystack_type
);
518 if (args
[argidx
] == "-swap" && argidx
+2 < args
.size()) {
519 std::string type
= RTLIL::escape_id(args
[++argidx
]);
520 std::set
<std::string
> ports
;
521 std::string ports_str
= args
[++argidx
], p
;
522 while (!(p
= next_token(ports_str
, ",\t\r\n ")).empty())
523 ports
.insert(RTLIL::escape_id(p
));
524 solver
.addSwappablePorts(type
, ports
);
527 if (args
[argidx
] == "-perm" && argidx
+3 < args
.size()) {
528 std::string type
= RTLIL::escape_id(args
[++argidx
]);
529 std::vector
<std::string
> map_left
, map_right
;
530 std::string left_str
= args
[++argidx
];
531 std::string right_str
= args
[++argidx
], p
;
532 while (!(p
= next_token(left_str
, ",\t\r\n ")).empty())
533 map_left
.push_back(RTLIL::escape_id(p
));
534 while (!(p
= next_token(right_str
, ",\t\r\n ")).empty())
535 map_right
.push_back(RTLIL::escape_id(p
));
536 if (map_left
.size() != map_right
.size())
537 log_cmd_error("Arguments to -perm are not a valid permutation!\n");
538 std::map
<std::string
, std::string
> map
;
539 for (size_t i
= 0; i
< map_left
.size(); i
++)
540 map
[map_left
[i
]] = map_right
[i
];
541 std::sort(map_left
.begin(), map_left
.end());
542 std::sort(map_right
.begin(), map_right
.end());
543 if (map_left
!= map_right
)
544 log_cmd_error("Arguments to -perm are not a valid permutation!\n");
545 solver
.addSwappablePortsPermutation(type
, map
);
548 if (args
[argidx
] == "-cell_attr" && argidx
+1 < args
.size()) {
549 solver
.cell_attr
.insert(RTLIL::escape_id(args
[++argidx
]));
552 if (args
[argidx
] == "-wire_attr" && argidx
+1 < args
.size()) {
553 solver
.wire_attr
.insert(RTLIL::escape_id(args
[++argidx
]));
556 if (args
[argidx
] == "-ignore_parameters") {
557 solver
.ignore_parameters
= true;
560 if (args
[argidx
] == "-ignore_param" && argidx
+2 < args
.size()) {
561 solver
.ignored_parameters
.insert(std::pair
<RTLIL::IdString
, RTLIL::IdString
>(RTLIL::escape_id(args
[argidx
+1]), RTLIL::escape_id(args
[argidx
+2])));
567 extra_args(args
, argidx
, design
);
569 if (!nodefaultswaps
) {
570 solver
.addSwappablePorts("$and", "\\A", "\\B");
571 solver
.addSwappablePorts("$or", "\\A", "\\B");
572 solver
.addSwappablePorts("$xor", "\\A", "\\B");
573 solver
.addSwappablePorts("$xnor", "\\A", "\\B");
574 solver
.addSwappablePorts("$eq", "\\A", "\\B");
575 solver
.addSwappablePorts("$ne", "\\A", "\\B");
576 solver
.addSwappablePorts("$eqx", "\\A", "\\B");
577 solver
.addSwappablePorts("$nex", "\\A", "\\B");
578 solver
.addSwappablePorts("$add", "\\A", "\\B");
579 solver
.addSwappablePorts("$mul", "\\A", "\\B");
580 solver
.addSwappablePorts("$logic_and", "\\A", "\\B");
581 solver
.addSwappablePorts("$logic_or", "\\A", "\\B");
582 solver
.addSwappablePorts("$_AND_", "\\A", "\\B");
583 solver
.addSwappablePorts("$_OR_", "\\A", "\\B");
584 solver
.addSwappablePorts("$_XOR_", "\\A", "\\B");
587 if (map_filenames
.empty() && mine_outfile
.empty())
588 log_cmd_error("Missing option -map <verilog_or_ilang_file> or -mine <output_ilang_file>.\n");
590 RTLIL::Design
*map
= NULL
;
594 map
= new RTLIL::Design
;
595 for (auto &filename
: map_filenames
)
597 if (filename
.substr(0, 1) == "%")
599 if (!saved_designs
.count(filename
.substr(1))) {
601 log_cmd_error("Can't saved design `%s'.\n", filename
.c_str()+1);
603 for (auto mod
: saved_designs
.at(filename
.substr(1))->modules())
604 if (!map
->has(mod
->name
))
605 map
->add(mod
->clone());
610 rewrite_filename(filename
);
611 f
.open(filename
.c_str());
614 log_cmd_error("Can't open map file `%s'.\n", filename
.c_str());
616 Frontend::frontend_call(map
, &f
, filename
, (filename
.size() > 3 && filename
.substr(filename
.size()-3) == ".il") ? "ilang" : "verilog");
619 if (filename
.size() <= 3 || filename
.substr(filename
.size()-3) != ".il") {
620 Pass::call(map
, "proc");
621 Pass::call(map
, "opt_clean");
627 std::map
<std::string
, RTLIL::Module
*> needle_map
, haystack_map
;
628 std::vector
<RTLIL::Module
*> needle_list
;
630 log_header(design
, "Creating graphs for SubCircuit library.\n");
633 for (auto &mod_it
: map
->modules_
) {
634 SubCircuit::Graph mod_graph
;
635 std::string graph_name
= "needle_" + RTLIL::unescape_id(mod_it
.first
);
636 log("Creating needle graph %s.\n", graph_name
.c_str());
637 if (module2graph(mod_graph
, mod_it
.second
, constports
)) {
638 solver
.addGraph(graph_name
, mod_graph
);
639 needle_map
[graph_name
] = mod_it
.second
;
640 needle_list
.push_back(mod_it
.second
);
644 for (auto &mod_it
: design
->modules_
) {
645 SubCircuit::Graph mod_graph
;
646 std::string graph_name
= "haystack_" + RTLIL::unescape_id(mod_it
.first
);
647 log("Creating haystack graph %s.\n", graph_name
.c_str());
648 if (module2graph(mod_graph
, mod_it
.second
, constports
, design
, mine_mode
? mine_max_fanout
: -1, mine_mode
? &mine_split
: NULL
)) {
649 solver
.addGraph(graph_name
, mod_graph
);
650 haystack_map
[graph_name
] = mod_it
.second
;
656 std::vector
<SubCircuit::Solver::Result
> results
;
657 log_header(design
, "Running solver from SubCircuit library.\n");
659 std::sort(needle_list
.begin(), needle_list
.end(), compareSortNeedleList
);
661 for (auto needle
: needle_list
)
662 for (auto &haystack_it
: haystack_map
) {
663 log("Solving for %s in %s.\n", ("needle_" + RTLIL::unescape_id(needle
->name
)).c_str(), haystack_it
.first
.c_str());
664 solver
.solve(results
, "needle_" + RTLIL::unescape_id(needle
->name
), haystack_it
.first
, false);
666 log("Found %d matches.\n", GetSize(results
));
668 if (results
.size() > 0)
670 log_header(design
, "Substitute SubCircuits with cells.\n");
672 for (int i
= 0; i
< int(results
.size()); i
++) {
673 auto &result
= results
[i
];
674 log("\nMatch #%d: (%s in %s)\n", i
, result
.needleGraphId
.c_str(), result
.haystackGraphId
.c_str());
675 for (const auto &it
: result
.mappings
) {
676 log(" %s -> %s", it
.first
.c_str(), it
.second
.haystackNodeId
.c_str());
677 for (const auto & it2
: it
.second
.portMapping
)
678 log(" %s:%s", it2
.first
.c_str(), it2
.second
.c_str());
681 RTLIL::Cell
*new_cell
= replace(needle_map
.at(result
.needleGraphId
), haystack_map
.at(result
.haystackGraphId
), result
);
682 design
->select(haystack_map
.at(result
.haystackGraphId
), new_cell
);
683 log(" new cell: %s\n", id2cstr(new_cell
->name
));
689 std::vector
<SubCircuit::Solver::MineResult
> results
;
691 log_header(design
, "Running miner from SubCircuit library.\n");
692 solver
.mine(results
, mine_cells_min
, mine_cells_max
, mine_min_freq
, mine_limit_mod
);
694 map
= new RTLIL::Design
;
696 int needleCounter
= 0;
697 for (auto &result
: results
)
699 log("\nFrequent SubCircuit with %d nodes and %d matches:\n", int(result
.nodes
.size()), result
.totalMatchesAfterLimits
);
700 log(" primary match in %s:", id2cstr(haystack_map
.at(result
.graphId
)->name
));
701 for (auto &node
: result
.nodes
)
702 log(" %s", RTLIL::unescape_id(node
.nodeId
).c_str());
704 for (auto &it
: result
.matchesPerGraph
)
705 log(" matches in %s: %d\n", id2cstr(haystack_map
.at(it
.first
)->name
), it
.second
);
707 RTLIL::Module
*mod
= haystack_map
.at(result
.graphId
);
708 std::set
<RTLIL::Cell
*> cells
;
709 std::set
<RTLIL::Wire
*> wires
;
713 for (auto &node
: result
.nodes
)
714 cells
.insert((RTLIL::Cell
*)node
.userData
);
716 for (auto cell
: cells
)
717 for (auto &conn
: cell
->connections()) {
718 RTLIL::SigSpec sig
= sigmap(conn
.second
);
719 for (auto &chunk
: sig
.chunks())
720 if (chunk
.wire
!= NULL
)
721 wires
.insert(chunk
.wire
);
724 RTLIL::Module
*newMod
= new RTLIL::Module
;
725 newMod
->name
= stringf("\\needle%05d_%s_%dx", needleCounter
++, id2cstr(haystack_map
.at(result
.graphId
)->name
), result
.totalMatchesAfterLimits
);
728 for (auto wire
: wires
) {
729 RTLIL::Wire
*newWire
= newMod
->addWire(wire
->name
, wire
->width
);
730 newWire
->port_input
= true;
731 newWire
->port_output
= true;
734 newMod
->fixup_ports();
736 for (auto cell
: cells
) {
737 RTLIL::Cell
*newCell
= newMod
->addCell(cell
->name
, cell
->type
);
738 newCell
->parameters
= cell
->parameters
;
739 for (auto &conn
: cell
->connections()) {
740 std::vector
<SigChunk
> chunks
= sigmap(conn
.second
);
741 for (auto &chunk
: chunks
)
742 if (chunk
.wire
!= NULL
)
743 chunk
.wire
= newMod
->wires_
.at(chunk
.wire
->name
);
744 newCell
->setPort(conn
.first
, chunks
);
750 rewrite_filename(mine_outfile
);
751 f
.open(mine_outfile
.c_str(), std::ofstream::trunc
);
753 log_error("Can't open output file `%s'.\n", mine_outfile
.c_str());
754 Backend::backend_call(map
, &f
, mine_outfile
, "ilang");
763 PRIVATE_NAMESPACE_END