projects / yosys.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Merge pull request #1188 from YosysHQ/eddie/abc9_push_inverters
[yosys.git] / passes / techmap / extract_fa.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22 #include "kernel/consteval.h"
23
24 USING_YOSYS_NAMESPACE
25 PRIVATE_NAMESPACE_BEGIN
26
27 struct ExtractFaConfig
28 {
29 bool enable_fa = false;
30 bool enable_ha = false;
31 bool verbose = false;
32 int maxdepth = 20;
33 int maxbreadth = 6;
34 };
35
36 // http://svn.clifford.at/handicraft/2016/bindec/bindec.c
37 int bindec(unsigned char v)
38 {
39 int r = v & 1;
40 r += (~((v & 2) - 1)) & 10;
41 r += (~((v & 4) - 1)) & 100;
42 r += (~((v & 8) - 1)) & 1000;
43 r += (~((v & 16) - 1)) & 10000;
44 r += (~((v & 32) - 1)) & 100000;
45 r += (~((v & 64) - 1)) & 1000000;
46 r += (~((v & 128) - 1)) & 10000000;
47 return r;
48 }
49
50 struct ExtractFaWorker
51 {
52 const ExtractFaConfig &config;
53 Module *module;
54 ConstEval ce;
55 SigMap &sigmap;
56
57 dict<SigBit, Cell*> driver;
58 pool<SigBit> handled_bits;
59
60 const int xor2_func = 0x6, xnor2_func = 0x9;
61 const int xor3_func = 0x96, xnor3_func = 0x69;
62
63 pool<tuple<SigBit, SigBit>> xorxnor2;
64 pool<tuple<SigBit, SigBit, SigBit>> xorxnor3;
65
66 dict<tuple<SigBit, SigBit>, dict<int, pool<SigBit>>> func2;
67 dict<tuple<SigBit, SigBit, SigBit>, dict<int, pool<SigBit>>> func3;
68
69 int count_func2;
70 int count_func3;
71
72 struct func2_and_info_t {
73 bool inv_a, inv_b, inv_y;
74 };
75
76 struct func3_maj_info_t {
77 bool inv_a, inv_b, inv_c, inv_y;
78 };
79
80 dict<int, func2_and_info_t> func2_and_info;
81 dict<int, func3_maj_info_t> func3_maj_info;
82
83 ExtractFaWorker(const ExtractFaConfig &config, Module *module) :
84 config(config), module(module), ce(module), sigmap(ce.assign_map)
85 {
86 for (auto cell : module->selected_cells())
87 {
88 if (cell->type.in( "$_BUF_", "$_NOT_", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_",
89 "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_", "$_MUX_",
90 "$_AOI3_", "$_OAI3_", "$_AOI4_", "$_OAI4_"))
91 {
92 SigBit y = sigmap(SigBit(cell->getPort("\\Y")));
93 log_assert(driver.count(y) == 0);
94 driver[y] = cell;
95 }
96 }
97
98 for (int ia = 0; ia < 2; ia++)
99 for (int ib = 0; ib < 2; ib++)
100 {
101 func2_and_info_t f2i;
102
103 f2i.inv_a = ia;
104 f2i.inv_b = ib;
105 f2i.inv_y = false;
106
107 int func = 0;
108 for (int i = 0; i < 4; i++)
109 {
110 bool a = (i & 1) ? !f2i.inv_a : f2i.inv_a;
111 bool b = (i & 2) ? !f2i.inv_b : f2i.inv_b;
112 if (a && b) func |= 1 << i;
113 }
114
115 log_assert(func2_and_info.count(func) == 0);
116 func2_and_info[func] = f2i;
117
118 f2i.inv_y = true;
119 func ^= 15;
120
121 log_assert(func2_and_info.count(func) == 0);
122 func2_and_info[func] = f2i;
123 }
124
125 for (int ia = 0; ia < 2; ia++)
126 for (int ib = 0; ib < 2; ib++)
127 for (int ic = 0; ic < 2; ic++)
128 {
129 func3_maj_info_t f3i;
130
131 f3i.inv_a = ia;
132 f3i.inv_b = ib;
133 f3i.inv_c = ic;
134 f3i.inv_y = false;
135
136 int func = 0;
137 for (int i = 0; i < 8; i++)
138 {
139 bool a = (i & 1) ? !f3i.inv_a : f3i.inv_a;
140 bool b = (i & 2) ? !f3i.inv_b : f3i.inv_b;
141 bool c = (i & 4) ? !f3i.inv_c : f3i.inv_c;
142 if ((a && b) || (a && c) || (b &&c)) func |= 1 << i;
143 }
144
145 log_assert(func3_maj_info.count(func) == 0);
146 func3_maj_info[func] = f3i;
147
148 // f3i.inv_y = true;
149 // func ^= 255;
150
151 // log_assert(func3_maj_info.count(func) == 0);
152 // func3_maj_info[func] = f3i;
153 }
154 }
155
156 void check_partition(SigBit root, pool<SigBit> &leaves)
157 {
158 if (config.enable_ha && GetSize(leaves) == 2)
159 {
160 leaves.sort();
161
162 SigBit A = SigSpec(leaves)[0];
163 SigBit B = SigSpec(leaves)[1];
164
165 int func = 0;
166 for (int i = 0; i < 4; i++)
167 {
168 bool a_value = (i & 1) != 0;
169 bool b_value = (i & 2) != 0;
170
171 ce.push();
172 ce.set(A, a_value ? State::S1 : State::S0);
173 ce.set(B, b_value ? State::S1 : State::S0);
174
175 SigSpec sig = root;
176
177 if (!ce.eval(sig)) {
178 ce.pop();
179 return;
180 }
181
182 if (sig == State::S1)
183 func |= 1 << i;
184
185 ce.pop();
186 }
187
188 // log("%04d %s %s -> %s\n", bindec(func), log_signal(A), log_signal(B), log_signal(root));
189
190 if (func == xor2_func || func == xnor2_func)
191 xorxnor2.insert(tuple<SigBit, SigBit>(A, B));
192
193 count_func2++;
194 func2[tuple<SigBit, SigBit>(A, B)][func].insert(root);
195 }
196
197 if (config.enable_fa && GetSize(leaves) == 3)
198 {
199 leaves.sort();
200
201 SigBit A = SigSpec(leaves)[0];
202 SigBit B = SigSpec(leaves)[1];
203 SigBit C = SigSpec(leaves)[2];
204
205 int func = 0;
206 for (int i = 0; i < 8; i++)
207 {
208 bool a_value = (i & 1) != 0;
209 bool b_value = (i & 2) != 0;
210 bool c_value = (i & 4) != 0;
211
212 ce.push();
213 ce.set(A, a_value ? State::S1 : State::S0);
214 ce.set(B, b_value ? State::S1 : State::S0);
215 ce.set(C, c_value ? State::S1 : State::S0);
216
217 SigSpec sig = root;
218
219 if (!ce.eval(sig)) {
220 ce.pop();
221 return;
222 }
223
224 if (sig == State::S1)
225 func |= 1 << i;
226
227 ce.pop();
228 }
229
230 // log("%08d %s %s %s -> %s\n", bindec(func), log_signal(A), log_signal(B), log_signal(C), log_signal(root));
231
232 if (func == xor3_func || func == xnor3_func)
233 xorxnor3.insert(tuple<SigBit, SigBit, SigBit>(A, B, C));
234
235 count_func3++;
236 func3[tuple<SigBit, SigBit, SigBit>(A, B, C)][func].insert(root);
237 }
238 }
239
240 void find_partitions(SigBit root, pool<SigBit> &leaves, pool<pool<SigBit>> &cache, int maxdepth, int maxbreadth)
241 {
242 if (cache.count(leaves))
243 return;
244
245 // log("%*s[%d] %s:", 20-maxdepth, "", maxdepth, log_signal(root));
246 // for (auto bit : leaves)
247 // log(" %s", log_signal(bit));
248 // log("\n");
249
250 cache.insert(leaves);
251 check_partition(root, leaves);
252
253 if (maxdepth == 0)
254 return;
255
256 for (SigBit bit : leaves)
257 {
258 if (driver.count(bit) == 0)
259 continue;
260
261 Cell *cell = driver.at(bit);
262 pool<SigBit> new_leaves = leaves;
263
264 new_leaves.erase(bit);
265 if (cell->hasPort("\\A")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\A"))));
266 if (cell->hasPort("\\B")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\B"))));
267 if (cell->hasPort("\\C")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\C"))));
268 if (cell->hasPort("\\D")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\D"))));
269
270 if (GetSize(new_leaves) > maxbreadth)
271 continue;
272
273 find_partitions(root, new_leaves, cache, maxdepth-1, maxbreadth);
274 }
275 }
276
277 void assign_new_driver(SigBit bit, SigBit new_driver)
278 {
279 Cell *cell = driver.at(bit);
280 if (sigmap(cell->getPort("\\Y")) == bit) {
281 cell->setPort("\\Y", module->addWire(NEW_ID));
282 module->connect(bit, new_driver);
283 }
284 }
285
286 void run()
287 {
288 log("Extracting full/half adders from %s:\n", log_id(module));
289
290 for (auto it : driver)
291 {
292 if (it.second->type.in("$_BUF_", "$_NOT_"))
293 continue;
294
295 SigBit root = it.first;
296 pool<SigBit> leaves = { root };
297 pool<pool<SigBit>> cache;
298
299 if (config.verbose)
300 log(" checking %s\n", log_signal(it.first));
301
302 count_func2 = 0;
303 count_func3 = 0;
304
305 find_partitions(root, leaves, cache, config.maxdepth, config.maxbreadth);
306
307 if (config.verbose && count_func2 > 0)
308 log(" extracted %d two-input functions\n", count_func2);
309
310 if (config.verbose && count_func3 > 0)
311 log(" extracted %d three-input functions\n", count_func3);
312 }
313
314 for (auto &key : xorxnor3)
315 {
316 SigBit A = get<0>(key);
317 SigBit B = get<1>(key);
318 SigBit C = get<2>(key);
319
320 log(" 3-Input XOR/XNOR %s %s %s:\n", log_signal(A), log_signal(B), log_signal(C));
321
322 for (auto &it : func3.at(key))
323 {
324 if (it.first != xor3_func && it.first != xnor3_func)
325 continue;
326
327 log(" %08d ->", bindec(it.first));
328 for (auto bit : it.second)
329 log(" %s", log_signal(bit));
330 log("\n");
331 }
332
333 dict<int, tuple<SigBit, SigBit, Cell*>> facache;
334
335 for (auto &it : func3_maj_info)
336 {
337 int func = it.first;
338 auto f3i = it.second;
339
340 if (func3.at(key).count(func) == 0)
341 continue;
342
343 if (func3.at(key).count(xor3_func) == 0 && func3.at(key).count(xnor3_func) != 0) {
344 f3i.inv_a = !f3i.inv_a;
345 f3i.inv_b = !f3i.inv_b;
346 f3i.inv_c = !f3i.inv_c;
347 f3i.inv_y = !f3i.inv_y;
348 }
349
350 if (!f3i.inv_a && !f3i.inv_b && !f3i.inv_c && !f3i.inv_y) {
351 log(" Majority without inversions:\n");
352 } else {
353 log(" Majority with inverted");
354 if (f3i.inv_a) log(" A");
355 if (f3i.inv_b) log(" B");
356 if (f3i.inv_c) log(" C");
357 if (f3i.inv_y) log(" Y");
358 log(":\n");
359 }
360
361 log(" %08d ->", bindec(func));
362 for (auto bit : func3.at(key).at(func))
363 log(" %s", log_signal(bit));
364 log("\n");
365
366 int fakey = 0;
367 if (f3i.inv_a) fakey |= 1;
368 if (f3i.inv_b) fakey |= 2;
369 if (f3i.inv_c) fakey |= 4;
370
371 int fakey_inv = fakey ^ 7;
372 bool invert_xy = false;
373 SigBit X, Y;
374
375 if (facache.count(fakey))
376 {
377 auto &fa = facache.at(fakey);
378 X = get<0>(fa);
379 Y = get<1>(fa);
380 log(" Reusing $fa cell %s.\n", log_id(get<2>(fa)));
381 }
382 else
383 if (facache.count(fakey_inv))
384 {
385 auto &fa = facache.at(fakey_inv);
386 invert_xy = true;
387 X = get<0>(fa);
388 Y = get<1>(fa);
389 log(" Reusing $fa cell %s.\n", log_id(get<2>(fa)));
390 }
391 else
392 {
393 Cell *cell = module->addCell(NEW_ID, "$fa");
394 cell->setParam("\\WIDTH", 1);
395
396 log(" Created $fa cell %s.\n", log_id(cell));
397
398 cell->setPort("\\A", f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
399 cell->setPort("\\B", f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
400 cell->setPort("\\C", f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
401
402 X = module->addWire(NEW_ID);
403 Y = module->addWire(NEW_ID);
404
405 cell->setPort("\\X", X);
406 cell->setPort("\\Y", Y);
407
408 facache[fakey] = make_tuple(X, Y, cell);
409 }
410
411 if (func3.at(key).count(xor3_func)) {
412 SigBit YY = invert_xy ? module->NotGate(NEW_ID, Y) : Y;
413 for (auto bit : func3.at(key).at(xor3_func))
414 assign_new_driver(bit, YY);
415 }
416
417 if (func3.at(key).count(xnor3_func)) {
418 SigBit YY = invert_xy ? Y : module->NotGate(NEW_ID, Y);
419 for (auto bit : func3.at(key).at(xnor3_func))
420 assign_new_driver(bit, YY);
421 }
422
423 SigBit XX = invert_xy != f3i.inv_y ? module->NotGate(NEW_ID, X) : X;
424
425 for (auto bit : func3.at(key).at(func))
426 assign_new_driver(bit, XX);
427 }
428 }
429
430 for (auto &key : xorxnor2)
431 {
432 SigBit A = get<0>(key);
433 SigBit B = get<1>(key);
434
435 log(" 2-Input XOR/XNOR %s %s:\n", log_signal(A), log_signal(B));
436
437 for (auto &it : func2.at(key))
438 {
439 if (it.first != xor2_func && it.first != xnor2_func)
440 continue;
441
442 log(" %04d ->", bindec(it.first));
443 for (auto bit : it.second)
444 log(" %s", log_signal(bit));
445 log("\n");
446 }
447
448 dict<int, tuple<SigBit, SigBit, Cell*>> facache;
449
450 for (auto &it : func2_and_info)
451 {
452 int func = it.first;
453 auto &f2i = it.second;
454
455 if (func2.at(key).count(func) == 0)
456 continue;
457
458 if (!f2i.inv_a && !f2i.inv_b && !f2i.inv_y) {
459 log(" AND without inversions:\n");
460 } else {
461 log(" AND with inverted");
462 if (f2i.inv_a) log(" A");
463 if (f2i.inv_b) log(" B");
464 if (f2i.inv_y) log(" Y");
465 log(":\n");
466 }
467
468 log(" %04d ->", bindec(func));
469 for (auto bit : func2.at(key).at(func))
470 log(" %s", log_signal(bit));
471 log("\n");
472
473 int fakey = 0;
474 if (f2i.inv_a) fakey |= 1;
475 if (f2i.inv_b) fakey |= 2;
476
477 int fakey_inv = fakey ^ 3;
478 bool invert_xy = false;
479 SigBit X, Y;
480
481 if (facache.count(fakey))
482 {
483 auto &fa = facache.at(fakey);
484 X = get<0>(fa);
485 Y = get<1>(fa);
486 log(" Reusing $fa cell %s.\n", log_id(get<2>(fa)));
487 }
488 else
489 if (facache.count(fakey_inv))
490 {
491 auto &fa = facache.at(fakey_inv);
492 invert_xy = true;
493 X = get<0>(fa);
494 Y = get<1>(fa);
495 log(" Reusing $fa cell %s.\n", log_id(get<2>(fa)));
496 }
497 else
498 {
499 Cell *cell = module->addCell(NEW_ID, "$fa");
500 cell->setParam("\\WIDTH", 1);
501
502 log(" Created $fa cell %s.\n", log_id(cell));
503
504 cell->setPort("\\A", f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
505 cell->setPort("\\B", f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
506 cell->setPort("\\C", State::S0);
507
508 X = module->addWire(NEW_ID);
509 Y = module->addWire(NEW_ID);
510
511 cell->setPort("\\X", X);
512 cell->setPort("\\Y", Y);
513 }
514
515 if (func2.at(key).count(xor2_func)) {
516 SigBit YY = invert_xy ? module->NotGate(NEW_ID, Y) : Y;
517 for (auto bit : func2.at(key).at(xor2_func))
518 assign_new_driver(bit, YY);
519 }
520
521 if (func2.at(key).count(xnor2_func)) {
522 SigBit YY = invert_xy ? Y : module->NotGate(NEW_ID, Y);
523 for (auto bit : func2.at(key).at(xnor2_func))
524 assign_new_driver(bit, YY);
525 }
526
527 SigBit XX = invert_xy != f2i.inv_y ? module->NotGate(NEW_ID, X) : X;
528
529 for (auto bit : func2.at(key).at(func))
530 assign_new_driver(bit, XX);
531 }
532 }
533 }
534 };
535
536 struct ExtractFaPass : public Pass {
537 ExtractFaPass() : Pass("extract_fa", "find and extract full/half adders") { }
538 void help() YS_OVERRIDE
539 {
540 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
541 log("\n");
542 log(" extract_fa [options] [selection]\n");
543 log("\n");
544 log("This pass extracts full/half adders from a gate-level design.\n");
545 log("\n");
546 log(" -fa, -ha\n");
547 log(" Enable cell types (fa=full adder, ha=half adder)\n");
548 log(" All types are enabled if none of this options is used\n");
549 log("\n");
550 log(" -d <int>\n");
551 log(" Set maximum depth for extracted logic cones (default=20)\n");
552 log("\n");
553 log(" -b <int>\n");
554 log(" Set maximum breadth for extracted logic cones (default=6)\n");
555 log("\n");
556 log(" -v\n");
557 log(" Verbose output\n");
558 log("\n");
559 }
560 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
561 {
562 ExtractFaConfig config;
563
564 log_header(design, "Executing EXTRACT_FA pass (find and extract full/half adders).\n");
565 log_push();
566
567 size_t argidx;
568 for (argidx = 1; argidx < args.size(); argidx++)
569 {
570 if (args[argidx] == "-fa") {
571 config.enable_fa = true;
572 continue;
573 }
574 if (args[argidx] == "-ha") {
575 config.enable_ha = true;
576 continue;
577 }
578 if (args[argidx] == "-v") {
579 config.verbose = true;
580 continue;
581 }
582 if (args[argidx] == "-d" && argidx+2 < args.size()) {
583 config.maxdepth = atoi(args[++argidx].c_str());
584 continue;
585 }
586 if (args[argidx] == "-b" && argidx+2 < args.size()) {
587 config.maxbreadth = atoi(args[++argidx].c_str());
588 continue;
589 }
590 break;
591 }
592 extra_args(args, argidx, design);
593
594 if (!config.enable_fa && !config.enable_ha) {
595 config.enable_fa = true;
596 config.enable_ha = true;
597 }
598
599 for (auto module : design->selected_modules())
600 {
601 ExtractFaWorker worker(config, module);
602 worker.run();
603 }
604
605 log_pop();
606 }
607 } ExtractFaPass;
608
609 PRIVATE_NAMESPACE_END