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Further improve extract_fa (but still buggy)
[yosys.git] / passes / techmap / extract_fa.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22 #include "kernel/consteval.h"
23
24 USING_YOSYS_NAMESPACE
25 PRIVATE_NAMESPACE_BEGIN
26
27 struct ExtractFaConfig
28 {
29 bool enable_fa = false;
30 bool enable_ha = false;
31 bool verbose = false;
32 int maxdepth = 20;
33 int maxbreadth = 6;
34 };
35
36 // http://svn.clifford.at/handicraft/2016/bindec/bindec.c
37 int bindec(unsigned char v)
38 {
39 int r = v & 1;
40 r += (~((v & 2) - 1)) & 10;
41 r += (~((v & 4) - 1)) & 100;
42 r += (~((v & 8) - 1)) & 1000;
43 r += (~((v & 16) - 1)) & 10000;
44 r += (~((v & 32) - 1)) & 100000;
45 r += (~((v & 64) - 1)) & 1000000;
46 r += (~((v & 128) - 1)) & 10000000;
47 return r;
48 }
49
50 struct ExtractFaWorker
51 {
52 const ExtractFaConfig &config;
53 Module *module;
54 ConstEval ce;
55 SigMap &sigmap;
56
57 dict<SigBit, Cell*> driver;
58 pool<SigBit> handled_bits;
59
60 const int xor2_func = 0x6, xnor2_func = 0x9;
61 const int xor3_func = 0x96, xnor3_func = 0x69;
62
63 pool<tuple<SigBit, SigBit>> xorxnor2;
64 pool<tuple<SigBit, SigBit, SigBit>> xorxnor3;
65
66 dict<tuple<SigBit, SigBit>, dict<int, pool<SigBit>>> func2;
67 dict<tuple<SigBit, SigBit, SigBit>, dict<int, pool<SigBit>>> func3;
68
69 int count_func2;
70 int count_func3;
71
72 struct func2_and_info_t {
73 bool inv_a, inv_b, inv_y;
74 };
75
76 struct func3_maj_info_t {
77 bool inv_a, inv_b, inv_c, inv_y;
78 };
79
80 dict<int, func2_and_info_t> func2_and_info;
81 dict<int, func3_maj_info_t> func3_maj_info;
82
83 ExtractFaWorker(const ExtractFaConfig &config, Module *module) :
84 config(config), module(module), ce(module), sigmap(ce.assign_map)
85 {
86 for (auto cell : module->selected_cells())
87 {
88 if (cell->type.in( "$_BUF_", "$_NOT_", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_",
89 "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_", "$_MUX_",
90 "$_AOI3_", "$_OAI3_", "$_AOI4_", "$_OAI4_"))
91 {
92 SigBit y = sigmap(SigBit(cell->getPort("\\Y")));
93 log_assert(driver.count(y) == 0);
94 driver[y] = cell;
95 }
96 }
97
98 for (int ia = 0; ia < 2; ia++)
99 for (int ib = 0; ib < 2; ib++)
100 {
101 func2_and_info_t f2i;
102
103 f2i.inv_a = ia;
104 f2i.inv_b = ib;
105 f2i.inv_y = false;
106
107 int func = 0;
108 for (int i = 0; i < 4; i++)
109 {
110 bool a = (i & 1) ? !f2i.inv_a : f2i.inv_a;
111 bool b = (i & 2) ? !f2i.inv_b : f2i.inv_b;
112 if (a && b) func |= 1 << i;
113 }
114
115 log_assert(func2_and_info.count(func) == 0);
116 func2_and_info[func] = f2i;
117
118 f2i.inv_y = true;
119 func ^= 15;
120
121 log_assert(func2_and_info.count(func) == 0);
122 func2_and_info[func] = f2i;
123 }
124
125 for (int ia = 0; ia < 2; ia++)
126 for (int ib = 0; ib < 2; ib++)
127 for (int ic = 0; ic < 2; ic++)
128 {
129 func3_maj_info_t f3i;
130
131 f3i.inv_a = ia;
132 f3i.inv_b = ib;
133 f3i.inv_c = ic;
134 f3i.inv_y = false;
135
136 int func = 0;
137 for (int i = 0; i < 8; i++)
138 {
139 bool a = (i & 1) ? !f3i.inv_a : f3i.inv_a;
140 bool b = (i & 2) ? !f3i.inv_b : f3i.inv_b;
141 bool c = (i & 4) ? !f3i.inv_c : f3i.inv_c;
142 if ((a && b) || (a && c) || (b &&c)) func |= 1 << i;
143 }
144
145 log_assert(func3_maj_info.count(func) == 0);
146 func3_maj_info[func] = f3i;
147
148 // f3i.inv_y = true;
149 // func ^= 255;
150
151 // log_assert(func3_maj_info.count(func) == 0);
152 // func3_maj_info[func] = f3i;
153 }
154 }
155
156 void check_partition(SigBit root, pool<SigBit> &leaves)
157 {
158 if (config.enable_ha && GetSize(leaves) == 2)
159 {
160 leaves.sort();
161
162 SigBit A = SigSpec(leaves)[0];
163 SigBit B = SigSpec(leaves)[1];
164
165 int func = 0;
166 for (int i = 0; i < 4; i++)
167 {
168 bool a_value = (i & 1) != 0;
169 bool b_value = (i & 2) != 0;
170
171 ce.push();
172 ce.set(A, a_value ? State::S1 : State::S0);
173 ce.set(B, b_value ? State::S1 : State::S0);
174
175 SigSpec sig = root;
176
177 if (!ce.eval(sig))
178 log_abort();
179
180 if (sig == State::S1)
181 func |= 1 << i;
182
183 ce.pop();
184 }
185
186 // log("%04d %s %s -> %s\n", bindec(func), log_signal(A), log_signal(B), log_signal(root));
187
188 if (func == xor2_func || func == xnor2_func)
189 xorxnor2.insert(tuple<SigBit, SigBit>(A, B));
190
191 count_func2++;
192 func2[tuple<SigBit, SigBit>(A, B)][func].insert(root);
193 }
194
195 if (config.enable_fa && GetSize(leaves) == 3)
196 {
197 leaves.sort();
198
199 SigBit A = SigSpec(leaves)[0];
200 SigBit B = SigSpec(leaves)[1];
201 SigBit C = SigSpec(leaves)[2];
202
203 int func = 0;
204 for (int i = 0; i < 8; i++)
205 {
206 bool a_value = (i & 1) != 0;
207 bool b_value = (i & 2) != 0;
208 bool c_value = (i & 4) != 0;
209
210 ce.push();
211 ce.set(A, a_value ? State::S1 : State::S0);
212 ce.set(B, b_value ? State::S1 : State::S0);
213 ce.set(C, c_value ? State::S1 : State::S0);
214
215 SigSpec sig = root;
216
217 if (!ce.eval(sig))
218 log_abort();
219
220 if (sig == State::S1)
221 func |= 1 << i;
222
223 ce.pop();
224 }
225
226 // log("%08d %s %s %s -> %s\n", bindec(func), log_signal(A), log_signal(B), log_signal(C), log_signal(root));
227
228 if (func == xor3_func || func == xnor3_func)
229 xorxnor3.insert(tuple<SigBit, SigBit, SigBit>(A, B, C));
230
231 count_func3++;
232 func3[tuple<SigBit, SigBit, SigBit>(A, B, C)][func].insert(root);
233 }
234 }
235
236 void find_partitions(SigBit root, pool<SigBit> &leaves, pool<pool<SigBit>> &cache, int maxdepth, int maxbreadth)
237 {
238 if (cache.count(leaves))
239 return;
240
241 // log("%*s[%d] %s:", 20-maxdepth, "", maxdepth, log_signal(root));
242 // for (auto bit : leaves)
243 // log(" %s", log_signal(bit));
244 // log("\n");
245
246 cache.insert(leaves);
247 check_partition(root, leaves);
248
249 if (maxdepth == 0)
250 return;
251
252 for (SigBit bit : leaves)
253 {
254 if (driver.count(bit) == 0)
255 continue;
256
257 Cell *cell = driver.at(bit);
258 pool<SigBit> new_leaves = leaves;
259
260 new_leaves.erase(bit);
261 if (cell->hasPort("\\A")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\A"))));
262 if (cell->hasPort("\\B")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\B"))));
263 if (cell->hasPort("\\C")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\C"))));
264 if (cell->hasPort("\\D")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\D"))));
265
266 if (GetSize(new_leaves) > maxbreadth)
267 continue;
268
269 find_partitions(root, new_leaves, cache, maxdepth-1, maxbreadth);
270 }
271 }
272
273 void assign_new_driver(SigBit bit, SigBit new_driver)
274 {
275 Cell *cell = driver.at(bit);
276 if (sigmap(cell->getPort("\\Y")) == bit) {
277 cell->setPort("\\Y", module->addWire(NEW_ID));
278 module->connect(bit, new_driver);
279 }
280 }
281
282 void run()
283 {
284 log("Extracting full/half adders from %s:\n", log_id(module));
285
286 for (auto it : driver)
287 {
288 if (it.second->type.in("$_BUF_", "$_NOT_"))
289 continue;
290
291 SigBit root = it.first;
292 pool<SigBit> leaves = { root };
293 pool<pool<SigBit>> cache;
294
295 if (config.verbose)
296 log(" checking %s\n", log_signal(it.first));
297
298 count_func2 = 0;
299 count_func3 = 0;
300
301 find_partitions(root, leaves, cache, config.maxdepth, config.maxbreadth);
302
303 if (config.verbose && count_func2 > 0)
304 log(" extracted %d two-input functions\n", count_func2);
305
306 if (config.verbose && count_func3 > 0)
307 log(" extracted %d three-input functions\n", count_func3);
308 }
309
310 for (auto &key : xorxnor3)
311 {
312 SigBit A = get<0>(key);
313 SigBit B = get<1>(key);
314 SigBit C = get<2>(key);
315
316 log(" 3-Input XOR/XNOR %s %s %s:\n", log_signal(A), log_signal(B), log_signal(C));
317
318 for (auto &it : func3.at(key))
319 {
320 if (it.first != xor3_func && it.first != xnor3_func)
321 continue;
322
323 log(" %08d ->", bindec(it.first));
324 for (auto bit : it.second)
325 log(" %s", log_signal(bit));
326 log("\n");
327 }
328
329 dict<int, tuple<SigBit, SigBit, Cell*>> facache;
330
331 for (auto &it : func3_maj_info)
332 {
333 int func = it.first;
334 auto f3i = it.second;
335
336 if (func3.at(key).count(func) == 0)
337 continue;
338
339 if (func3.at(key).count(xor3_func) == 0 && func3.at(key).count(xnor3_func) != 0) {
340 f3i.inv_a = !f3i.inv_a;
341 f3i.inv_b = !f3i.inv_b;
342 f3i.inv_c = !f3i.inv_c;
343 f3i.inv_y = !f3i.inv_y;
344 }
345
346 if (!f3i.inv_a && !f3i.inv_b && !f3i.inv_c && !f3i.inv_y) {
347 log(" Majority without inversions:\n");
348 } else {
349 log(" Majority with inverted");
350 if (f3i.inv_a) log(" A");
351 if (f3i.inv_b) log(" B");
352 if (f3i.inv_c) log(" C");
353 if (f3i.inv_y) log(" Y");
354 log(":\n");
355 }
356
357 log(" %08d ->", bindec(func));
358 for (auto bit : func3.at(key).at(func))
359 log(" %s", log_signal(bit));
360 log("\n");
361
362 int fakey = 0;
363 if (f3i.inv_a) fakey |= 1;
364 if (f3i.inv_b) fakey |= 2;
365 if (f3i.inv_c) fakey |= 4;
366
367 int fakey_inv = fakey ^ 7;
368 bool invert_xy = false;
369 SigBit X, Y;
370
371 if (facache.count(fakey))
372 {
373 auto &fa = facache.at(fakey);
374 X = get<0>(fa);
375 Y = get<1>(fa);
376 log(" Reusing $fa cell %s.\n", log_id(get<2>(fa)));
377 }
378 else
379 if (facache.count(fakey_inv))
380 {
381 auto &fa = facache.at(fakey_inv);
382 invert_xy = true;
383 X = get<0>(fa);
384 Y = get<1>(fa);
385 log(" Reusing $fa cell %s.\n", log_id(get<2>(fa)));
386 }
387 else
388 {
389 Cell *cell = module->addCell(NEW_ID, "$fa");
390 cell->setParam("\\WIDTH", 1);
391
392 log(" Created $fa cell %s.\n", log_id(cell));
393
394 cell->setPort("\\A", f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
395 cell->setPort("\\B", f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
396 cell->setPort("\\C", f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
397
398 X = module->addWire(NEW_ID);
399 Y = module->addWire(NEW_ID);
400
401 cell->setPort("\\X", X);
402 cell->setPort("\\Y", Y);
403
404 facache[fakey] = make_tuple(X, Y, cell);
405 }
406
407 if (func3.at(key).count(xor3_func)) {
408 SigBit YY = invert_xy ? module->NotGate(NEW_ID, Y) : Y;
409 for (auto bit : func3.at(key).at(xor3_func))
410 assign_new_driver(bit, YY);
411 }
412
413 if (func3.at(key).count(xnor3_func)) {
414 SigBit YY = invert_xy ? Y : module->NotGate(NEW_ID, Y);
415 for (auto bit : func3.at(key).at(xnor3_func))
416 assign_new_driver(bit, YY);
417 }
418
419 SigBit XX = invert_xy != f3i.inv_y ? module->NotGate(NEW_ID, X) : X;
420
421 for (auto bit : func3.at(key).at(func))
422 assign_new_driver(bit, XX);
423 }
424 }
425
426 for (auto &key : xorxnor2)
427 {
428 SigBit A = get<0>(key);
429 SigBit B = get<1>(key);
430
431 log(" 2-Input XOR/XNOR %s %s:\n", log_signal(A), log_signal(B));
432
433 for (auto &it : func2.at(key))
434 {
435 if (it.first != xor2_func && it.first != xnor2_func)
436 continue;
437
438 log(" %04d ->", bindec(it.first));
439 for (auto bit : it.second)
440 log(" %s", log_signal(bit));
441 log("\n");
442 }
443
444 dict<int, tuple<SigBit, SigBit, Cell*>> facache;
445
446 for (auto &it : func2_and_info)
447 {
448 int func = it.first;
449 auto &f2i = it.second;
450
451 if (func2.at(key).count(func) == 0)
452 continue;
453
454 if (!f2i.inv_a && !f2i.inv_b && !f2i.inv_y) {
455 log(" AND without inversions:\n");
456 } else {
457 log(" AND with inverted");
458 if (f2i.inv_a) log(" A");
459 if (f2i.inv_b) log(" B");
460 if (f2i.inv_y) log(" Y");
461 log(":\n");
462 }
463
464 log(" %04d ->", bindec(func));
465 for (auto bit : func2.at(key).at(func))
466 log(" %s", log_signal(bit));
467 log("\n");
468
469 int fakey = 0;
470 if (f2i.inv_a) fakey |= 1;
471 if (f2i.inv_b) fakey |= 2;
472
473 int fakey_inv = fakey ^ 3;
474 bool invert_xy = false;
475 SigBit X, Y;
476
477 if (facache.count(fakey))
478 {
479 auto &fa = facache.at(fakey);
480 X = get<0>(fa);
481 Y = get<1>(fa);
482 log(" Reusing $fa cell %s.\n", log_id(get<2>(fa)));
483 }
484 else
485 if (facache.count(fakey_inv))
486 {
487 auto &fa = facache.at(fakey_inv);
488 invert_xy = true;
489 X = get<0>(fa);
490 Y = get<1>(fa);
491 log(" Reusing $fa cell %s.\n", log_id(get<2>(fa)));
492 }
493 else
494 {
495 Cell *cell = module->addCell(NEW_ID, "$fa");
496 cell->setParam("\\WIDTH", 1);
497
498 log(" Created $fa cell %s.\n", log_id(cell));
499
500 cell->setPort("\\A", f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
501 cell->setPort("\\B", f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
502 cell->setPort("\\C", State::S0);
503
504 X = module->addWire(NEW_ID);
505 Y = module->addWire(NEW_ID);
506
507 cell->setPort("\\X", X);
508 cell->setPort("\\Y", Y);
509 }
510
511 if (func2.at(key).count(xor2_func)) {
512 SigBit YY = invert_xy ? module->NotGate(NEW_ID, Y) : Y;
513 for (auto bit : func2.at(key).at(xor2_func))
514 assign_new_driver(bit, YY);
515 }
516
517 if (func2.at(key).count(xnor2_func)) {
518 SigBit YY = invert_xy ? Y : module->NotGate(NEW_ID, Y);
519 for (auto bit : func2.at(key).at(xnor2_func))
520 assign_new_driver(bit, YY);
521 }
522
523 SigBit XX = invert_xy != f2i.inv_y ? module->NotGate(NEW_ID, X) : X;
524
525 for (auto bit : func2.at(key).at(func))
526 assign_new_driver(bit, XX);
527 }
528 }
529 }
530 };
531
532 struct ExtractFaPass : public Pass {
533 ExtractFaPass() : Pass("extract_fa", "find and extract full/half adders") { }
534 virtual void help()
535 {
536 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
537 log("\n");
538 log(" extract_fa [options] [selection]\n");
539 log("\n");
540 log("This pass extracts full/half adders from a gate-level design.\n");
541 log("\n");
542 log(" -fa, -ha\n");
543 log(" Enable cell types (fa=full adder, ha=half adder)\n");
544 log(" All types are enabled if none of this options is used\n");
545 log("\n");
546 log(" -d <int>\n");
547 log(" Set maximum depth for extracted logic cones (default=20)\n");
548 log("\n");
549 log(" -b <int>\n");
550 log(" Set maximum breadth for extracted logic cones (default=6)\n");
551 log("\n");
552 log(" -v\n");
553 log(" Verbose output\n");
554 log("\n");
555 }
556 virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
557 {
558 ExtractFaConfig config;
559
560 log_header(design, "Executing EXTRACT_FA pass (find and extract full/half adders).\n");
561 log_push();
562
563 size_t argidx;
564 for (argidx = 1; argidx < args.size(); argidx++)
565 {
566 if (args[argidx] == "-fa") {
567 config.enable_fa = true;
568 continue;
569 }
570 if (args[argidx] == "-ha") {
571 config.enable_ha = true;
572 continue;
573 }
574 if (args[argidx] == "-v") {
575 config.verbose = true;
576 continue;
577 }
578 if (args[argidx] == "-d" && argidx+2 < args.size()) {
579 config.maxdepth = atoi(args[++argidx].c_str());
580 continue;
581 }
582 if (args[argidx] == "-b" && argidx+2 < args.size()) {
583 config.maxbreadth = atoi(args[++argidx].c_str());
584 continue;
585 }
586 break;
587 }
588 extra_args(args, argidx, design);
589
590 if (!config.enable_fa && !config.enable_ha) {
591 config.enable_fa = true;
592 config.enable_ha = true;
593 }
594
595 for (auto module : design->selected_modules())
596 {
597 ExtractFaWorker worker(config, module);
598 worker.run();
599 }
600
601 log_pop();
602 }
603 } ExtractFaPass;
604
605 PRIVATE_NAMESPACE_END