passes/techmap/extractinv.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *  Copyright (C) 2019  Marcin Kościelnicki <mwk@0x04.net>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 #include "kernel/yosys.h"
  22 #include "kernel/sigtools.h"
  23
  24 USING_YOSYS_NAMESPACE
  25 PRIVATE_NAMESPACE_BEGIN
  26
  27 void split_portname_pair(std::string &port1, std::string &port2)
  28 {
  29         size_t pos = port1.find_first_of(':');
  30         if (pos != std::string::npos) {
  31                 port2 = port1.substr(pos+1);
  32                 port1 = port1.substr(0, pos);
  33         }
  34 }
  35
  36 struct ExtractinvPass : public Pass {
  37         ExtractinvPass() : Pass("extractinv", "extract explicit inverter cells for invertible cell pins") { }
  38         void help() YS_OVERRIDE
  39         {
  40                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  41                 log("\n");
  42                 log("    extractinv [options] [selection]\n");
  43                 log("\n");
  44                 log("Searches the design for all cells with invertible pins controlled by a cell\n");
  45                 log("parameter (eg. IS_CLK_INVERTED on many Xilinx cells) and removes the parameter.\n");
  46                 log("If the parameter was set to 1, inserts an explicit inverter cell in front of\n");
  47                 log("the pin instead.  Normally used for output to ISE, which does not support the\n");
  48                 log("inversion parameters.\n");
  49                 log("\n");
  50                 log("To mark a cell port as invertible, use (* invertible_pin = \"param_name\" *)\n");
  51                 log("on the wire in the blackbox module.  The parameter value should have\n");
  52                 log("the same width as the port, and will be effectively XORed with it.\n");
  53                 log("\n");
  54                 log("    -inv <celltype> <portname_out>:<portname_in>\n");
  55                 log("        Specifies the cell type to use for the inverters and its port names.\n");
  56                 log("        This option is required.\n");
  57                 log("\n");
  58         }
  59
  60         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  61         {
  62                 log_header(design, "Executing EXTRACTINV pass (extracting pin inverters).\n");
  63
  64                 std::string inv_celltype, inv_portname, inv_portname2;
  65
  66                 size_t argidx;
  67                 for (argidx = 1; argidx < args.size(); argidx++)
  68                 {
  69                         std::string arg = args[argidx];
  70                         if (arg == "-inv" && argidx+2 < args.size()) {
  71                                 inv_celltype = args[++argidx];
  72                                 inv_portname = args[++argidx];
  73                                 split_portname_pair(inv_portname, inv_portname2);
  74                                 continue;
  75                         }
  76                         break;
  77                 }
  78                 extra_args(args, argidx, design);
  79
  80                 if (inv_celltype.empty())
  81                         log_error("The -inv option is required.\n");
  82
  83                 for (auto module : design->selected_modules())
  84                 {
  85                         for (auto cell : module->selected_cells())
  86                         for (auto port : cell->connections()) {
  87                                 auto cell_module = design->module(cell->type);
  88                                 if (!cell_module)
  89                                         continue;
  90                                 auto cell_wire = cell_module->wire(port.first);
  91                                 if (!cell_wire)
  92                                         continue;
  93                                 auto it = cell_wire->attributes.find("\\invertible_pin");
  94                                 if (it == cell_wire->attributes.end())
  95                                         continue;
  96                                 IdString param_name = RTLIL::escape_id(it->second.decode_string());
  97                                 auto it2 = cell->parameters.find(param_name);
  98                                 // Inversion not used -- skip.
  99                                 if (it2 == cell->parameters.end())
 100                                         continue;
 101                                 SigSpec sig = port.second;
 102                                 if (it2->second.size() != sig.size())
 103                                         log_error("The inversion parameter needs to be the same width as the port (%s.%s port %s parameter %s)", log_id(module->name), log_id(cell->type), log_id(port.first), log_id(param_name));
 104                                 RTLIL::Const invmask = it2->second;
 105                                 cell->parameters.erase(param_name);
 106                                 if (invmask.is_fully_zero())
 107                                         continue;
 108                                 Wire *iwire = module->addWire(NEW_ID, sig.size());
 109                                 for (int i = 0; i < sig.size(); i++)
 110                                         if (invmask[i] == State::S1) {
 111                                                 RTLIL::Cell *icell = module->addCell(NEW_ID, RTLIL::escape_id(inv_celltype));
 112                                                 icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i));
 113                                                 icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]);
 114                                                 log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype.c_str(), log_id(module), log_id(cell->type), log_id(port.first), i);
 115                                                 sig[i] = SigBit(iwire, i);
 116                                         }
 117                                 cell->setPort(port.first, sig);
 118                         }
 119                 }
 120         }
 121 } ExtractinvPass;
 122
 123 PRIVATE_NAMESPACE_END