passes/techmap/insbuf.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21 #include "kernel/sigtools.h"
  22
  23 USING_YOSYS_NAMESPACE
  24 PRIVATE_NAMESPACE_BEGIN
  25
  26 struct InsbufPass : public Pass {
  27         InsbufPass() : Pass("insbuf", "insert buffer cells for connected wires") { }
  28         void help() YS_OVERRIDE
  29         {
  30                 log("\n");
  31                 log("    insbuf [options] [selection]\n");
  32                 log("\n");
  33                 log("Insert buffer cells into the design for directly connected wires.\n");
  34                 log("\n");
  35                 log("    -buf <celltype> <in-portname> <out-portname>\n");
  36                 log("        Use the given cell type instead of $_BUF_. (Notice that the next\n");
  37                 log("        call to \"clean\" will remove all $_BUF_ in the design.)\n");
  38                 log("\n");
  39         }
  40         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  41         {
  42                 log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n");
  43
  44                 std::string celltype = "$_BUF_", in_portname = "\\A", out_portname = "\\Y";
  45
  46                 size_t argidx;
  47                 for (argidx = 1; argidx < args.size(); argidx++)
  48                 {
  49                         std::string arg = args[argidx];
  50                         if (arg == "-buf" && argidx+3 < args.size()) {
  51                                 celltype = args[++argidx];
  52                                 in_portname = args[++argidx];
  53                                 out_portname = args[++argidx];
  54                                 continue;
  55                         }
  56                         break;
  57                 }
  58                 extra_args(args, argidx, design);
  59
  60                 for (auto module : design->selected_modules())
  61                 {
  62                         std::vector<RTLIL::SigSig> new_connections;
  63
  64                         for (auto &conn : module->connections())
  65                         {
  66                                 RTLIL::SigSig new_conn;
  67
  68                                 for (int i = 0; i < GetSize(conn.first); i++)
  69                                 {
  70                                         SigBit lhs = conn.first[i];
  71                                         SigBit rhs = conn.second[i];
  72
  73                                         if (lhs.wire && !design->selected(module, lhs.wire)) {
  74                                                 new_conn.first.append(lhs);
  75                                                 new_conn.second.append(rhs);
  76                                                 continue;
  77                                         }
  78
  79                                         Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
  80                                         cell->setPort(RTLIL::escape_id(in_portname), rhs);
  81                                         cell->setPort(RTLIL::escape_id(out_portname), lhs);
  82                                         log("Added %s.%s: %s -> %s\n", log_id(module), log_id(cell), log_signal(rhs), log_signal(lhs));
  83                                 }
  84
  85                                 if (GetSize(new_conn.first))
  86                                         new_connections.push_back(new_conn);
  87                         }
  88
  89                         module->new_connections(new_connections);
  90                 }
  91         }
  92 } InsbufPass;
  93
  94 PRIVATE_NAMESPACE_END