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abc9_ops: still emit delay table even box has no timing
[yosys.git] / passes / techmap / iopadmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22
23 USING_YOSYS_NAMESPACE
24 PRIVATE_NAMESPACE_BEGIN
25
26 void split_portname_pair(std::string &port1, std::string &port2)
27 {
28 size_t pos = port1.find_first_of(':');
29 if (pos != std::string::npos) {
30 port2 = port1.substr(pos+1);
31 port1 = port1.substr(0, pos);
32 }
33 }
34
35 struct IopadmapPass : public Pass {
36 IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { }
37 void help() YS_OVERRIDE
38 {
39 log("\n");
40 log(" iopadmap [options] [selection]\n");
41 log("\n");
42 log("Map module inputs/outputs to PAD cells from a library. This pass\n");
43 log("can only map to very simple PAD cells. Use 'techmap' to further map\n");
44 log("the resulting cells to more sophisticated PAD cells.\n");
45 log("\n");
46 log(" -inpad <celltype> <portname>[:<portname>]\n");
47 log(" Map module input ports to the given cell type with the\n");
48 log(" given output port name. if a 2nd portname is given, the\n");
49 log(" signal is passed through the pad call, using the 2nd\n");
50 log(" portname as the port facing the module port.\n");
51 log("\n");
52 log(" -outpad <celltype> <portname>[:<portname>]\n");
53 log(" -inoutpad <celltype> <portname>[:<portname>]\n");
54 log(" Similar to -inpad, but for output and inout ports.\n");
55 log("\n");
56 log(" -toutpad <celltype> <portname>:<portname>[:<portname>]\n");
57 log(" Merges $_TBUF_ cells into the output pad cell. This takes precedence\n");
58 log(" over the other -outpad cell. The first portname is the enable input\n");
59 log(" of the tristate driver.\n");
60 log("\n");
61 log(" -tinoutpad <celltype> <portname>:<portname>:<portname>[:<portname>]\n");
62 log(" Merges $_TBUF_ cells into the inout pad cell. This takes precedence\n");
63 log(" over the other -inoutpad cell. The first portname is the enable input\n");
64 log(" of the tristate driver and the 2nd portname is the internal output\n");
65 log(" buffering the external signal.\n");
66 log("\n");
67 log(" -ignore <celltype> <portname>[:<portname>]*\n");
68 log(" Skips mapping inputs/outputs that are already connected to given\n");
69 log(" ports of the given cell. Can be used multiple times. This is in\n");
70 log(" addition to the cells specified as mapping targets.\n");
71 log("\n");
72 log(" -widthparam <param_name>\n");
73 log(" Use the specified parameter name to set the port width.\n");
74 log("\n");
75 log(" -nameparam <param_name>\n");
76 log(" Use the specified parameter to set the port name.\n");
77 log("\n");
78 log(" -bits\n");
79 log(" create individual bit-wide buffers even for ports that\n");
80 log(" are wider. (the default behavior is to create word-wide\n");
81 log(" buffers using -widthparam to set the word size on the cell.)\n");
82 log("\n");
83 log("Tristate PADS (-toutpad, -tinoutpad) always operate in -bits mode.\n");
84 log("\n");
85 }
86 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
87 {
88 log_header(design, "Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
89
90 std::string inpad_celltype, inpad_portname_o, inpad_portname_pad;
91 std::string outpad_celltype, outpad_portname_i, outpad_portname_pad;
92 std::string inoutpad_celltype, inoutpad_portname_io, inoutpad_portname_pad;
93 std::string toutpad_celltype, toutpad_portname_oe, toutpad_portname_i, toutpad_portname_pad;
94 std::string tinoutpad_celltype, tinoutpad_portname_oe, tinoutpad_portname_o, tinoutpad_portname_i, tinoutpad_portname_pad;
95 std::string widthparam, nameparam;
96 pool<pair<IdString, IdString>> ignore;
97 bool flag_bits = false;
98
99 size_t argidx;
100 for (argidx = 1; argidx < args.size(); argidx++)
101 {
102 std::string arg = args[argidx];
103 if (arg == "-inpad" && argidx+2 < args.size()) {
104 inpad_celltype = args[++argidx];
105 inpad_portname_o = args[++argidx];
106 split_portname_pair(inpad_portname_o, inpad_portname_pad);
107 continue;
108 }
109 if (arg == "-outpad" && argidx+2 < args.size()) {
110 outpad_celltype = args[++argidx];
111 outpad_portname_i = args[++argidx];
112 split_portname_pair(outpad_portname_i, outpad_portname_pad);
113 continue;
114 }
115 if (arg == "-inoutpad" && argidx+2 < args.size()) {
116 inoutpad_celltype = args[++argidx];
117 inoutpad_portname_io = args[++argidx];
118 split_portname_pair(inoutpad_portname_io, inoutpad_portname_pad);
119 continue;
120 }
121 if (arg == "-toutpad" && argidx+2 < args.size()) {
122 toutpad_celltype = args[++argidx];
123 toutpad_portname_oe = args[++argidx];
124 split_portname_pair(toutpad_portname_oe, toutpad_portname_i);
125 split_portname_pair(toutpad_portname_i, toutpad_portname_pad);
126 continue;
127 }
128 if (arg == "-tinoutpad" && argidx+2 < args.size()) {
129 tinoutpad_celltype = args[++argidx];
130 tinoutpad_portname_oe = args[++argidx];
131 split_portname_pair(tinoutpad_portname_oe, tinoutpad_portname_o);
132 split_portname_pair(tinoutpad_portname_o, tinoutpad_portname_i);
133 split_portname_pair(tinoutpad_portname_i, tinoutpad_portname_pad);
134 continue;
135 }
136 if (arg == "-ignore" && argidx+2 < args.size()) {
137 std::string ignore_celltype = args[++argidx];
138 std::string ignore_portname = args[++argidx];
139 std::string ignore_portname2;
140 while (!ignore_portname.empty()) {
141 split_portname_pair(ignore_portname, ignore_portname2);
142 ignore.insert(make_pair(RTLIL::escape_id(ignore_celltype), RTLIL::escape_id(ignore_portname)));
143
144 ignore_portname = ignore_portname2;
145 }
146 continue;
147 }
148 if (arg == "-widthparam" && argidx+1 < args.size()) {
149 widthparam = args[++argidx];
150 continue;
151 }
152 if (arg == "-nameparam" && argidx+1 < args.size()) {
153 nameparam = args[++argidx];
154 continue;
155 }
156 if (arg == "-bits") {
157 flag_bits = true;
158 continue;
159 }
160 break;
161 }
162 extra_args(args, argidx, design);
163
164 if (!inpad_portname_pad.empty())
165 ignore.insert(make_pair(RTLIL::escape_id(inpad_celltype), RTLIL::escape_id(inpad_portname_pad)));
166 if (!outpad_portname_pad.empty())
167 ignore.insert(make_pair(RTLIL::escape_id(outpad_celltype), RTLIL::escape_id(outpad_portname_pad)));
168 if (!inoutpad_portname_pad.empty())
169 ignore.insert(make_pair(RTLIL::escape_id(inoutpad_celltype), RTLIL::escape_id(inoutpad_portname_pad)));
170 if (!toutpad_portname_pad.empty())
171 ignore.insert(make_pair(RTLIL::escape_id(toutpad_celltype), RTLIL::escape_id(toutpad_portname_pad)));
172 if (!tinoutpad_portname_pad.empty())
173 ignore.insert(make_pair(RTLIL::escape_id(tinoutpad_celltype), RTLIL::escape_id(tinoutpad_portname_pad)));
174
175 for (auto module : design->modules())
176 if (module->get_blackbox_attribute())
177 for (auto wire : module->wires())
178 if (wire->get_bool_attribute("\\iopad_external_pin"))
179 ignore.insert(make_pair(module->name, wire->name));
180
181 for (auto module : design->selected_modules())
182 {
183 pool<SigBit> skip_wire_bits;
184 dict<Wire *, dict<int, pair<Cell *, IdString>>> rewrite_bits;
185
186 for (auto cell : module->cells())
187 for (auto port : cell->connections())
188 if (ignore.count(make_pair(cell->type, port.first)))
189 for (auto bit : port.second)
190 skip_wire_bits.insert(bit);
191
192 if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
193 {
194 dict<SigBit, Cell *> tbuf_bits;
195 pool<SigBit> driven_bits;
196
197 // Gather tristate buffers and always-on drivers.
198 for (auto cell : module->cells())
199 if (cell->type == ID($_TBUF_)) {
200 SigBit bit = cell->getPort(ID::Y).as_bit();
201 tbuf_bits[bit] = cell;
202 } else {
203 for (auto port : cell->connections())
204 if (!cell->known() || cell->output(port.first))
205 for (auto bit : port.second)
206 driven_bits.insert(bit);
207 }
208
209 // If a wire is a target of an assignment, it is driven, unless the source is 'z.
210 for (auto &conn : module->connections())
211 for (int i = 0; i < GetSize(conn.first); i++) {
212 SigBit dstbit = conn.first[i];
213 SigBit srcbit = conn.second[i];
214 if (!srcbit.wire && srcbit.data == State::Sz)
215 continue;
216 driven_bits.insert(dstbit);
217 }
218
219 for (auto wire : module->selected_wires())
220 {
221 if (!wire->port_output)
222 continue;
223
224 // Don't handle inout ports if we have no suitable buffer type.
225 if (wire->port_input && tinoutpad_celltype.empty())
226 continue;
227
228 // likewise for output ports.
229 if (!wire->port_input && toutpad_celltype.empty())
230 continue;
231
232 for (int i = 0; i < GetSize(wire); i++)
233 {
234 SigBit wire_bit(wire, i);
235 Cell *tbuf_cell = nullptr;
236
237 if (skip_wire_bits.count(wire_bit))
238 continue;
239
240 if (tbuf_bits.count(wire_bit))
241 tbuf_cell = tbuf_bits.at(wire_bit);
242
243 SigBit en_sig;
244 SigBit data_sig;
245 bool is_driven = driven_bits.count(wire_bit);
246
247 if (tbuf_cell != nullptr) {
248 // Found a tristate buffer — use it.
249 en_sig = tbuf_cell->getPort(ID(E)).as_bit();
250 data_sig = tbuf_cell->getPort(ID::A).as_bit();
251 } else if (is_driven) {
252 // No tristate buffer, but an always-on driver is present.
253 // If this is an inout port, we're creating a tinoutpad
254 // anyway, just with a constant 1 as enable.
255 if (!wire->port_input)
256 continue;
257 en_sig = SigBit(State::S1);
258 data_sig = wire_bit;
259 } else {
260 // No driver on a wire. Create a tristate pad with always-0
261 // enable.
262 en_sig = SigBit(State::S0);
263 data_sig = SigBit(State::Sx);
264 }
265
266 if (wire->port_input)
267 {
268 log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype.c_str());
269
270 Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(tinoutpad_celltype));
271
272 cell->setPort(RTLIL::escape_id(tinoutpad_portname_oe), en_sig);
273 cell->attributes[ID::keep] = RTLIL::Const(1);
274
275 if (tbuf_cell) {
276 module->remove(tbuf_cell);
277 cell->setPort(RTLIL::escape_id(tinoutpad_portname_o), wire_bit);
278 cell->setPort(RTLIL::escape_id(tinoutpad_portname_i), data_sig);
279 } else if (is_driven) {
280 cell->setPort(RTLIL::escape_id(tinoutpad_portname_i), wire_bit);
281 } else {
282 cell->setPort(RTLIL::escape_id(tinoutpad_portname_o), wire_bit);
283 cell->setPort(RTLIL::escape_id(tinoutpad_portname_i), data_sig);
284 }
285 skip_wire_bits.insert(wire_bit);
286 if (!tinoutpad_portname_pad.empty())
287 rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(tinoutpad_portname_pad));
288 } else {
289 log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype.c_str());
290
291 Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(toutpad_celltype));
292
293 cell->setPort(RTLIL::escape_id(toutpad_portname_oe), en_sig);
294 cell->setPort(RTLIL::escape_id(toutpad_portname_i), data_sig);
295 cell->attributes[ID::keep] = RTLIL::Const(1);
296
297 if (tbuf_cell) {
298 module->remove(tbuf_cell);
299 module->connect(wire_bit, data_sig);
300 }
301 skip_wire_bits.insert(wire_bit);
302 if (!toutpad_portname_pad.empty())
303 rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(toutpad_portname_pad));
304 }
305 }
306 }
307 }
308
309 for (auto wire : module->selected_wires())
310 {
311 if (!wire->port_id)
312 continue;
313
314 std::string celltype, portname_int, portname_pad;
315 pool<int> skip_bit_indices;
316
317 for (int i = 0; i < GetSize(wire); i++)
318 if (skip_wire_bits.count(SigBit(wire, i)))
319 skip_bit_indices.insert(i);
320
321 if (GetSize(wire) == GetSize(skip_bit_indices))
322 continue;
323
324 if (wire->port_input && !wire->port_output) {
325 if (inpad_celltype.empty()) {
326 log("Don't map input port %s.%s: Missing option -inpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
327 continue;
328 }
329 celltype = inpad_celltype;
330 portname_int = inpad_portname_o;
331 portname_pad = inpad_portname_pad;
332 } else
333 if (!wire->port_input && wire->port_output) {
334 if (outpad_celltype.empty()) {
335 log("Don't map output port %s.%s: Missing option -outpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
336 continue;
337 }
338 celltype = outpad_celltype;
339 portname_int = outpad_portname_i;
340 portname_pad = outpad_portname_pad;
341 } else
342 if (wire->port_input && wire->port_output) {
343 if (inoutpad_celltype.empty()) {
344 log("Don't map inout port %s.%s: Missing option -inoutpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
345 continue;
346 }
347 celltype = inoutpad_celltype;
348 portname_int = inoutpad_portname_io;
349 portname_pad = inoutpad_portname_pad;
350 } else
351 log_abort();
352
353 if (!flag_bits && wire->width != 1 && widthparam.empty()) {
354 log("Don't map multi-bit port %s.%s: Missing option -widthparam or -bits.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
355 continue;
356 }
357
358 log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str());
359
360 if (flag_bits)
361 {
362 for (int i = 0; i < wire->width; i++)
363 {
364 if (skip_bit_indices.count(i))
365 continue;
366
367 SigBit wire_bit(wire, i);
368
369 RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
370 cell->setPort(RTLIL::escape_id(portname_int), wire_bit);
371
372 if (!portname_pad.empty())
373 rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(portname_pad));
374 if (!widthparam.empty())
375 cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
376 if (!nameparam.empty())
377 cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i));
378 cell->attributes[ID::keep] = RTLIL::Const(1);
379 }
380 }
381 else
382 {
383 RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
384 cell->setPort(RTLIL::escape_id(portname_int), RTLIL::SigSpec(wire));
385
386 if (!portname_pad.empty()) {
387 RTLIL::Wire *new_wire = NULL;
388 new_wire = module->addWire(NEW_ID, wire);
389 module->swap_names(new_wire, wire);
390 wire->attributes.clear();
391 cell->setPort(RTLIL::escape_id(portname_pad), RTLIL::SigSpec(new_wire));
392 }
393 if (!widthparam.empty())
394 cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
395 if (!nameparam.empty())
396 cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
397 cell->attributes[ID::keep] = RTLIL::Const(1);
398 }
399
400 if (!rewrite_bits.count(wire)) {
401 wire->port_id = 0;
402 wire->port_input = false;
403 wire->port_output = false;
404 }
405 }
406
407 for (auto &it : rewrite_bits) {
408 RTLIL::Wire *wire = it.first;
409 RTLIL::Wire *new_wire = module->addWire(NEW_ID, wire);
410 module->swap_names(new_wire, wire);
411 wire->attributes.clear();
412 for (int i = 0; i < wire->width; i++)
413 {
414 SigBit wire_bit(wire, i);
415 if (!it.second.count(i)) {
416 if (wire->port_output)
417 module->connect(SigSpec(new_wire, i), SigSpec(wire, i));
418 else
419 module->connect(SigSpec(wire, i), SigSpec(new_wire, i));
420 } else {
421 auto &new_conn = it.second.at(i);
422 new_conn.first->setPort(new_conn.second, RTLIL::SigSpec(new_wire, i));
423 }
424 }
425
426 if (wire->port_output) {
427 auto jt = new_wire->attributes.find(ID(init));
428 // For output ports, move \init attributes from old wire to new wire
429 if (jt != new_wire->attributes.end()) {
430 wire->attributes[ID(init)] = std::move(jt->second);
431 new_wire->attributes.erase(jt);
432 }
433 }
434
435 wire->port_id = 0;
436 wire->port_input = false;
437 wire->port_output = false;
438 }
439
440 module->fixup_ports();
441 }
442 }
443 } IopadmapPass;
444
445 PRIVATE_NAMESPACE_END