2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
24 PRIVATE_NAMESPACE_BEGIN
26 void split_portname_pair(std::string
&port1
, std::string
&port2
)
28 size_t pos
= port1
.find_first_of(':');
29 if (pos
!= std::string::npos
) {
30 port2
= port1
.substr(pos
+1);
31 port1
= port1
.substr(0, pos
);
35 struct IopadmapPass
: public Pass
{
36 IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { }
37 void help() YS_OVERRIDE
40 log(" iopadmap [options] [selection]\n");
42 log("Map module inputs/outputs to PAD cells from a library. This pass\n");
43 log("can only map to very simple PAD cells. Use 'techmap' to further map\n");
44 log("the resulting cells to more sophisticated PAD cells.\n");
46 log(" -inpad <celltype> <portname>[:<portname>]\n");
47 log(" Map module input ports to the given cell type with the\n");
48 log(" given output port name. if a 2nd portname is given, the\n");
49 log(" signal is passed through the pad call, using the 2nd\n");
50 log(" portname as the port facing the module port.\n");
52 log(" -outpad <celltype> <portname>[:<portname>]\n");
53 log(" -inoutpad <celltype> <portname>[:<portname>]\n");
54 log(" Similar to -inpad, but for output and inout ports.\n");
56 log(" -toutpad <celltype> <portname>:<portname>[:<portname>]\n");
57 log(" Merges $_TBUF_ cells into the output pad cell. This takes precedence\n");
58 log(" over the other -outpad cell. The first portname is the enable input\n");
59 log(" of the tristate driver.\n");
61 log(" -tinoutpad <celltype> <portname>:<portname>:<portname>[:<portname>]\n");
62 log(" Merges $_TBUF_ cells into the inout pad cell. This takes precedence\n");
63 log(" over the other -inoutpad cell. The first portname is the enable input\n");
64 log(" of the tristate driver and the 2nd portname is the internal output\n");
65 log(" buffering the external signal.\n");
67 log(" -ignore <celltype> <portname>[:<portname>]*\n");
68 log(" Skips mapping inputs/outputs that are already connected to given\n");
69 log(" ports of the given cell. Can be used multiple times. This is in\n");
70 log(" addition to the cells specified as mapping targets.\n");
72 log(" -widthparam <param_name>\n");
73 log(" Use the specified parameter name to set the port width.\n");
75 log(" -nameparam <param_name>\n");
76 log(" Use the specified parameter to set the port name.\n");
79 log(" create individual bit-wide buffers even for ports that\n");
80 log(" are wider. (the default behavior is to create word-wide\n");
81 log(" buffers using -widthparam to set the word size on the cell.)\n");
83 log("Tristate PADS (-toutpad, -tinoutpad) always operate in -bits mode.\n");
86 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
88 log_header(design
, "Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
90 std::string inpad_celltype
, inpad_portname
, inpad_portname2
;
91 std::string outpad_celltype
, outpad_portname
, outpad_portname2
;
92 std::string inoutpad_celltype
, inoutpad_portname
, inoutpad_portname2
;
93 std::string toutpad_celltype
, toutpad_portname
, toutpad_portname2
, toutpad_portname3
;
94 std::string tinoutpad_celltype
, tinoutpad_portname
, tinoutpad_portname2
, tinoutpad_portname3
, tinoutpad_portname4
;
95 std::string widthparam
, nameparam
;
96 pool
<pair
<IdString
, IdString
>> ignore
;
97 bool flag_bits
= false;
100 for (argidx
= 1; argidx
< args
.size(); argidx
++)
102 std::string arg
= args
[argidx
];
103 if (arg
== "-inpad" && argidx
+2 < args
.size()) {
104 inpad_celltype
= args
[++argidx
];
105 inpad_portname
= args
[++argidx
];
106 split_portname_pair(inpad_portname
, inpad_portname2
);
109 if (arg
== "-outpad" && argidx
+2 < args
.size()) {
110 outpad_celltype
= args
[++argidx
];
111 outpad_portname
= args
[++argidx
];
112 split_portname_pair(outpad_portname
, outpad_portname2
);
115 if (arg
== "-inoutpad" && argidx
+2 < args
.size()) {
116 inoutpad_celltype
= args
[++argidx
];
117 inoutpad_portname
= args
[++argidx
];
118 split_portname_pair(inoutpad_portname
, inoutpad_portname2
);
121 if (arg
== "-toutpad" && argidx
+2 < args
.size()) {
122 toutpad_celltype
= args
[++argidx
];
123 toutpad_portname
= args
[++argidx
];
124 split_portname_pair(toutpad_portname
, toutpad_portname2
);
125 split_portname_pair(toutpad_portname2
, toutpad_portname3
);
128 if (arg
== "-tinoutpad" && argidx
+2 < args
.size()) {
129 tinoutpad_celltype
= args
[++argidx
];
130 tinoutpad_portname
= args
[++argidx
];
131 split_portname_pair(tinoutpad_portname
, tinoutpad_portname2
);
132 split_portname_pair(tinoutpad_portname2
, tinoutpad_portname3
);
133 split_portname_pair(tinoutpad_portname3
, tinoutpad_portname4
);
136 if (arg
== "-ignore" && argidx
+2 < args
.size()) {
137 std::string ignore_celltype
= args
[++argidx
];
138 std::string ignore_portname
= args
[++argidx
];
139 std::string ignore_portname2
;
140 while (!ignore_portname
.empty()) {
141 split_portname_pair(ignore_portname
, ignore_portname2
);
142 ignore
.insert(make_pair(RTLIL::escape_id(ignore_celltype
), RTLIL::escape_id(ignore_portname
)));
144 ignore_portname
= ignore_portname2
;
148 if (arg
== "-widthparam" && argidx
+1 < args
.size()) {
149 widthparam
= args
[++argidx
];
152 if (arg
== "-nameparam" && argidx
+1 < args
.size()) {
153 nameparam
= args
[++argidx
];
156 if (arg
== "-bits") {
162 extra_args(args
, argidx
, design
);
164 if (!inpad_portname2
.empty())
165 ignore
.insert(make_pair(RTLIL::escape_id(inpad_celltype
), RTLIL::escape_id(inpad_portname2
)));
166 if (!outpad_portname2
.empty())
167 ignore
.insert(make_pair(RTLIL::escape_id(outpad_celltype
), RTLIL::escape_id(outpad_portname2
)));
168 if (!inoutpad_portname2
.empty())
169 ignore
.insert(make_pair(RTLIL::escape_id(inoutpad_celltype
), RTLIL::escape_id(inoutpad_portname2
)));
170 if (!toutpad_portname3
.empty())
171 ignore
.insert(make_pair(RTLIL::escape_id(toutpad_celltype
), RTLIL::escape_id(toutpad_portname3
)));
172 if (!tinoutpad_portname4
.empty())
173 ignore
.insert(make_pair(RTLIL::escape_id(tinoutpad_celltype
), RTLIL::escape_id(tinoutpad_portname4
)));
175 for (auto module
: design
->modules())
176 if (module
->get_blackbox_attribute())
177 for (auto wire
: module
->wires())
178 if (wire
->get_bool_attribute("\\iopad_external_pin"))
179 ignore
.insert(make_pair(module
->name
, wire
->name
));
181 for (auto module
: design
->selected_modules())
183 dict
<IdString
, pool
<int>> skip_wires
;
184 pool
<SigBit
> skip_wire_bits
;
185 SigMap
sigmap(module
);
187 for (auto cell
: module
->cells())
188 for (auto port
: cell
->connections())
189 if (ignore
.count(make_pair(cell
->type
, port
.first
)))
190 for (auto bit
: sigmap(port
.second
))
191 skip_wire_bits
.insert(bit
);
193 if (!toutpad_celltype
.empty() || !tinoutpad_celltype
.empty())
195 dict
<SigBit
, pair
<IdString
, pool
<IdString
>>> tbuf_bits
;
196 pool
<pair
<IdString
, IdString
>> norewrites
;
199 for (auto cell
: module
->cells())
200 if (cell
->type
== "$_TBUF_") {
201 SigBit bit
= sigmap(cell
->getPort("\\Y").as_bit());
202 tbuf_bits
[bit
].first
= cell
->name
;
205 for (auto cell
: module
->cells())
206 for (auto port
: cell
->connections())
207 for (auto bit
: sigmap(port
.second
))
208 if (tbuf_bits
.count(bit
))
209 tbuf_bits
.at(bit
).second
.insert(cell
->name
);
211 for (auto wire
: module
->selected_wires())
213 if (!wire
->port_output
)
216 for (int i
= 0; i
< GetSize(wire
); i
++)
218 SigBit
wire_bit(wire
, i
);
219 SigBit mapped_wire_bit
= sigmap(wire_bit
);
221 if (tbuf_bits
.count(mapped_wire_bit
) == 0)
224 if (skip_wire_bits
.count(mapped_wire_bit
))
227 auto &tbuf_cache
= tbuf_bits
.at(mapped_wire_bit
);
228 Cell
*tbuf_cell
= module
->cell(tbuf_cache
.first
);
230 if (tbuf_cell
== nullptr)
233 SigBit en_sig
= tbuf_cell
->getPort("\\E").as_bit();
234 SigBit data_sig
= tbuf_cell
->getPort("\\A").as_bit();
236 if (wire
->port_input
&& !tinoutpad_celltype
.empty())
238 log("Mapping port %s.%s[%d] using %s.\n", log_id(module
), log_id(wire
), i
, tinoutpad_celltype
.c_str());
240 Cell
*cell
= module
->addCell(NEW_ID
, RTLIL::escape_id(tinoutpad_celltype
));
241 Wire
*owire
= module
->addWire(NEW_ID
);
243 cell
->setPort(RTLIL::escape_id(tinoutpad_portname
), en_sig
);
244 cell
->setPort(RTLIL::escape_id(tinoutpad_portname2
), owire
);
245 cell
->setPort(RTLIL::escape_id(tinoutpad_portname3
), data_sig
);
246 cell
->setPort(RTLIL::escape_id(tinoutpad_portname4
), wire_bit
);
247 cell
->attributes
["\\keep"] = RTLIL::Const(1);
249 for (auto cn
: tbuf_cache
.second
) {
250 auto c
= module
->cell(cn
);
253 for (auto port
: c
->connections()) {
254 SigSpec sig
= port
.second
;
256 for (auto &bit
: sig
)
257 if (sigmap(bit
) == mapped_wire_bit
) {
262 c
->setPort(port
.first
, sig
);
267 module
->remove(tbuf_cell
);
268 skip_wires
[wire
->name
].insert(i
);
270 norewrites
.insert(make_pair(cell
->name
, RTLIL::escape_id(tinoutpad_portname4
)));
271 rewrites
.add(sigmap(wire_bit
), owire
);
275 if (!wire
->port_input
&& !toutpad_celltype
.empty())
277 log("Mapping port %s.%s[%d] using %s.\n", log_id(module
), log_id(wire
), i
, toutpad_celltype
.c_str());
279 Cell
*cell
= module
->addCell(NEW_ID
, RTLIL::escape_id(toutpad_celltype
));
281 cell
->setPort(RTLIL::escape_id(toutpad_portname
), en_sig
);
282 cell
->setPort(RTLIL::escape_id(toutpad_portname2
), data_sig
);
283 cell
->setPort(RTLIL::escape_id(toutpad_portname3
), wire_bit
);
284 cell
->attributes
["\\keep"] = RTLIL::Const(1);
286 for (auto cn
: tbuf_cache
.second
) {
287 auto c
= module
->cell(cn
);
290 for (auto port
: c
->connections()) {
291 SigSpec sig
= port
.second
;
293 for (auto &bit
: sig
)
294 if (sigmap(bit
) == mapped_wire_bit
) {
299 c
->setPort(port
.first
, sig
);
303 module
->remove(tbuf_cell
);
304 skip_wires
[wire
->name
].insert(i
);
310 if (GetSize(norewrites
))
312 for (auto cell
: module
->cells())
313 for (auto port
: cell
->connections())
315 if (norewrites
.count(make_pair(cell
->name
, port
.first
)))
318 SigSpec orig_sig
= sigmap(port
.second
);
319 SigSpec new_sig
= rewrites(orig_sig
);
321 if (orig_sig
!= new_sig
)
322 cell
->setPort(port
.first
, new_sig
);
327 for (auto wire
: module
->selected_wires())
332 std::string celltype
, portname
, portname2
;
333 pool
<int> skip_bit_indices
;
335 if (skip_wires
.count(wire
->name
)) {
338 skip_bit_indices
= skip_wires
.at(wire
->name
);
341 for (int i
= 0; i
< GetSize(wire
); i
++)
342 if (skip_wire_bits
.count(sigmap(SigBit(wire
, i
))))
343 skip_bit_indices
.insert(i
);
345 if (GetSize(wire
) == GetSize(skip_bit_indices
))
348 if (wire
->port_input
&& !wire
->port_output
) {
349 if (inpad_celltype
.empty()) {
350 log("Don't map input port %s.%s: Missing option -inpad.\n", RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(wire
->name
));
353 celltype
= inpad_celltype
;
354 portname
= inpad_portname
;
355 portname2
= inpad_portname2
;
357 if (!wire
->port_input
&& wire
->port_output
) {
358 if (outpad_celltype
.empty()) {
359 log("Don't map output port %s.%s: Missing option -outpad.\n", RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(wire
->name
));
362 celltype
= outpad_celltype
;
363 portname
= outpad_portname
;
364 portname2
= outpad_portname2
;
366 if (wire
->port_input
&& wire
->port_output
) {
367 if (inoutpad_celltype
.empty()) {
368 log("Don't map inout port %s.%s: Missing option -inoutpad.\n", RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(wire
->name
));
371 celltype
= inoutpad_celltype
;
372 portname
= inoutpad_portname
;
373 portname2
= inoutpad_portname2
;
377 if (!flag_bits
&& wire
->width
!= 1 && widthparam
.empty()) {
378 log("Don't map multi-bit port %s.%s: Missing option -widthparam or -bits.\n", RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(wire
->name
));
382 log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(wire
->name
), celltype
.c_str());
384 RTLIL::Wire
*new_wire
= NULL
;
385 if (!portname2
.empty()) {
386 new_wire
= module
->addWire(NEW_ID
, wire
);
387 module
->swap_names(new_wire
, wire
);
388 wire
->attributes
.clear();
393 for (int i
= 0; i
< wire
->width
; i
++)
395 if (skip_bit_indices
.count(i
)) {
396 if (wire
->port_output
)
397 module
->connect(SigSpec(new_wire
, i
), SigSpec(wire
, i
));
399 module
->connect(SigSpec(wire
, i
), SigSpec(new_wire
, i
));
403 RTLIL::Cell
*cell
= module
->addCell(NEW_ID
, RTLIL::escape_id(celltype
));
404 cell
->setPort(RTLIL::escape_id(portname
), RTLIL::SigSpec(wire
, i
));
405 if (!portname2
.empty())
406 cell
->setPort(RTLIL::escape_id(portname2
), RTLIL::SigSpec(new_wire
, i
));
407 if (!widthparam
.empty())
408 cell
->parameters
[RTLIL::escape_id(widthparam
)] = RTLIL::Const(1);
409 if (!nameparam
.empty())
410 cell
->parameters
[RTLIL::escape_id(nameparam
)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire
->name
), i
));
411 cell
->attributes
["\\keep"] = RTLIL::Const(1);
416 RTLIL::Cell
*cell
= module
->addCell(NEW_ID
, RTLIL::escape_id(celltype
));
417 cell
->setPort(RTLIL::escape_id(portname
), RTLIL::SigSpec(wire
));
418 if (!portname2
.empty())
419 cell
->setPort(RTLIL::escape_id(portname2
), RTLIL::SigSpec(new_wire
));
420 if (!widthparam
.empty())
421 cell
->parameters
[RTLIL::escape_id(widthparam
)] = RTLIL::Const(wire
->width
);
422 if (!nameparam
.empty())
423 cell
->parameters
[RTLIL::escape_id(nameparam
)] = RTLIL::Const(RTLIL::id2cstr(wire
->name
));
424 cell
->attributes
["\\keep"] = RTLIL::Const(1);
428 wire
->port_input
= false;
429 wire
->port_output
= false;
432 module
->fixup_ports();
437 PRIVATE_NAMESPACE_END