2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
24 PRIVATE_NAMESPACE_BEGIN
26 void split_portname_pair(std::string
&port1
, std::string
&port2
)
28 size_t pos
= port1
.find_first_of(':');
29 if (pos
!= std::string::npos
) {
30 port2
= port1
.substr(pos
+1);
31 port1
= port1
.substr(0, pos
);
35 struct IopadmapPass
: public Pass
{
36 IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { }
37 void help() YS_OVERRIDE
40 log(" iopadmap [options] [selection]\n");
42 log("Map module inputs/outputs to PAD cells from a library. This pass\n");
43 log("can only map to very simple PAD cells. Use 'techmap' to further map\n");
44 log("the resulting cells to more sophisticated PAD cells.\n");
46 log(" -inpad <celltype> <portname>[:<portname>]\n");
47 log(" Map module input ports to the given cell type with the\n");
48 log(" given output port name. if a 2nd portname is given, the\n");
49 log(" signal is passed through the pad call, using the 2nd\n");
50 log(" portname as the port facing the module port.\n");
52 log(" -outpad <celltype> <portname>[:<portname>]\n");
53 log(" -inoutpad <celltype> <portname>[:<portname>]\n");
54 log(" Similar to -inpad, but for output and inout ports.\n");
56 log(" -toutpad <celltype> <portname>:<portname>[:<portname>]\n");
57 log(" Merges $_TBUF_ cells into the output pad cell. This takes precedence\n");
58 log(" over the other -outpad cell. The first portname is the enable input\n");
59 log(" of the tristate driver.\n");
61 log(" -tinoutpad <celltype> <portname>:<portname>:<portname>[:<portname>]\n");
62 log(" Merges $_TBUF_ cells into the inout pad cell. This takes precedence\n");
63 log(" over the other -inoutpad cell. The first portname is the enable input\n");
64 log(" of the tristate driver and the 2nd portname is the internal output\n");
65 log(" buffering the external signal.\n");
67 log(" -ignore <celltype> <portname>[:<portname>]*\n");
68 log(" Skips mapping inputs/outputs that are already connected to given\n");
69 log(" ports of the given cell. Can be used multiple times. This is in\n");
70 log(" addition to the cells specified as mapping targets.\n");
72 log(" -widthparam <param_name>\n");
73 log(" Use the specified parameter name to set the port width.\n");
75 log(" -nameparam <param_name>\n");
76 log(" Use the specified parameter to set the port name.\n");
79 log(" create individual bit-wide buffers even for ports that\n");
80 log(" are wider. (the default behavior is to create word-wide\n");
81 log(" buffers using -widthparam to set the word size on the cell.)\n");
83 log("Tristate PADS (-toutpad, -tinoutpad) always operate in -bits mode.\n");
86 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
88 log_header(design
, "Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
90 std::string inpad_celltype
, inpad_portname_o
, inpad_portname_pad
;
91 std::string outpad_celltype
, outpad_portname_i
, outpad_portname_pad
;
92 std::string inoutpad_celltype
, inoutpad_portname_io
, inoutpad_portname_pad
;
93 std::string toutpad_celltype
, toutpad_portname_oe
, toutpad_portname_i
, toutpad_portname_pad
;
94 std::string tinoutpad_celltype
, tinoutpad_portname_oe
, tinoutpad_portname_o
, tinoutpad_portname_i
, tinoutpad_portname_pad
;
95 std::string widthparam
, nameparam
;
96 pool
<pair
<IdString
, IdString
>> ignore
;
97 bool flag_bits
= false;
100 for (argidx
= 1; argidx
< args
.size(); argidx
++)
102 std::string arg
= args
[argidx
];
103 if (arg
== "-inpad" && argidx
+2 < args
.size()) {
104 inpad_celltype
= args
[++argidx
];
105 inpad_portname_o
= args
[++argidx
];
106 split_portname_pair(inpad_portname_o
, inpad_portname_pad
);
109 if (arg
== "-outpad" && argidx
+2 < args
.size()) {
110 outpad_celltype
= args
[++argidx
];
111 outpad_portname_i
= args
[++argidx
];
112 split_portname_pair(outpad_portname_i
, outpad_portname_pad
);
115 if (arg
== "-inoutpad" && argidx
+2 < args
.size()) {
116 inoutpad_celltype
= args
[++argidx
];
117 inoutpad_portname_io
= args
[++argidx
];
118 split_portname_pair(inoutpad_portname_io
, inoutpad_portname_pad
);
121 if (arg
== "-toutpad" && argidx
+2 < args
.size()) {
122 toutpad_celltype
= args
[++argidx
];
123 toutpad_portname_oe
= args
[++argidx
];
124 split_portname_pair(toutpad_portname_oe
, toutpad_portname_i
);
125 split_portname_pair(toutpad_portname_i
, toutpad_portname_pad
);
128 if (arg
== "-tinoutpad" && argidx
+2 < args
.size()) {
129 tinoutpad_celltype
= args
[++argidx
];
130 tinoutpad_portname_oe
= args
[++argidx
];
131 split_portname_pair(tinoutpad_portname_oe
, tinoutpad_portname_o
);
132 split_portname_pair(tinoutpad_portname_o
, tinoutpad_portname_i
);
133 split_portname_pair(tinoutpad_portname_i
, tinoutpad_portname_pad
);
136 if (arg
== "-ignore" && argidx
+2 < args
.size()) {
137 std::string ignore_celltype
= args
[++argidx
];
138 std::string ignore_portname
= args
[++argidx
];
139 std::string ignore_portname2
;
140 while (!ignore_portname
.empty()) {
141 split_portname_pair(ignore_portname
, ignore_portname2
);
142 ignore
.insert(make_pair(RTLIL::escape_id(ignore_celltype
), RTLIL::escape_id(ignore_portname
)));
144 ignore_portname
= ignore_portname2
;
148 if (arg
== "-widthparam" && argidx
+1 < args
.size()) {
149 widthparam
= args
[++argidx
];
152 if (arg
== "-nameparam" && argidx
+1 < args
.size()) {
153 nameparam
= args
[++argidx
];
156 if (arg
== "-bits") {
162 extra_args(args
, argidx
, design
);
164 if (!inpad_portname_pad
.empty())
165 ignore
.insert(make_pair(RTLIL::escape_id(inpad_celltype
), RTLIL::escape_id(inpad_portname_pad
)));
166 if (!outpad_portname_pad
.empty())
167 ignore
.insert(make_pair(RTLIL::escape_id(outpad_celltype
), RTLIL::escape_id(outpad_portname_pad
)));
168 if (!inoutpad_portname_pad
.empty())
169 ignore
.insert(make_pair(RTLIL::escape_id(inoutpad_celltype
), RTLIL::escape_id(inoutpad_portname_pad
)));
170 if (!toutpad_portname_pad
.empty())
171 ignore
.insert(make_pair(RTLIL::escape_id(toutpad_celltype
), RTLIL::escape_id(toutpad_portname_pad
)));
172 if (!tinoutpad_portname_pad
.empty())
173 ignore
.insert(make_pair(RTLIL::escape_id(tinoutpad_celltype
), RTLIL::escape_id(tinoutpad_portname_pad
)));
175 for (auto module
: design
->modules())
176 if (module
->get_blackbox_attribute())
177 for (auto wire
: module
->wires())
178 if (wire
->get_bool_attribute("\\iopad_external_pin"))
179 ignore
.insert(make_pair(module
->name
, wire
->name
));
181 for (auto module
: design
->selected_modules())
183 pool
<SigBit
> skip_wire_bits
;
184 dict
<Wire
*, dict
<int, pair
<Cell
*, IdString
>>> rewrite_bits
;
186 for (auto cell
: module
->cells())
187 for (auto port
: cell
->connections())
188 if (ignore
.count(make_pair(cell
->type
, port
.first
)))
189 for (auto bit
: port
.second
)
190 skip_wire_bits
.insert(bit
);
192 if (!toutpad_celltype
.empty() || !tinoutpad_celltype
.empty())
194 dict
<SigBit
, Cell
*> tbuf_bits
;
195 pool
<SigBit
> driven_bits
;
197 // Gather tristate buffers and always-on drivers.
198 for (auto cell
: module
->cells())
199 if (cell
->type
== ID($_TBUF_
)) {
200 SigBit bit
= cell
->getPort(ID::Y
).as_bit();
201 tbuf_bits
[bit
] = cell
;
203 for (auto port
: cell
->connections())
204 if (!cell
->known() || cell
->output(port
.first
))
205 for (auto bit
: port
.second
)
206 driven_bits
.insert(bit
);
209 // If a wire is a target of an assignment, it is driven, unless the source is 'z.
210 for (auto &conn
: module
->connections())
211 for (int i
= 0; i
< GetSize(conn
.first
); i
++) {
212 SigBit dstbit
= conn
.first
[i
];
213 SigBit srcbit
= conn
.second
[i
];
214 if (!srcbit
.wire
&& srcbit
.data
== State::Sz
)
216 driven_bits
.insert(dstbit
);
219 for (auto wire
: module
->selected_wires())
221 if (!wire
->port_output
)
224 // Don't handle inout ports if we have no suitable buffer type.
225 if (wire
->port_input
&& tinoutpad_celltype
.empty())
228 // likewise for output ports.
229 if (!wire
->port_input
&& toutpad_celltype
.empty())
232 for (int i
= 0; i
< GetSize(wire
); i
++)
234 SigBit
wire_bit(wire
, i
);
235 Cell
*tbuf_cell
= nullptr;
237 if (tbuf_bits
.count(wire_bit
))
238 tbuf_cell
= tbuf_bits
.at(wire_bit
);
242 bool is_driven
= driven_bits
.count(wire_bit
);
244 if (tbuf_cell
!= nullptr) {
245 // Found a tristate buffer — use it.
246 en_sig
= tbuf_cell
->getPort(ID(E
)).as_bit();
247 data_sig
= tbuf_cell
->getPort(ID::A
).as_bit();
248 } else if (is_driven
) {
249 // No tristate buffer, but an always-on driver is present.
250 // If this is an inout port, we're creating a tinoutpad
251 // anyway, just with a constant 1 as enable.
252 if (!wire
->port_input
)
254 en_sig
= SigBit(State::S1
);
257 // No driver on a wire. Create a tristate pad with always-0
259 en_sig
= SigBit(State::S0
);
260 data_sig
= SigBit(State::Sx
);
263 if (wire
->port_input
)
265 log("Mapping port %s.%s[%d] using %s.\n", log_id(module
), log_id(wire
), i
, tinoutpad_celltype
.c_str());
267 Cell
*cell
= module
->addCell(NEW_ID
, RTLIL::escape_id(tinoutpad_celltype
));
269 cell
->setPort(RTLIL::escape_id(tinoutpad_portname_oe
), en_sig
);
270 cell
->attributes
[ID::keep
] = RTLIL::Const(1);
273 module
->remove(tbuf_cell
);
274 cell
->setPort(RTLIL::escape_id(tinoutpad_portname_o
), wire_bit
);
275 cell
->setPort(RTLIL::escape_id(tinoutpad_portname_i
), data_sig
);
276 } else if (is_driven
) {
277 cell
->setPort(RTLIL::escape_id(tinoutpad_portname_i
), wire_bit
);
279 cell
->setPort(RTLIL::escape_id(tinoutpad_portname_o
), wire_bit
);
280 cell
->setPort(RTLIL::escape_id(tinoutpad_portname_i
), data_sig
);
282 skip_wire_bits
.insert(wire_bit
);
283 if (!tinoutpad_portname_pad
.empty())
284 rewrite_bits
[wire
][i
] = make_pair(cell
, RTLIL::escape_id(tinoutpad_portname_pad
));
286 log("Mapping port %s.%s[%d] using %s.\n", log_id(module
), log_id(wire
), i
, toutpad_celltype
.c_str());
288 Cell
*cell
= module
->addCell(NEW_ID
, RTLIL::escape_id(toutpad_celltype
));
290 cell
->setPort(RTLIL::escape_id(toutpad_portname_oe
), en_sig
);
291 cell
->setPort(RTLIL::escape_id(toutpad_portname_i
), data_sig
);
292 cell
->attributes
[ID::keep
] = RTLIL::Const(1);
295 module
->remove(tbuf_cell
);
296 module
->connect(wire_bit
, data_sig
);
298 skip_wire_bits
.insert(wire_bit
);
299 if (!toutpad_portname_pad
.empty())
300 rewrite_bits
[wire
][i
] = make_pair(cell
, RTLIL::escape_id(toutpad_portname_pad
));
306 for (auto wire
: module
->selected_wires())
311 std::string celltype
, portname_int
, portname_pad
;
312 pool
<int> skip_bit_indices
;
314 for (int i
= 0; i
< GetSize(wire
); i
++)
315 if (skip_wire_bits
.count(SigBit(wire
, i
)))
316 skip_bit_indices
.insert(i
);
318 if (GetSize(wire
) == GetSize(skip_bit_indices
))
321 if (wire
->port_input
&& !wire
->port_output
) {
322 if (inpad_celltype
.empty()) {
323 log("Don't map input port %s.%s: Missing option -inpad.\n", RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(wire
->name
));
326 celltype
= inpad_celltype
;
327 portname_int
= inpad_portname_o
;
328 portname_pad
= inpad_portname_pad
;
330 if (!wire
->port_input
&& wire
->port_output
) {
331 if (outpad_celltype
.empty()) {
332 log("Don't map output port %s.%s: Missing option -outpad.\n", RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(wire
->name
));
335 celltype
= outpad_celltype
;
336 portname_int
= outpad_portname_i
;
337 portname_pad
= outpad_portname_pad
;
339 if (wire
->port_input
&& wire
->port_output
) {
340 if (inoutpad_celltype
.empty()) {
341 log("Don't map inout port %s.%s: Missing option -inoutpad.\n", RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(wire
->name
));
344 celltype
= inoutpad_celltype
;
345 portname_int
= inoutpad_portname_io
;
346 portname_pad
= inoutpad_portname_pad
;
350 if (!flag_bits
&& wire
->width
!= 1 && widthparam
.empty()) {
351 log("Don't map multi-bit port %s.%s: Missing option -widthparam or -bits.\n", RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(wire
->name
));
355 log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(wire
->name
), celltype
.c_str());
359 for (int i
= 0; i
< wire
->width
; i
++)
361 if (skip_bit_indices
.count(i
))
364 SigBit
wire_bit(wire
, i
);
366 RTLIL::Cell
*cell
= module
->addCell(NEW_ID
, RTLIL::escape_id(celltype
));
367 cell
->setPort(RTLIL::escape_id(portname_int
), wire_bit
);
369 if (!portname_pad
.empty())
370 rewrite_bits
[wire
][i
] = make_pair(cell
, RTLIL::escape_id(portname_pad
));
371 if (!widthparam
.empty())
372 cell
->parameters
[RTLIL::escape_id(widthparam
)] = RTLIL::Const(1);
373 if (!nameparam
.empty())
374 cell
->parameters
[RTLIL::escape_id(nameparam
)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire
->name
), i
));
375 cell
->attributes
[ID::keep
] = RTLIL::Const(1);
380 RTLIL::Cell
*cell
= module
->addCell(NEW_ID
, RTLIL::escape_id(celltype
));
381 cell
->setPort(RTLIL::escape_id(portname_int
), RTLIL::SigSpec(wire
));
383 if (!portname_pad
.empty()) {
384 RTLIL::Wire
*new_wire
= NULL
;
385 new_wire
= module
->addWire(NEW_ID
, wire
);
386 module
->swap_names(new_wire
, wire
);
387 wire
->attributes
.clear();
388 cell
->setPort(RTLIL::escape_id(portname_pad
), RTLIL::SigSpec(new_wire
));
390 if (!widthparam
.empty())
391 cell
->parameters
[RTLIL::escape_id(widthparam
)] = RTLIL::Const(wire
->width
);
392 if (!nameparam
.empty())
393 cell
->parameters
[RTLIL::escape_id(nameparam
)] = RTLIL::Const(RTLIL::id2cstr(wire
->name
));
394 cell
->attributes
[ID::keep
] = RTLIL::Const(1);
397 if (!rewrite_bits
.count(wire
)) {
399 wire
->port_input
= false;
400 wire
->port_output
= false;
404 for (auto &it
: rewrite_bits
) {
405 RTLIL::Wire
*wire
= it
.first
;
406 RTLIL::Wire
*new_wire
= module
->addWire(NEW_ID
, wire
);
407 module
->swap_names(new_wire
, wire
);
408 wire
->attributes
.clear();
409 for (int i
= 0; i
< wire
->width
; i
++)
411 SigBit
wire_bit(wire
, i
);
412 if (!it
.second
.count(i
)) {
413 if (wire
->port_output
)
414 module
->connect(SigSpec(new_wire
, i
), SigSpec(wire
, i
));
416 module
->connect(SigSpec(wire
, i
), SigSpec(new_wire
, i
));
418 auto &new_conn
= it
.second
.at(i
);
419 new_conn
.first
->setPort(new_conn
.second
, RTLIL::SigSpec(new_wire
, i
));
424 wire
->port_input
= false;
425 wire
->port_output
= false;
428 module
->fixup_ports();
433 PRIVATE_NAMESPACE_END