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Undo "preserve wire attributes in iopadmap" change (it was OK before)
[yosys.git] / passes / techmap / iopadmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22
23 USING_YOSYS_NAMESPACE
24 PRIVATE_NAMESPACE_BEGIN
25
26 void split_portname_pair(std::string &port1, std::string &port2)
27 {
28 size_t pos = port1.find_first_of(':');
29 if (pos != std::string::npos) {
30 port2 = port1.substr(pos+1);
31 port1 = port1.substr(0, pos);
32 }
33 }
34
35 struct IopadmapPass : public Pass {
36 IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { }
37 virtual void help()
38 {
39 log("\n");
40 log(" iopadmap [options] [selection]\n");
41 log("\n");
42 log("Map module inputs/outputs to PAD cells from a library. This pass\n");
43 log("can only map to very simple PAD cells. Use 'techmap' to further map\n");
44 log("the resulting cells to more sophisticated PAD cells.\n");
45 log("\n");
46 log(" -inpad <celltype> <portname>[:<portname>]\n");
47 log(" Map module input ports to the given cell type with the\n");
48 log(" given output port name. if a 2nd portname is given, the\n");
49 log(" signal is passed through the pad call, using the 2nd\n");
50 log(" portname as the port facing the module port.\n");
51 log("\n");
52 log(" -outpad <celltype> <portname>[:<portname>]\n");
53 log(" -inoutpad <celltype> <portname>[:<portname>]\n");
54 log(" Similar to -inpad, but for output and inout ports.\n");
55 log("\n");
56 log(" -toutpad <celltype> <portname>:<portname>[:<portname>]\n");
57 log(" Merges $_TBUF_ cells into the output pad cell. This takes precedence\n");
58 log(" over the other -outpad cell. The first portname is the enable input\n");
59 log(" of the tristate driver.\n");
60 log("\n");
61 log(" -tinoutpad <celltype> <portname>:<portname>:<portname>[:<portname>]\n");
62 log(" Merges $_TBUF_ cells into the inout pad cell. This takes precedence\n");
63 log(" over the other -inoutpad cell. The first portname is the enable input\n");
64 log(" of the tristate driver and the 2nd portname is the internal output\n");
65 log(" buffering the external signal.\n");
66 log("\n");
67 log(" -widthparam <param_name>\n");
68 log(" Use the specified parameter name to set the port width.\n");
69 log("\n");
70 log(" -nameparam <param_name>\n");
71 log(" Use the specified parameter to set the port name.\n");
72 log("\n");
73 log(" -bits\n");
74 log(" create individual bit-wide buffers even for ports that\n");
75 log(" are wider. (the default behavior is to create word-wide\n");
76 log(" buffers using -widthparam to set the word size on the cell.)\n");
77 log("\n");
78 log("Tristate PADS (-toutpad, -tinoutpad) always operate in -bits mode.\n");
79 log("\n");
80 }
81 virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
82 {
83 log_header(design, "Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
84
85 std::string inpad_celltype, inpad_portname, inpad_portname2;
86 std::string outpad_celltype, outpad_portname, outpad_portname2;
87 std::string inoutpad_celltype, inoutpad_portname, inoutpad_portname2;
88 std::string toutpad_celltype, toutpad_portname, toutpad_portname2, toutpad_portname3;
89 std::string tinoutpad_celltype, tinoutpad_portname, tinoutpad_portname2, tinoutpad_portname3, tinoutpad_portname4;
90 std::string widthparam, nameparam;
91 bool flag_bits = false;
92
93 size_t argidx;
94 for (argidx = 1; argidx < args.size(); argidx++)
95 {
96 std::string arg = args[argidx];
97 if (arg == "-inpad" && argidx+2 < args.size()) {
98 inpad_celltype = args[++argidx];
99 inpad_portname = args[++argidx];
100 split_portname_pair(inpad_portname, inpad_portname2);
101 continue;
102 }
103 if (arg == "-outpad" && argidx+2 < args.size()) {
104 outpad_celltype = args[++argidx];
105 outpad_portname = args[++argidx];
106 split_portname_pair(outpad_portname, outpad_portname2);
107 continue;
108 }
109 if (arg == "-inoutpad" && argidx+2 < args.size()) {
110 inoutpad_celltype = args[++argidx];
111 inoutpad_portname = args[++argidx];
112 split_portname_pair(inoutpad_portname, inoutpad_portname2);
113 continue;
114 }
115 if (arg == "-toutpad" && argidx+2 < args.size()) {
116 toutpad_celltype = args[++argidx];
117 toutpad_portname = args[++argidx];
118 split_portname_pair(toutpad_portname, toutpad_portname2);
119 split_portname_pair(toutpad_portname2, toutpad_portname3);
120 continue;
121 }
122 if (arg == "-tinoutpad" && argidx+2 < args.size()) {
123 tinoutpad_celltype = args[++argidx];
124 tinoutpad_portname = args[++argidx];
125 split_portname_pair(tinoutpad_portname, tinoutpad_portname2);
126 split_portname_pair(tinoutpad_portname2, tinoutpad_portname3);
127 split_portname_pair(tinoutpad_portname3, tinoutpad_portname4);
128 continue;
129 }
130 if (arg == "-widthparam" && argidx+1 < args.size()) {
131 widthparam = args[++argidx];
132 continue;
133 }
134 if (arg == "-nameparam" && argidx+1 < args.size()) {
135 nameparam = args[++argidx];
136 continue;
137 }
138 if (arg == "-bits") {
139 flag_bits = true;
140 continue;
141 }
142 break;
143 }
144 extra_args(args, argidx, design);
145
146 for (auto module : design->selected_modules())
147 {
148 dict<IdString, pool<int>> skip_wires;
149
150 if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
151 {
152 SigMap sigmap(module);
153 dict<SigBit, pair<IdString, pool<IdString>>> tbuf_bits;
154
155 for (auto cell : module->cells())
156 if (cell->type == "$_TBUF_") {
157 SigBit bit = sigmap(cell->getPort("\\Y").as_bit());
158 tbuf_bits[bit].first = cell->name;
159 }
160
161 for (auto cell : module->cells())
162 for (auto port : cell->connections())
163 for (auto bit : sigmap(port.second))
164 if (tbuf_bits.count(bit))
165 tbuf_bits.at(bit).second.insert(cell->name);
166
167 for (auto wire : module->selected_wires())
168 {
169 if (!wire->port_output)
170 continue;
171
172 for (int i = 0; i < GetSize(wire); i++)
173 {
174 SigBit wire_bit(wire, i);
175 SigBit mapped_wire_bit = sigmap(wire_bit);
176
177 if (tbuf_bits.count(mapped_wire_bit) == 0)
178 continue;
179
180 auto &tbuf_cache = tbuf_bits.at(mapped_wire_bit);
181 Cell *tbuf_cell = module->cell(tbuf_cache.first);
182
183 if (tbuf_cell == nullptr)
184 continue;
185
186 SigBit en_sig = tbuf_cell->getPort("\\E").as_bit();
187 SigBit data_sig = tbuf_cell->getPort("\\A").as_bit();
188
189 if (wire->port_input && !tinoutpad_celltype.empty())
190 {
191 log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype.c_str());
192
193 Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(tinoutpad_celltype));
194 Wire *owire = module->addWire(NEW_ID);
195
196 cell->setPort(RTLIL::escape_id(tinoutpad_portname), en_sig);
197 cell->setPort(RTLIL::escape_id(tinoutpad_portname2), owire);
198 cell->setPort(RTLIL::escape_id(tinoutpad_portname3), data_sig);
199 cell->setPort(RTLIL::escape_id(tinoutpad_portname4), wire_bit);
200 cell->attributes["\\keep"] = RTLIL::Const(1);
201
202 for (auto cn : tbuf_cache.second) {
203 auto c = module->cell(cn);
204 if (c == nullptr)
205 continue;
206 for (auto port : c->connections()) {
207 SigSpec sig = port.second;
208 bool newsig = false;
209 for (auto &bit : sig)
210 if (sigmap(bit) == mapped_wire_bit) {
211 bit = owire;
212 newsig = true;
213 }
214 if (newsig)
215 c->setPort(port.first, sig);
216 }
217 }
218
219
220 module->remove(tbuf_cell);
221 skip_wires[wire->name].insert(i);
222 continue;
223 }
224
225 if (!wire->port_input && !toutpad_celltype.empty())
226 {
227 log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype.c_str());
228
229 Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(toutpad_celltype));
230
231 cell->setPort(RTLIL::escape_id(toutpad_portname), en_sig);
232 cell->setPort(RTLIL::escape_id(toutpad_portname2), data_sig);
233 cell->setPort(RTLIL::escape_id(toutpad_portname3), wire_bit);
234 cell->attributes["\\keep"] = RTLIL::Const(1);
235
236 for (auto cn : tbuf_cache.second) {
237 auto c = module->cell(cn);
238 if (c == nullptr)
239 continue;
240 for (auto port : c->connections()) {
241 SigSpec sig = port.second;
242 bool newsig = false;
243 for (auto &bit : sig)
244 if (sigmap(bit) == mapped_wire_bit) {
245 bit = data_sig;
246 newsig = true;
247 }
248 if (newsig)
249 c->setPort(port.first, sig);
250 }
251 }
252
253 module->remove(tbuf_cell);
254 skip_wires[wire->name].insert(i);
255 continue;
256 }
257 }
258 }
259 }
260
261 for (auto wire : module->selected_wires())
262 {
263 if (!wire->port_id)
264 continue;
265
266 std::string celltype, portname, portname2;
267 pool<int> skip_bit_indices;
268
269 if (skip_wires.count(wire->name)) {
270 if (!flag_bits)
271 continue;
272 skip_bit_indices = skip_wires.at(wire->name);
273 }
274
275 if (wire->port_input && !wire->port_output) {
276 if (inpad_celltype.empty()) {
277 log("Don't map input port %s.%s: Missing option -inpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
278 continue;
279 }
280 celltype = inpad_celltype;
281 portname = inpad_portname;
282 portname2 = inpad_portname2;
283 } else
284 if (!wire->port_input && wire->port_output) {
285 if (outpad_celltype.empty()) {
286 log("Don't map output port %s.%s: Missing option -outpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
287 continue;
288 }
289 celltype = outpad_celltype;
290 portname = outpad_portname;
291 portname2 = outpad_portname2;
292 } else
293 if (wire->port_input && wire->port_output) {
294 if (inoutpad_celltype.empty()) {
295 log("Don't map inout port %s.%s: Missing option -inoutpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
296 continue;
297 }
298 celltype = inoutpad_celltype;
299 portname = inoutpad_portname;
300 portname2 = inoutpad_portname2;
301 } else
302 log_abort();
303
304 if (!flag_bits && wire->width != 1 && widthparam.empty()) {
305 log("Don't map multi-bit port %s.%s: Missing option -widthparam or -bits.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
306 continue;
307 }
308
309 log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str());
310
311 RTLIL::Wire *new_wire = NULL;
312 if (!portname2.empty()) {
313 new_wire = module->addWire(NEW_ID, wire);
314 module->swap_names(new_wire, wire);
315 wire->attributes.clear();
316 }
317
318 if (flag_bits)
319 {
320 for (int i = 0; i < wire->width; i++)
321 {
322 if (skip_bit_indices.count(i)) {
323 if (wire->port_output)
324 module->connect(SigSpec(new_wire, i), SigSpec(wire, i));
325 else
326 module->connect(SigSpec(wire, i), SigSpec(new_wire, i));
327 continue;
328 }
329
330 RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
331 cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i));
332 if (!portname2.empty())
333 cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire, i));
334 if (!widthparam.empty())
335 cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
336 if (!nameparam.empty())
337 cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i));
338 cell->attributes["\\keep"] = RTLIL::Const(1);
339 }
340 }
341 else
342 {
343 RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
344 cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire));
345 if (!portname2.empty())
346 cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire));
347 if (!widthparam.empty())
348 cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
349 if (!nameparam.empty())
350 cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
351 cell->attributes["\\keep"] = RTLIL::Const(1);
352 }
353
354 wire->port_id = 0;
355 wire->port_input = false;
356 wire->port_output = false;
357 }
358
359 module->fixup_ports();
360 }
361 }
362 } IopadmapPass;
363
364 PRIVATE_NAMESPACE_END