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Transform "$.*" to ID("$.*") in passes/techmap
[yosys.git] / passes / techmap / iopadmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22
23 USING_YOSYS_NAMESPACE
24 PRIVATE_NAMESPACE_BEGIN
25
26 void split_portname_pair(std::string &port1, std::string &port2)
27 {
28 size_t pos = port1.find_first_of(':');
29 if (pos != std::string::npos) {
30 port2 = port1.substr(pos+1);
31 port1 = port1.substr(0, pos);
32 }
33 }
34
35 struct IopadmapPass : public Pass {
36 IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { }
37 void help() YS_OVERRIDE
38 {
39 log("\n");
40 log(" iopadmap [options] [selection]\n");
41 log("\n");
42 log("Map module inputs/outputs to PAD cells from a library. This pass\n");
43 log("can only map to very simple PAD cells. Use 'techmap' to further map\n");
44 log("the resulting cells to more sophisticated PAD cells.\n");
45 log("\n");
46 log(" -inpad <celltype> <portname>[:<portname>]\n");
47 log(" Map module input ports to the given cell type with the\n");
48 log(" given output port name. if a 2nd portname is given, the\n");
49 log(" signal is passed through the pad call, using the 2nd\n");
50 log(" portname as the port facing the module port.\n");
51 log("\n");
52 log(" -outpad <celltype> <portname>[:<portname>]\n");
53 log(" -inoutpad <celltype> <portname>[:<portname>]\n");
54 log(" Similar to -inpad, but for output and inout ports.\n");
55 log("\n");
56 log(" -toutpad <celltype> <portname>:<portname>[:<portname>]\n");
57 log(" Merges $_TBUF_ cells into the output pad cell. This takes precedence\n");
58 log(" over the other -outpad cell. The first portname is the enable input\n");
59 log(" of the tristate driver.\n");
60 log("\n");
61 log(" -tinoutpad <celltype> <portname>:<portname>:<portname>[:<portname>]\n");
62 log(" Merges $_TBUF_ cells into the inout pad cell. This takes precedence\n");
63 log(" over the other -inoutpad cell. The first portname is the enable input\n");
64 log(" of the tristate driver and the 2nd portname is the internal output\n");
65 log(" buffering the external signal.\n");
66 log("\n");
67 log(" -widthparam <param_name>\n");
68 log(" Use the specified parameter name to set the port width.\n");
69 log("\n");
70 log(" -nameparam <param_name>\n");
71 log(" Use the specified parameter to set the port name.\n");
72 log("\n");
73 log(" -bits\n");
74 log(" create individual bit-wide buffers even for ports that\n");
75 log(" are wider. (the default behavior is to create word-wide\n");
76 log(" buffers using -widthparam to set the word size on the cell.)\n");
77 log("\n");
78 log("Tristate PADS (-toutpad, -tinoutpad) always operate in -bits mode.\n");
79 log("\n");
80 }
81 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
82 {
83 log_header(design, "Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
84
85 std::string inpad_celltype, inpad_portname, inpad_portname2;
86 std::string outpad_celltype, outpad_portname, outpad_portname2;
87 std::string inoutpad_celltype, inoutpad_portname, inoutpad_portname2;
88 std::string toutpad_celltype, toutpad_portname, toutpad_portname2, toutpad_portname3;
89 std::string tinoutpad_celltype, tinoutpad_portname, tinoutpad_portname2, tinoutpad_portname3, tinoutpad_portname4;
90 std::string widthparam, nameparam;
91 bool flag_bits = false;
92
93 size_t argidx;
94 for (argidx = 1; argidx < args.size(); argidx++)
95 {
96 std::string arg = args[argidx];
97 if (arg == "-inpad" && argidx+2 < args.size()) {
98 inpad_celltype = args[++argidx];
99 inpad_portname = args[++argidx];
100 split_portname_pair(inpad_portname, inpad_portname2);
101 continue;
102 }
103 if (arg == "-outpad" && argidx+2 < args.size()) {
104 outpad_celltype = args[++argidx];
105 outpad_portname = args[++argidx];
106 split_portname_pair(outpad_portname, outpad_portname2);
107 continue;
108 }
109 if (arg == "-inoutpad" && argidx+2 < args.size()) {
110 inoutpad_celltype = args[++argidx];
111 inoutpad_portname = args[++argidx];
112 split_portname_pair(inoutpad_portname, inoutpad_portname2);
113 continue;
114 }
115 if (arg == "-toutpad" && argidx+2 < args.size()) {
116 toutpad_celltype = args[++argidx];
117 toutpad_portname = args[++argidx];
118 split_portname_pair(toutpad_portname, toutpad_portname2);
119 split_portname_pair(toutpad_portname2, toutpad_portname3);
120 continue;
121 }
122 if (arg == "-tinoutpad" && argidx+2 < args.size()) {
123 tinoutpad_celltype = args[++argidx];
124 tinoutpad_portname = args[++argidx];
125 split_portname_pair(tinoutpad_portname, tinoutpad_portname2);
126 split_portname_pair(tinoutpad_portname2, tinoutpad_portname3);
127 split_portname_pair(tinoutpad_portname3, tinoutpad_portname4);
128 continue;
129 }
130 if (arg == "-widthparam" && argidx+1 < args.size()) {
131 widthparam = args[++argidx];
132 continue;
133 }
134 if (arg == "-nameparam" && argidx+1 < args.size()) {
135 nameparam = args[++argidx];
136 continue;
137 }
138 if (arg == "-bits") {
139 flag_bits = true;
140 continue;
141 }
142 break;
143 }
144 extra_args(args, argidx, design);
145
146 for (auto module : design->selected_modules())
147 {
148 dict<IdString, pool<int>> skip_wires;
149 pool<SigBit> skip_wire_bits;
150 SigMap sigmap(module);
151
152 for (auto cell : module->cells())
153 {
154 if (cell->type == RTLIL::escape_id(inpad_celltype) && cell->hasPort(RTLIL::escape_id(inpad_portname2)))
155 for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inpad_portname2))))
156 skip_wire_bits.insert(bit);
157
158 if (cell->type == RTLIL::escape_id(outpad_celltype) && cell->hasPort(RTLIL::escape_id(outpad_portname2)))
159 for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(outpad_portname2))))
160 skip_wire_bits.insert(bit);
161
162 if (cell->type == RTLIL::escape_id(inoutpad_celltype) && cell->hasPort(RTLIL::escape_id(inoutpad_portname2)))
163 for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inoutpad_portname2))))
164 skip_wire_bits.insert(bit);
165
166 if (cell->type == RTLIL::escape_id(toutpad_celltype) && cell->hasPort(RTLIL::escape_id(toutpad_portname3)))
167 for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(toutpad_portname3))))
168 skip_wire_bits.insert(bit);
169
170 if (cell->type == RTLIL::escape_id(tinoutpad_celltype) && cell->hasPort(RTLIL::escape_id(tinoutpad_portname4)))
171 for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(tinoutpad_portname4))))
172 skip_wire_bits.insert(bit);
173 }
174
175 if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
176 {
177 dict<SigBit, pair<IdString, pool<IdString>>> tbuf_bits;
178 pool<pair<IdString, IdString>> norewrites;
179 SigMap rewrites;
180
181 for (auto cell : module->cells())
182 if (cell->type == ID($_TBUF_)) {
183 SigBit bit = sigmap(cell->getPort("\\Y").as_bit());
184 tbuf_bits[bit].first = cell->name;
185 }
186
187 for (auto cell : module->cells())
188 for (auto port : cell->connections())
189 for (auto bit : sigmap(port.second))
190 if (tbuf_bits.count(bit))
191 tbuf_bits.at(bit).second.insert(cell->name);
192
193 for (auto wire : module->selected_wires())
194 {
195 if (!wire->port_output)
196 continue;
197
198 for (int i = 0; i < GetSize(wire); i++)
199 {
200 SigBit wire_bit(wire, i);
201 SigBit mapped_wire_bit = sigmap(wire_bit);
202
203 if (tbuf_bits.count(mapped_wire_bit) == 0)
204 continue;
205
206 if (skip_wire_bits.count(mapped_wire_bit))
207 continue;
208
209 auto &tbuf_cache = tbuf_bits.at(mapped_wire_bit);
210 Cell *tbuf_cell = module->cell(tbuf_cache.first);
211
212 if (tbuf_cell == nullptr)
213 continue;
214
215 SigBit en_sig = tbuf_cell->getPort("\\E").as_bit();
216 SigBit data_sig = tbuf_cell->getPort("\\A").as_bit();
217
218 if (wire->port_input && !tinoutpad_celltype.empty())
219 {
220 log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype.c_str());
221
222 Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(tinoutpad_celltype));
223 Wire *owire = module->addWire(NEW_ID);
224
225 cell->setPort(RTLIL::escape_id(tinoutpad_portname), en_sig);
226 cell->setPort(RTLIL::escape_id(tinoutpad_portname2), owire);
227 cell->setPort(RTLIL::escape_id(tinoutpad_portname3), data_sig);
228 cell->setPort(RTLIL::escape_id(tinoutpad_portname4), wire_bit);
229 cell->attributes["\\keep"] = RTLIL::Const(1);
230
231 for (auto cn : tbuf_cache.second) {
232 auto c = module->cell(cn);
233 if (c == nullptr)
234 continue;
235 for (auto port : c->connections()) {
236 SigSpec sig = port.second;
237 bool newsig = false;
238 for (auto &bit : sig)
239 if (sigmap(bit) == mapped_wire_bit) {
240 bit = owire;
241 newsig = true;
242 }
243 if (newsig)
244 c->setPort(port.first, sig);
245 }
246 }
247
248
249 module->remove(tbuf_cell);
250 skip_wires[wire->name].insert(i);
251
252 norewrites.insert(make_pair(cell->name, RTLIL::escape_id(tinoutpad_portname4)));
253 rewrites.add(sigmap(wire_bit), owire);
254 continue;
255 }
256
257 if (!wire->port_input && !toutpad_celltype.empty())
258 {
259 log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype.c_str());
260
261 Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(toutpad_celltype));
262
263 cell->setPort(RTLIL::escape_id(toutpad_portname), en_sig);
264 cell->setPort(RTLIL::escape_id(toutpad_portname2), data_sig);
265 cell->setPort(RTLIL::escape_id(toutpad_portname3), wire_bit);
266 cell->attributes["\\keep"] = RTLIL::Const(1);
267
268 for (auto cn : tbuf_cache.second) {
269 auto c = module->cell(cn);
270 if (c == nullptr)
271 continue;
272 for (auto port : c->connections()) {
273 SigSpec sig = port.second;
274 bool newsig = false;
275 for (auto &bit : sig)
276 if (sigmap(bit) == mapped_wire_bit) {
277 bit = data_sig;
278 newsig = true;
279 }
280 if (newsig)
281 c->setPort(port.first, sig);
282 }
283 }
284
285 module->remove(tbuf_cell);
286 skip_wires[wire->name].insert(i);
287 continue;
288 }
289 }
290 }
291
292 if (GetSize(norewrites))
293 {
294 for (auto cell : module->cells())
295 for (auto port : cell->connections())
296 {
297 if (norewrites.count(make_pair(cell->name, port.first)))
298 continue;
299
300 SigSpec orig_sig = sigmap(port.second);
301 SigSpec new_sig = rewrites(orig_sig);
302
303 if (orig_sig != new_sig)
304 cell->setPort(port.first, new_sig);
305 }
306 }
307 }
308
309 for (auto wire : module->selected_wires())
310 {
311 if (!wire->port_id)
312 continue;
313
314 std::string celltype, portname, portname2;
315 pool<int> skip_bit_indices;
316
317 if (skip_wires.count(wire->name)) {
318 if (!flag_bits)
319 continue;
320 skip_bit_indices = skip_wires.at(wire->name);
321 }
322
323 for (int i = 0; i < GetSize(wire); i++)
324 if (skip_wire_bits.count(sigmap(SigBit(wire, i))))
325 skip_bit_indices.insert(i);
326
327 if (GetSize(wire) == GetSize(skip_bit_indices))
328 continue;
329
330 if (wire->port_input && !wire->port_output) {
331 if (inpad_celltype.empty()) {
332 log("Don't map input port %s.%s: Missing option -inpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
333 continue;
334 }
335 celltype = inpad_celltype;
336 portname = inpad_portname;
337 portname2 = inpad_portname2;
338 } else
339 if (!wire->port_input && wire->port_output) {
340 if (outpad_celltype.empty()) {
341 log("Don't map output port %s.%s: Missing option -outpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
342 continue;
343 }
344 celltype = outpad_celltype;
345 portname = outpad_portname;
346 portname2 = outpad_portname2;
347 } else
348 if (wire->port_input && wire->port_output) {
349 if (inoutpad_celltype.empty()) {
350 log("Don't map inout port %s.%s: Missing option -inoutpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
351 continue;
352 }
353 celltype = inoutpad_celltype;
354 portname = inoutpad_portname;
355 portname2 = inoutpad_portname2;
356 } else
357 log_abort();
358
359 if (!flag_bits && wire->width != 1 && widthparam.empty()) {
360 log("Don't map multi-bit port %s.%s: Missing option -widthparam or -bits.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
361 continue;
362 }
363
364 log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str());
365
366 RTLIL::Wire *new_wire = NULL;
367 if (!portname2.empty()) {
368 new_wire = module->addWire(NEW_ID, wire);
369 module->swap_names(new_wire, wire);
370 wire->attributes.clear();
371 }
372
373 if (flag_bits)
374 {
375 for (int i = 0; i < wire->width; i++)
376 {
377 if (skip_bit_indices.count(i)) {
378 if (wire->port_output)
379 module->connect(SigSpec(new_wire, i), SigSpec(wire, i));
380 else
381 module->connect(SigSpec(wire, i), SigSpec(new_wire, i));
382 continue;
383 }
384
385 RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
386 cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i));
387 if (!portname2.empty())
388 cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire, i));
389 if (!widthparam.empty())
390 cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
391 if (!nameparam.empty())
392 cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i));
393 cell->attributes["\\keep"] = RTLIL::Const(1);
394 }
395 }
396 else
397 {
398 RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
399 cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire));
400 if (!portname2.empty())
401 cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire));
402 if (!widthparam.empty())
403 cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
404 if (!nameparam.empty())
405 cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
406 cell->attributes["\\keep"] = RTLIL::Const(1);
407 }
408
409 wire->port_id = 0;
410 wire->port_input = false;
411 wire->port_output = false;
412 }
413
414 module->fixup_ports();
415 }
416 }
417 } IopadmapPass;
418
419 PRIVATE_NAMESPACE_END