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[yosys.git] / passes / techmap / iopadmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22
23 USING_YOSYS_NAMESPACE
24 PRIVATE_NAMESPACE_BEGIN
25
26 void split_portname_pair(std::string &port1, std::string &port2)
27 {
28 size_t pos = port1.find_first_of(':');
29 if (pos != std::string::npos) {
30 port2 = port1.substr(pos+1);
31 port1 = port1.substr(0, pos);
32 }
33 }
34
35 struct IopadmapPass : public Pass {
36 IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { }
37 void help() YS_OVERRIDE
38 {
39 log("\n");
40 log(" iopadmap [options] [selection]\n");
41 log("\n");
42 log("Map module inputs/outputs to PAD cells from a library. This pass\n");
43 log("can only map to very simple PAD cells. Use 'techmap' to further map\n");
44 log("the resulting cells to more sophisticated PAD cells.\n");
45 log("\n");
46 log(" -inpad <celltype> <portname>[:<portname>]\n");
47 log(" Map module input ports to the given cell type with the\n");
48 log(" given output port name. if a 2nd portname is given, the\n");
49 log(" signal is passed through the pad call, using the 2nd\n");
50 log(" portname as the port facing the module port.\n");
51 log("\n");
52 log(" -outpad <celltype> <portname>[:<portname>]\n");
53 log(" -inoutpad <celltype> <portname>[:<portname>]\n");
54 log(" Similar to -inpad, but for output and inout ports.\n");
55 log("\n");
56 log(" -toutpad <celltype> <portname>:<portname>[:<portname>]\n");
57 log(" Merges $_TBUF_ cells into the output pad cell. This takes precedence\n");
58 log(" over the other -outpad cell. The first portname is the enable input\n");
59 log(" of the tristate driver.\n");
60 log("\n");
61 log(" -tinoutpad <celltype> <portname>:<portname>:<portname>[:<portname>]\n");
62 log(" Merges $_TBUF_ cells into the inout pad cell. This takes precedence\n");
63 log(" over the other -inoutpad cell. The first portname is the enable input\n");
64 log(" of the tristate driver and the 2nd portname is the internal output\n");
65 log(" buffering the external signal.\n");
66 log("\n");
67 log(" -ignore <celltype> <portname>[:<portname>]*\n");
68 log(" Skips mapping inputs/outputs that are already connected to given\n");
69 log(" ports of the given cell. Can be used multiple times. This is in\n");
70 log(" addition to the cells specified as mapping targets.\n");
71 log("\n");
72 log(" -widthparam <param_name>\n");
73 log(" Use the specified parameter name to set the port width.\n");
74 log("\n");
75 log(" -nameparam <param_name>\n");
76 log(" Use the specified parameter to set the port name.\n");
77 log("\n");
78 log(" -bits\n");
79 log(" create individual bit-wide buffers even for ports that\n");
80 log(" are wider. (the default behavior is to create word-wide\n");
81 log(" buffers using -widthparam to set the word size on the cell.)\n");
82 log("\n");
83 log("Tristate PADS (-toutpad, -tinoutpad) always operate in -bits mode.\n");
84 log("\n");
85 }
86 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
87 {
88 log_header(design, "Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
89
90 std::string inpad_celltype, inpad_portname, inpad_portname2;
91 std::string outpad_celltype, outpad_portname, outpad_portname2;
92 std::string inoutpad_celltype, inoutpad_portname, inoutpad_portname2;
93 std::string toutpad_celltype, toutpad_portname, toutpad_portname2, toutpad_portname3;
94 std::string tinoutpad_celltype, tinoutpad_portname, tinoutpad_portname2, tinoutpad_portname3, tinoutpad_portname4;
95 std::string widthparam, nameparam;
96 pool<pair<IdString, IdString>> ignore;
97 bool flag_bits = false;
98
99 size_t argidx;
100 for (argidx = 1; argidx < args.size(); argidx++)
101 {
102 std::string arg = args[argidx];
103 if (arg == "-inpad" && argidx+2 < args.size()) {
104 inpad_celltype = args[++argidx];
105 inpad_portname = args[++argidx];
106 split_portname_pair(inpad_portname, inpad_portname2);
107 continue;
108 }
109 if (arg == "-outpad" && argidx+2 < args.size()) {
110 outpad_celltype = args[++argidx];
111 outpad_portname = args[++argidx];
112 split_portname_pair(outpad_portname, outpad_portname2);
113 continue;
114 }
115 if (arg == "-inoutpad" && argidx+2 < args.size()) {
116 inoutpad_celltype = args[++argidx];
117 inoutpad_portname = args[++argidx];
118 split_portname_pair(inoutpad_portname, inoutpad_portname2);
119 continue;
120 }
121 if (arg == "-toutpad" && argidx+2 < args.size()) {
122 toutpad_celltype = args[++argidx];
123 toutpad_portname = args[++argidx];
124 split_portname_pair(toutpad_portname, toutpad_portname2);
125 split_portname_pair(toutpad_portname2, toutpad_portname3);
126 continue;
127 }
128 if (arg == "-tinoutpad" && argidx+2 < args.size()) {
129 tinoutpad_celltype = args[++argidx];
130 tinoutpad_portname = args[++argidx];
131 split_portname_pair(tinoutpad_portname, tinoutpad_portname2);
132 split_portname_pair(tinoutpad_portname2, tinoutpad_portname3);
133 split_portname_pair(tinoutpad_portname3, tinoutpad_portname4);
134 continue;
135 }
136 if (arg == "-ignore" && argidx+2 < args.size()) {
137 std::string ignore_celltype = args[++argidx];
138 std::string ignore_portname = args[++argidx];
139 std::string ignore_portname2;
140 while (!ignore_portname.empty()) {
141 split_portname_pair(ignore_portname, ignore_portname2);
142 ignore.insert(make_pair(RTLIL::escape_id(ignore_celltype), RTLIL::escape_id(ignore_portname)));
143
144 ignore_portname = ignore_portname2;
145 }
146 continue;
147 }
148 if (arg == "-widthparam" && argidx+1 < args.size()) {
149 widthparam = args[++argidx];
150 continue;
151 }
152 if (arg == "-nameparam" && argidx+1 < args.size()) {
153 nameparam = args[++argidx];
154 continue;
155 }
156 if (arg == "-bits") {
157 flag_bits = true;
158 continue;
159 }
160 break;
161 }
162 extra_args(args, argidx, design);
163
164 if (!inpad_portname2.empty())
165 ignore.insert(make_pair(RTLIL::escape_id(inpad_celltype), RTLIL::escape_id(inpad_portname2)));
166 if (!outpad_portname2.empty())
167 ignore.insert(make_pair(RTLIL::escape_id(outpad_celltype), RTLIL::escape_id(outpad_portname2)));
168 if (!inoutpad_portname2.empty())
169 ignore.insert(make_pair(RTLIL::escape_id(inoutpad_celltype), RTLIL::escape_id(inoutpad_portname2)));
170 if (!toutpad_portname3.empty())
171 ignore.insert(make_pair(RTLIL::escape_id(toutpad_celltype), RTLIL::escape_id(toutpad_portname3)));
172 if (!tinoutpad_portname4.empty())
173 ignore.insert(make_pair(RTLIL::escape_id(tinoutpad_celltype), RTLIL::escape_id(tinoutpad_portname4)));
174
175 for (auto module : design->modules())
176 {
177 auto it = module->attributes.find("\\iopad_external_pin");
178 if (it != module->attributes.end()) {
179 auto value = it->second.decode_string();
180 for (auto name : split_tokens(value, ",")) {
181 ignore.insert(make_pair(module->name, RTLIL::escape_id(name)));
182 }
183 }
184 }
185
186 for (auto module : design->selected_modules())
187 {
188 dict<IdString, pool<int>> skip_wires;
189 pool<SigBit> skip_wire_bits;
190 SigMap sigmap(module);
191
192 for (auto cell : module->cells())
193 for (auto port : cell->connections())
194 if (ignore.count(make_pair(cell->type, port.first)))
195 for (auto bit : sigmap(port.second))
196 skip_wire_bits.insert(bit);
197
198 if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
199 {
200 dict<SigBit, pair<IdString, pool<IdString>>> tbuf_bits;
201 pool<pair<IdString, IdString>> norewrites;
202 SigMap rewrites;
203
204 for (auto cell : module->cells())
205 if (cell->type == "$_TBUF_") {
206 SigBit bit = sigmap(cell->getPort("\\Y").as_bit());
207 tbuf_bits[bit].first = cell->name;
208 }
209
210 for (auto cell : module->cells())
211 for (auto port : cell->connections())
212 for (auto bit : sigmap(port.second))
213 if (tbuf_bits.count(bit))
214 tbuf_bits.at(bit).second.insert(cell->name);
215
216 for (auto wire : module->selected_wires())
217 {
218 if (!wire->port_output)
219 continue;
220
221 for (int i = 0; i < GetSize(wire); i++)
222 {
223 SigBit wire_bit(wire, i);
224 SigBit mapped_wire_bit = sigmap(wire_bit);
225
226 if (tbuf_bits.count(mapped_wire_bit) == 0)
227 continue;
228
229 if (skip_wire_bits.count(mapped_wire_bit))
230 continue;
231
232 auto &tbuf_cache = tbuf_bits.at(mapped_wire_bit);
233 Cell *tbuf_cell = module->cell(tbuf_cache.first);
234
235 if (tbuf_cell == nullptr)
236 continue;
237
238 SigBit en_sig = tbuf_cell->getPort("\\E").as_bit();
239 SigBit data_sig = tbuf_cell->getPort("\\A").as_bit();
240
241 if (wire->port_input && !tinoutpad_celltype.empty())
242 {
243 log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype.c_str());
244
245 Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(tinoutpad_celltype));
246 Wire *owire = module->addWire(NEW_ID);
247
248 cell->setPort(RTLIL::escape_id(tinoutpad_portname), en_sig);
249 cell->setPort(RTLIL::escape_id(tinoutpad_portname2), owire);
250 cell->setPort(RTLIL::escape_id(tinoutpad_portname3), data_sig);
251 cell->setPort(RTLIL::escape_id(tinoutpad_portname4), wire_bit);
252 cell->attributes["\\keep"] = RTLIL::Const(1);
253
254 for (auto cn : tbuf_cache.second) {
255 auto c = module->cell(cn);
256 if (c == nullptr)
257 continue;
258 for (auto port : c->connections()) {
259 SigSpec sig = port.second;
260 bool newsig = false;
261 for (auto &bit : sig)
262 if (sigmap(bit) == mapped_wire_bit) {
263 bit = owire;
264 newsig = true;
265 }
266 if (newsig)
267 c->setPort(port.first, sig);
268 }
269 }
270
271
272 module->remove(tbuf_cell);
273 skip_wires[wire->name].insert(i);
274
275 norewrites.insert(make_pair(cell->name, RTLIL::escape_id(tinoutpad_portname4)));
276 rewrites.add(sigmap(wire_bit), owire);
277 continue;
278 }
279
280 if (!wire->port_input && !toutpad_celltype.empty())
281 {
282 log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype.c_str());
283
284 Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(toutpad_celltype));
285
286 cell->setPort(RTLIL::escape_id(toutpad_portname), en_sig);
287 cell->setPort(RTLIL::escape_id(toutpad_portname2), data_sig);
288 cell->setPort(RTLIL::escape_id(toutpad_portname3), wire_bit);
289 cell->attributes["\\keep"] = RTLIL::Const(1);
290
291 for (auto cn : tbuf_cache.second) {
292 auto c = module->cell(cn);
293 if (c == nullptr)
294 continue;
295 for (auto port : c->connections()) {
296 SigSpec sig = port.second;
297 bool newsig = false;
298 for (auto &bit : sig)
299 if (sigmap(bit) == mapped_wire_bit) {
300 bit = data_sig;
301 newsig = true;
302 }
303 if (newsig)
304 c->setPort(port.first, sig);
305 }
306 }
307
308 module->remove(tbuf_cell);
309 skip_wires[wire->name].insert(i);
310 continue;
311 }
312 }
313 }
314
315 if (GetSize(norewrites))
316 {
317 for (auto cell : module->cells())
318 for (auto port : cell->connections())
319 {
320 if (norewrites.count(make_pair(cell->name, port.first)))
321 continue;
322
323 SigSpec orig_sig = sigmap(port.second);
324 SigSpec new_sig = rewrites(orig_sig);
325
326 if (orig_sig != new_sig)
327 cell->setPort(port.first, new_sig);
328 }
329 }
330 }
331
332 for (auto wire : module->selected_wires())
333 {
334 if (!wire->port_id)
335 continue;
336
337 std::string celltype, portname, portname2;
338 pool<int> skip_bit_indices;
339
340 if (skip_wires.count(wire->name)) {
341 if (!flag_bits)
342 continue;
343 skip_bit_indices = skip_wires.at(wire->name);
344 }
345
346 for (int i = 0; i < GetSize(wire); i++)
347 if (skip_wire_bits.count(sigmap(SigBit(wire, i))))
348 skip_bit_indices.insert(i);
349
350 if (GetSize(wire) == GetSize(skip_bit_indices))
351 continue;
352
353 if (wire->port_input && !wire->port_output) {
354 if (inpad_celltype.empty()) {
355 log("Don't map input port %s.%s: Missing option -inpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
356 continue;
357 }
358 celltype = inpad_celltype;
359 portname = inpad_portname;
360 portname2 = inpad_portname2;
361 } else
362 if (!wire->port_input && wire->port_output) {
363 if (outpad_celltype.empty()) {
364 log("Don't map output port %s.%s: Missing option -outpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
365 continue;
366 }
367 celltype = outpad_celltype;
368 portname = outpad_portname;
369 portname2 = outpad_portname2;
370 } else
371 if (wire->port_input && wire->port_output) {
372 if (inoutpad_celltype.empty()) {
373 log("Don't map inout port %s.%s: Missing option -inoutpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
374 continue;
375 }
376 celltype = inoutpad_celltype;
377 portname = inoutpad_portname;
378 portname2 = inoutpad_portname2;
379 } else
380 log_abort();
381
382 if (!flag_bits && wire->width != 1 && widthparam.empty()) {
383 log("Don't map multi-bit port %s.%s: Missing option -widthparam or -bits.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
384 continue;
385 }
386
387 log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str());
388
389 RTLIL::Wire *new_wire = NULL;
390 if (!portname2.empty()) {
391 new_wire = module->addWire(NEW_ID, wire);
392 module->swap_names(new_wire, wire);
393 wire->attributes.clear();
394 }
395
396 if (flag_bits)
397 {
398 for (int i = 0; i < wire->width; i++)
399 {
400 if (skip_bit_indices.count(i)) {
401 if (wire->port_output)
402 module->connect(SigSpec(new_wire, i), SigSpec(wire, i));
403 else
404 module->connect(SigSpec(wire, i), SigSpec(new_wire, i));
405 continue;
406 }
407
408 RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
409 cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i));
410 if (!portname2.empty())
411 cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire, i));
412 if (!widthparam.empty())
413 cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
414 if (!nameparam.empty())
415 cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i));
416 cell->attributes["\\keep"] = RTLIL::Const(1);
417 }
418 }
419 else
420 {
421 RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
422 cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire));
423 if (!portname2.empty())
424 cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire));
425 if (!widthparam.empty())
426 cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
427 if (!nameparam.empty())
428 cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
429 cell->attributes["\\keep"] = RTLIL::Const(1);
430 }
431
432 wire->port_id = 0;
433 wire->port_input = false;
434 wire->port_output = false;
435 }
436
437 module->fixup_ports();
438 }
439 }
440 } IopadmapPass;
441
442 PRIVATE_NAMESPACE_END