passes/techmap/lut2mux.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21 #include "kernel/sigtools.h"
  22
  23 USING_YOSYS_NAMESPACE
  24 PRIVATE_NAMESPACE_BEGIN
  25
  26 int lut2mux(Cell *cell)
  27 {
  28         SigSpec sig_a = cell->getPort(ID::A);
  29         SigSpec sig_y = cell->getPort(ID::Y);
  30         Const lut = cell->getParam(ID::LUT);
  31         int count = 1;
  32
  33         if (GetSize(sig_a) == 1)
  34         {
  35                 cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y);
  36         }
  37         else
  38         {
  39                 SigSpec sig_a_hi = sig_a[GetSize(sig_a)-1];
  40                 SigSpec sig_a_lo = sig_a.extract(0, GetSize(sig_a)-1);
  41                 SigSpec sig_y1 = cell->module->addWire(NEW_ID);
  42                 SigSpec sig_y2 = cell->module->addWire(NEW_ID);
  43
  44                 Const lut1 = lut.extract(0, GetSize(lut)/2);
  45                 Const lut2 = lut.extract(GetSize(lut)/2, GetSize(lut)/2);
  46
  47                 count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1));
  48                 count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y2, lut2));
  49
  50                 cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y);
  51         }
  52
  53         cell->module->remove(cell);
  54         return count;
  55 }
  56
  57 struct Lut2muxPass : public Pass {
  58         Lut2muxPass() : Pass("lut2mux", "convert $lut to $_MUX_") { }
  59         void help() override
  60         {
  61                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  62                 log("\n");
  63                 log("    lut2mux [options] [selection]\n");
  64                 log("\n");
  65                 log("This pass converts $lut cells to $_MUX_ gates.\n");
  66                 log("\n");
  67         }
  68         void execute(std::vector<std::string> args, RTLIL::Design *design) override
  69         {
  70                 log_header(design, "Executing LUT2MUX pass (convert $lut to $_MUX_).\n");
  71
  72                 size_t argidx;
  73                 for (argidx = 1; argidx < args.size(); argidx++)
  74                 {
  75                         // if (args[argidx] == "-v") {
  76                         //      continue;
  77                         // }
  78                         break;
  79                 }
  80                 extra_args(args, argidx, design);
  81
  82                 for (auto module : design->selected_modules())
  83                 for (auto cell : module->selected_cells()) {
  84                         if (cell->type == ID($lut)) {
  85                                 IdString cell_name = cell->name;
  86                                 int count = lut2mux(cell);
  87                                 log("Converted %s.%s to %d MUX cells.\n", log_id(module), log_id(cell_name), count);
  88                         }
  89                 }
  90         }
  91 } Lut2muxPass;
  92
  93 PRIVATE_NAMESPACE_END