projects / yosys.git / blob
? search:


766c1c65ffd900f802c0d8f78342eb9498b52b0a
[yosys.git] / passes / techmap / shregmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22
23 USING_YOSYS_NAMESPACE
24 PRIVATE_NAMESPACE_BEGIN
25
26 struct ShregmapTech
27 {
28 virtual ~ShregmapTech() { }
29 virtual bool analyze(vector<int> &taps) = 0;
30 virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) = 0;
31 };
32
33 struct ShregmapOptions
34 {
35 int minlen, maxlen;
36 int keep_before, keep_after;
37 bool zinit, init, params, ffe;
38 dict<IdString, pair<IdString, IdString>> ffcells;
39 ShregmapTech *tech;
40
41 ShregmapOptions()
42 {
43 minlen = 2;
44 maxlen = 0;
45 keep_before = 0;
46 keep_after = 0;
47 zinit = false;
48 init = false;
49 params = false;
50 ffe = false;
51 tech = nullptr;
52 }
53 };
54
55 struct ShregmapTechGreenpak4 : ShregmapTech
56 {
57 bool analyze(vector<int> &taps)
58 {
59 if (GetSize(taps) > 2 && taps[0] == 0 && taps[2] < 17) {
60 taps.clear();
61 return true;
62 }
63
64 if (GetSize(taps) > 2)
65 return false;
66
67 if (taps.back() > 16) return false;
68
69 return true;
70 }
71
72 bool fixup(Cell *cell, dict<int, SigBit> &taps)
73 {
74 auto D = cell->getPort("\\D");
75 auto C = cell->getPort("\\C");
76
77 auto newcell = cell->module->addCell(NEW_ID, "\\GP_SHREG");
78 newcell->setPort("\\nRST", State::S1);
79 newcell->setPort("\\CLK", C);
80 newcell->setPort("\\IN", D);
81
82 int i = 0;
83 for (auto tap : taps) {
84 newcell->setPort(i ? "\\OUTB" : "\\OUTA", tap.second);
85 newcell->setParam(i ? "\\OUTB_TAP" : "\\OUTA_TAP", tap.first + 1);
86 i++;
87 }
88
89 cell->setParam("\\OUTA_INVERT", 0);
90 return false;
91 }
92 };
93
94 struct ShregmapWorker
95 {
96 Module *module;
97 SigMap sigmap;
98
99 const ShregmapOptions &opts;
100 int dff_count, shreg_count;
101
102 pool<Cell*> remove_cells;
103 pool<SigBit> remove_init;
104
105 dict<SigBit, bool> sigbit_init;
106 dict<SigBit, Cell*> sigbit_chain_next;
107 dict<SigBit, Cell*> sigbit_chain_prev;
108 pool<SigBit> sigbit_with_non_chain_users;
109 pool<Cell*> chain_start_cells;
110
111 void make_sigbit_chain_next_prev()
112 {
113 for (auto wire : module->wires())
114 {
115 if (wire->port_output) {
116 for (auto bit : sigmap(wire))
117 sigbit_with_non_chain_users.insert(bit);
118 }
119
120 if (wire->attributes.count("\\init")) {
121 SigSpec initsig = sigmap(wire);
122 Const initval = wire->attributes.at("\\init");
123 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
124 if (initval[i] == State::S0 && !opts.zinit)
125 sigbit_init[initsig[i]] = false;
126 else if (initval[i] == State::S1)
127 sigbit_init[initsig[i]] = true;
128 }
129 }
130
131 for (auto cell : module->cells())
132 {
133 if (opts.ffcells.count(cell->type))
134 {
135 IdString d_port = opts.ffcells.at(cell->type).first;
136 IdString q_port = opts.ffcells.at(cell->type).second;
137
138 SigBit d_bit = sigmap(cell->getPort(d_port).as_bit());
139 SigBit q_bit = sigmap(cell->getPort(q_port).as_bit());
140
141 if (opts.init || sigbit_init.count(q_bit) == 0)
142 {
143 if (sigbit_chain_next.count(d_bit)) {
144 sigbit_with_non_chain_users.insert(d_bit);
145 } else
146 sigbit_chain_next[d_bit] = cell;
147
148 sigbit_chain_prev[q_bit] = cell;
149 continue;
150 }
151 }
152
153 for (auto conn : cell->connections())
154 if (cell->input(conn.first))
155 for (auto bit : sigmap(conn.second))
156 sigbit_with_non_chain_users.insert(bit);
157 }
158 }
159
160 void find_chain_start_cells()
161 {
162 for (auto it : sigbit_chain_next)
163 {
164 if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first))
165 goto start_cell;
166
167 if (sigbit_chain_prev.count(it.first) != 0)
168 {
169 Cell *c1 = sigbit_chain_prev.at(it.first);
170 Cell *c2 = it.second;
171
172 if (c1->type != c2->type)
173 goto start_cell;
174
175 if (c1->parameters != c2->parameters)
176 goto start_cell;
177
178 IdString d_port = opts.ffcells.at(c1->type).first;
179 IdString q_port = opts.ffcells.at(c1->type).second;
180
181 auto c1_conn = c1->connections();
182 auto c2_conn = c1->connections();
183
184 c1_conn.erase(d_port);
185 c1_conn.erase(q_port);
186
187 c2_conn.erase(d_port);
188 c2_conn.erase(q_port);
189
190 if (c1_conn != c2_conn)
191 goto start_cell;
192
193 continue;
194 }
195
196 start_cell:
197 chain_start_cells.insert(it.second);
198 }
199 }
200
201 vector<Cell*> create_chain(Cell *start_cell)
202 {
203 vector<Cell*> chain;
204
205 Cell *c = start_cell;
206 while (c != nullptr)
207 {
208 chain.push_back(c);
209
210 IdString q_port = opts.ffcells.at(c->type).second;
211 SigBit q_bit = sigmap(c->getPort(q_port).as_bit());
212
213 if (sigbit_chain_next.count(q_bit) == 0)
214 break;
215
216 c = sigbit_chain_next.at(q_bit);
217 if (chain_start_cells.count(c) != 0)
218 break;
219 }
220
221 return chain;
222 }
223
224 void process_chain(vector<Cell*> &chain)
225 {
226 if (GetSize(chain) < opts.keep_before + opts.minlen + opts.keep_after)
227 return;
228
229 int cursor = opts.keep_before;
230 while (cursor < GetSize(chain) - opts.keep_after)
231 {
232 int depth = GetSize(chain) - opts.keep_after - cursor;
233
234 if (opts.maxlen > 0)
235 depth = std::min(opts.maxlen, depth);
236
237 Cell *first_cell = chain[cursor];
238 IdString q_port = opts.ffcells.at(first_cell->type).second;
239 dict<int, SigBit> taps_dict;
240
241 if (opts.tech)
242 {
243 vector<SigBit> qbits;
244 vector<int> taps;
245
246 for (int i = 0; i < depth; i++)
247 {
248 Cell *cell = chain[cursor+i];
249 auto qbit = sigmap(cell->getPort(q_port));
250 qbits.push_back(qbit);
251
252 if (sigbit_with_non_chain_users.count(qbit))
253 taps.push_back(i);
254 }
255
256 while (depth > 0)
257 {
258 if (taps.empty() || taps.back() < depth-1)
259 taps.push_back(depth-1);
260
261 if (opts.tech->analyze(taps))
262 break;
263
264 taps.pop_back();
265 depth--;
266 }
267
268 depth = 0;
269 for (auto tap : taps) {
270 taps_dict[tap] = qbits.at(tap);
271 log_assert(depth < tap+1);
272 depth = tap+1;
273 }
274 }
275
276 if (depth < 2) {
277 cursor++;
278 continue;
279 }
280
281 Cell *last_cell = chain[cursor+depth-1];
282
283 log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n",
284 log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), depth);
285
286 dff_count += depth;
287 shreg_count += 1;
288
289 string shreg_cell_type_str = "$__SHREG";
290 if (opts.params) {
291 shreg_cell_type_str += "_";
292 } else {
293 if (first_cell->type[1] != '_')
294 shreg_cell_type_str += "_";
295 shreg_cell_type_str += first_cell->type.substr(1);
296 }
297
298 if (opts.init) {
299 vector<State> initval;
300 for (int i = depth-1; i >= 0; i--) {
301 SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
302 if (sigbit_init.count(bit) == 0)
303 initval.push_back(State::Sx);
304 else if (sigbit_init.at(bit))
305 initval.push_back(State::S1);
306 else
307 initval.push_back(State::S0);
308 remove_init.insert(bit);
309 }
310 first_cell->setParam("\\INIT", initval);
311 }
312
313 if (opts.zinit)
314 for (int i = depth-1; i >= 0; i--) {
315 SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
316 remove_init.insert(bit);
317 }
318
319 if (opts.params)
320 {
321 int param_clkpol = -1;
322 int param_enpol = 2;
323
324 if (first_cell->type == "$_DFF_N_") param_clkpol = 0;
325 if (first_cell->type == "$_DFF_P_") param_clkpol = 1;
326
327 if (first_cell->type == "$_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
328 if (first_cell->type == "$_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
329 if (first_cell->type == "$_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
330 if (first_cell->type == "$_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
331
332 log_assert(param_clkpol >= 0);
333 first_cell->setParam("\\CLKPOL", param_clkpol);
334 if (opts.ffe) first_cell->setParam("\\ENPOL", param_enpol);
335 }
336
337 first_cell->type = shreg_cell_type_str;
338 first_cell->setPort(q_port, last_cell->getPort(q_port));
339 first_cell->setParam("\\DEPTH", depth);
340
341 if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
342 remove_cells.insert(first_cell);
343
344 for (int i = 1; i < depth; i++)
345 remove_cells.insert(chain[cursor+i]);
346 cursor += depth;
347 }
348 }
349
350 void cleanup()
351 {
352 for (auto cell : remove_cells)
353 module->remove(cell);
354
355 for (auto wire : module->wires())
356 {
357 if (wire->attributes.count("\\init") == 0)
358 continue;
359
360 SigSpec initsig = sigmap(wire);
361 Const &initval = wire->attributes.at("\\init");
362
363 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
364 if (remove_init.count(initsig[i]))
365 initval[i] = State::Sx;
366
367 if (SigSpec(initval).is_fully_undef())
368 wire->attributes.erase("\\init");
369 }
370
371 remove_cells.clear();
372 sigbit_chain_next.clear();
373 sigbit_chain_prev.clear();
374 chain_start_cells.clear();
375 }
376
377 ShregmapWorker(Module *module, const ShregmapOptions &opts) :
378 module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0)
379 {
380 make_sigbit_chain_next_prev();
381 find_chain_start_cells();
382
383 for (auto c : chain_start_cells) {
384 vector<Cell*> chain = create_chain(c);
385 process_chain(chain);
386 }
387
388 cleanup();
389 }
390 };
391
392 struct ShregmapPass : public Pass {
393 ShregmapPass() : Pass("shregmap", "map shift registers") { }
394 virtual void help()
395 {
396 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
397 log("\n");
398 log(" shregmap [options] [selection]\n");
399 log("\n");
400 log("This pass converts chains of $_DFF_[NP]_ gates to target specific shift register\n");
401 log("primitives. The generated shift register will be of type $__SHREG_DFF_[NP]_ and\n");
402 log("will use the same interface as the original $_DFF_*_ cells. The cell parameter\n");
403 log("'DEPTH' will contain the depth of the shift register. Use a target-specific\n");
404 log("'techmap' map file to convert those cells to the actual target cells.\n");
405 log("\n");
406 log(" -minlen N\n");
407 log(" minimum length of shift register (default = 2)\n");
408 log(" (this is the length after -keep_before and -keep_after)\n");
409 log("\n");
410 log(" -maxlen N\n");
411 log(" maximum length of shift register (default = no limit)\n");
412 log(" larger chains will be mapped to multiple shift register instances\n");
413 log("\n");
414 log(" -keep_before N\n");
415 log(" number of DFFs to keep before the shift register (default = 0)\n");
416 log("\n");
417 log(" -keep_after N\n");
418 log(" number of DFFs to keep after the shift register (default = 0)\n");
419 log("\n");
420 log(" -clkpol pos|neg|any\n");
421 log(" limit match to only positive or negative edge clocks. (default = any)\n");
422 log("\n");
423 log(" -enpol pos|neg|none|any_or_none|any\n");
424 log(" limit match to FFs with the specified enable polarity. (default = none)\n");
425 log("\n");
426 log(" -match <cell_type>[:<d_port_name>:<q_port_name>]\n");
427 log(" match the specified cells instead of $_DFF_N_ and $_DFF_P_. If\n");
428 log(" ':<d_port_name>:<q_port_name>' is omitted then 'D' and 'Q' is used\n");
429 log(" by default. E.g. the option '-clkpol pos' is just an alias for\n");
430 log(" '-match $_DFF_P_', which is an alias for '-match $_DFF_P_:D:Q'.\n");
431 log("\n");
432 log(" -params\n");
433 log(" instead of encoding the clock and enable polarity in the cell name by\n");
434 log(" deriving from the original cell name, simply name all generated cells\n");
435 log(" $__SHREG_ and use CLKPOL and ENPOL parameters. An ENPOL value of 2 is\n");
436 log(" used to denote cells without enable input. The ENPOL parameter is\n");
437 log(" omitted when '-enpol none' (or no -enpol option) is passed.\n");
438 log("\n");
439 log(" -zinit\n");
440 log(" assume the shift register is automatically zero-initialized, so it\n");
441 log(" becomes legal to merge zero initialized FFs into the shift register.\n");
442 log("\n");
443 log(" -init\n");
444 log(" map initialized registers to the shift reg, add an INIT parameter to\n");
445 log(" generated cells with the initialization value. (first bit to shift out\n");
446 log(" in LSB position)\n");
447 log("\n");
448 log(" -tech greenpak4\n");
449 log(" map to greenpak4 shift registers.\n");
450 log("\n");
451 }
452 virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
453 {
454 ShregmapOptions opts;
455 string clkpol, enpol;
456
457 log_header(design, "Executing SHREGMAP pass (map shift registers).\n");
458
459 size_t argidx;
460 for (argidx = 1; argidx < args.size(); argidx++)
461 {
462 if (args[argidx] == "-clkpol" && argidx+1 < args.size()) {
463 clkpol = args[++argidx];
464 continue;
465 }
466 if (args[argidx] == "-enpol" && argidx+1 < args.size()) {
467 enpol = args[++argidx];
468 continue;
469 }
470 if (args[argidx] == "-match" && argidx+1 < args.size()) {
471 vector<string> match_args = split_tokens(args[++argidx], ":");
472 if (GetSize(match_args) < 2)
473 match_args.push_back("D");
474 if (GetSize(match_args) < 3)
475 match_args.push_back("Q");
476 IdString id_cell_type(RTLIL::escape_id(match_args[0]));
477 IdString id_d_port_name(RTLIL::escape_id(match_args[1]));
478 IdString id_q_port_name(RTLIL::escape_id(match_args[2]));
479 opts.ffcells[id_cell_type] = make_pair(id_d_port_name, id_q_port_name);
480 continue;
481 }
482 if (args[argidx] == "-minlen" && argidx+1 < args.size()) {
483 opts.minlen = atoi(args[++argidx].c_str());
484 continue;
485 }
486 if (args[argidx] == "-maxlen" && argidx+1 < args.size()) {
487 opts.maxlen = atoi(args[++argidx].c_str());
488 continue;
489 }
490 if (args[argidx] == "-keep_before" && argidx+1 < args.size()) {
491 opts.keep_before = atoi(args[++argidx].c_str());
492 continue;
493 }
494 if (args[argidx] == "-keep_after" && argidx+1 < args.size()) {
495 opts.keep_after = atoi(args[++argidx].c_str());
496 continue;
497 }
498 if (args[argidx] == "-tech" && argidx+1 < args.size() && opts.tech == nullptr) {
499 string tech = args[++argidx];
500 if (tech == "greenpak4") {
501 clkpol = "pos";
502 opts.zinit = true;
503 opts.tech = new ShregmapTechGreenpak4;
504 } else {
505 argidx--;
506 break;
507 }
508 continue;
509 }
510 if (args[argidx] == "-zinit") {
511 opts.zinit = true;
512 continue;
513 }
514 if (args[argidx] == "-init") {
515 opts.init = true;
516 continue;
517 }
518 if (args[argidx] == "-params") {
519 opts.params = true;
520 continue;
521 }
522 break;
523 }
524 extra_args(args, argidx, design);
525
526 if (opts.zinit && opts.init)
527 log_cmd_error("Options -zinit and -init are exclusive!\n");
528
529 if (opts.ffcells.empty())
530 {
531 bool clk_pos = clkpol == "" || clkpol == "pos" || clkpol == "any";
532 bool clk_neg = clkpol == "" || clkpol == "neg" || clkpol == "any";
533
534 bool en_none = enpol == "" || enpol == "none" || enpol == "any_or_none";
535 bool en_pos = enpol == "pos" || enpol == "any" || enpol == "any_or_none";
536 bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none";
537
538 if (clk_pos && en_none)
539 opts.ffcells["$_DFF_P_"] = make_pair(IdString("\\D"), IdString("\\Q"));
540 if (clk_neg && en_none)
541 opts.ffcells["$_DFF_N_"] = make_pair(IdString("\\D"), IdString("\\Q"));
542
543 if (clk_pos && en_pos)
544 opts.ffcells["$_DFFE_PP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
545 if (clk_pos && en_neg)
546 opts.ffcells["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
547
548 if (clk_neg && en_pos)
549 opts.ffcells["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
550 if (clk_neg && en_neg)
551 opts.ffcells["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
552
553 if (en_pos || en_neg)
554 opts.ffe = true;
555 }
556 else
557 {
558 if (!clkpol.empty())
559 log_cmd_error("Options -clkpol and -match are exclusive!\n");
560 if (!enpol.empty())
561 log_cmd_error("Options -enpol and -match are exclusive!\n");
562 if (opts.params)
563 log_cmd_error("Options -params and -match are exclusive!\n");
564 }
565
566 int dff_count = 0;
567 int shreg_count = 0;
568
569 for (auto module : design->selected_modules()) {
570 ShregmapWorker worker(module, opts);
571 dff_count += worker.dff_count;
572 shreg_count += worker.shreg_count;
573 }
574
575 log("Converted %d dff cells into %d shift registers.\n", dff_count, shreg_count);
576
577 if (opts.tech != nullptr) {
578 delete opts.tech;
579 opts.tech = nullptr;
580 }
581 }
582 } ShregmapPass;
583
584 PRIVATE_NAMESPACE_END