2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
24 PRIVATE_NAMESPACE_BEGIN
28 virtual ~ShregmapTech() { }
29 virtual void init(const Module
* /*module*/, const SigMap
&/*sigmap*/) {}
30 virtual void non_chain_user(const SigBit
&/*bit*/, const Cell
* /*cell*/, IdString
/*port*/) {}
31 virtual bool analyze_first(const Cell
* /*first_cell*/, const SigMap
&/*sigmap*/) { return true; }
32 virtual bool analyze(vector
<int> &taps
, const vector
<SigBit
> &qbits
) = 0;
33 virtual Cell
* fixup(Cell
*cell
, const vector
<int> &taps
, const vector
<SigBit
> &qbits
) = 0;
36 struct ShregmapOptions
39 int keep_before
, keep_after
;
40 bool zinit
, init
, params
, ffe
;
41 dict
<IdString
, pair
<IdString
, IdString
>> ffcells
;
58 struct ShregmapTechGreenpak4
: ShregmapTech
60 virtual bool analyze(vector
<int> &taps
, const vector
<SigBit
> &/*qbits*/) override
62 if (GetSize(taps
) > 2 && taps
[0] == 0 && taps
[2] < 17) {
67 if (GetSize(taps
) > 2)
70 if (taps
.back() > 16) return false;
75 virtual Cell
* fixup(Cell
*cell
, const vector
<int> &taps
, const vector
<SigBit
> &qbits
) override
77 auto D
= cell
->getPort("\\D");
78 auto C
= cell
->getPort("\\C");
80 auto newcell
= cell
->module
->addCell(NEW_ID
, "\\GP_SHREG");
81 newcell
->setPort("\\nRST", State::S1
);
82 newcell
->setPort("\\CLK", C
);
83 newcell
->setPort("\\IN", D
);
86 for (auto tap
: taps
) {
87 newcell
->setPort(i
? "\\OUTB" : "\\OUTA", qbits
[tap
]);
88 newcell
->setParam(i
? "\\OUTB_TAP" : "\\OUTA_TAP", tap
+ 1);
92 cell
->setParam("\\OUTA_INVERT", 0);
97 struct ShregmapTechXilinx7Static
: ShregmapTech
99 dict
<SigBit
, Cell
*> sigbit_to_cell
;
100 const ShregmapOptions
&opts
;
102 virtual void init(const Module
* module
, const SigMap
&sigmap
) override
104 for (const auto &i
: module
->cells_
) {
105 auto cell
= i
.second
;
106 if (!cell
->type
.in("\\FDRE", "\\FDRE_1","\\FDSE", "\\FDSE_1",
107 "\\FDCE", "\\FDCE_1", "\\FDPE", "\\FDPE_1"))
110 sigbit_to_cell
[sigmap(cell
->getPort("\\Q"))] = cell
;
114 ShregmapTechXilinx7Static(const ShregmapOptions
&opts
) : opts(opts
) {}
116 virtual bool analyze_first(const Cell
* first_cell
, const SigMap
&sigmap
) override
118 if (first_cell
->type
.in("\\FDRE", "\\FDRE_1")) {
119 bool is_R_inverted
= false;
120 if (first_cell
->hasParam("\\IS_R_INVERTED"))
121 is_R_inverted
= first_cell
->getParam("\\IS_R_INVERTED").as_bool();
122 SigBit R
= sigmap(first_cell
->getPort("\\R"));
123 if (R
!= RTLIL::S0
&& R
!= RTLIL::S1
)
125 if ((!is_R_inverted
&& R
!= RTLIL::S0
) || (is_R_inverted
&& R
!= RTLIL::S1
))
129 if (first_cell
->type
.in("\\FDSE", "\\FDSE_1")) {
130 bool is_S_inverted
= false;
131 if (first_cell
->hasParam("\\IS_S_INVERTED"))
132 is_S_inverted
= first_cell
->getParam("\\IS_S_INVERTED").as_bool();
133 SigBit S
= sigmap(first_cell
->getPort("\\S"));
134 if (S
!= RTLIL::S0
&& S
!= RTLIL::S1
)
136 if ((!is_S_inverted
&& S
!= RTLIL::S0
) || (is_S_inverted
&& S
!= RTLIL::S1
))
140 if (first_cell
->type
.in("\\FDCE", "\\FDCE_1")) {
141 bool is_CLR_inverted
= false;
142 if (first_cell
->hasParam("\\IS_CLR_INVERTED"))
143 is_CLR_inverted
= first_cell
->getParam("\\IS_CLR_INVERTED").as_bool();
144 SigBit CLR
= sigmap(first_cell
->getPort("\\CLR"));
145 if (CLR
!= RTLIL::S0
&& CLR
!= RTLIL::S1
)
147 if ((!is_CLR_inverted
&& CLR
!= RTLIL::S0
) || (is_CLR_inverted
&& CLR
!= RTLIL::S1
))
151 if (first_cell
->type
.in("\\FDPE", "\\FDPE_1")) {
152 bool is_PRE_inverted
= false;
153 if (first_cell
->hasParam("\\IS_PRE_INVERTED"))
154 is_PRE_inverted
= first_cell
->getParam("\\IS_PRE_INVERTED").as_bool();
155 SigBit PRE
= sigmap(first_cell
->getPort("\\PRE"));
156 if (PRE
!= RTLIL::S0
&& PRE
!= RTLIL::S1
)
158 if ((!is_PRE_inverted
&& PRE
!= RTLIL::S0
) || (is_PRE_inverted
&& PRE
!= RTLIL::S1
))
165 virtual bool analyze(vector
<int> &taps
, const vector
<SigBit
> &/*qbits*/) override
167 return GetSize(taps
) == 1 && taps
[0] >= opts
.minlen
-1;
170 virtual Cell
* fixup(Cell
*cell
, const vector
<int> &/*taps*/, const vector
<SigBit
> &qbits
) override
172 auto newcell
= cell
->module
->addCell(NEW_ID
, "$__SHREG_");
173 newcell
->set_src_attribute(cell
->get_src_attribute());
174 newcell
->setParam("\\DEPTH", cell
->getParam("\\DEPTH"));
176 if (cell
->type
.in("$__SHREG_DFF_N_", "$__SHREG_DFF_P_",
177 "$__SHREG_DFFE_NN_", "$__SHREG_DFFE_NP_", "$__SHREG_DFFE_PN_", "$__SHREG_DFFE_PP_")) {
178 int param_clkpol
= -1;
180 if (cell
->type
== "$__SHREG_DFF_N_") param_clkpol
= 0;
181 else if (cell
->type
== "$__SHREG_DFF_P_") param_clkpol
= 1;
182 else if (cell
->type
== "$__SHREG_DFFE_NN_") param_clkpol
= 0, param_enpol
= 0;
183 else if (cell
->type
== "$__SHREG_DFFE_NP_") param_clkpol
= 0, param_enpol
= 1;
184 else if (cell
->type
== "$__SHREG_DFFE_PN_") param_clkpol
= 1, param_enpol
= 0;
185 else if (cell
->type
== "$__SHREG_DFFE_PP_") param_clkpol
= 1, param_enpol
= 1;
188 log_assert(param_clkpol
>= 0);
189 newcell
->setParam("\\CLKPOL", param_clkpol
);
190 newcell
->setParam("\\ENPOL", param_enpol
);
191 newcell
->setParam("\\INIT", cell
->getParam("\\INIT"));
193 if (cell
->hasPort("\\E"))
194 newcell
->setPort("\\E", cell
->getPort("\\E"));
196 else if (cell
->type
.in("$__SHREG_FDRE", "$__SHREG_FDRE_1","$__SHREG_FDSE", "$__SHREG_FDSE_1",
197 "$__SHREG_FDCE", "$__SHREG_FDCE_1", "$__SHREG_FDPE", "$__SHREG_FDPE_1")) {
198 int param_clkpol
= 1;
199 if (cell
->hasParam("\\IS_C_INVERTED") && cell
->getParam("\\IS_C_INVERTED").as_bool())
201 newcell
->setParam("\\CLKPOL", param_clkpol
);
202 newcell
->setParam("\\ENPOL", 1);
203 log_assert(cell
->getParam("\\INIT").is_fully_undef());
205 for (auto q
: qbits
) {
206 Cell
* reg
= sigbit_to_cell
.at(q
);
207 INIT
.append(SigBit(reg
->getParam("\\INIT").as_bool()));
210 newcell
->setPort("\\E", cell
->getPort("\\CE"));
214 newcell
->setParam("\\ENPOL", 1);
216 newcell
->setPort("\\C", cell
->getPort("\\C"));
217 newcell
->setPort("\\D", cell
->getPort("\\D"));
218 newcell
->setPort("\\Q", cell
->getPort("\\Q"));
224 struct ShregmapTechXilinx7Dynamic
: ShregmapTechXilinx7Static
226 dict
<SigBit
, std::tuple
<Cell
*,int,int>> sigbit_to_shiftx_offset
;
228 ShregmapTechXilinx7Dynamic(const ShregmapOptions
&opts
) : ShregmapTechXilinx7Static(opts
) {}
230 virtual void init(const Module
* module
, const SigMap
&sigmap
) override
232 for (const auto &i
: module
->cells_
) {
233 auto cell
= i
.second
;
234 if (cell
->type
== "$shiftx") {
235 if (cell
->getParam("\\Y_WIDTH") != 1) continue;
237 for (auto bit
: sigmap(cell
->getPort("\\A")))
238 sigbit_to_shiftx_offset
[bit
] = std::make_tuple(cell
, j
++, 0);
239 log_assert(j
== cell
->getParam("\\A_WIDTH").as_int());
241 else if (cell
->type
== "$mux") {
243 for (auto bit
: sigmap(cell
->getPort("\\A")))
244 sigbit_to_shiftx_offset
[bit
] = std::make_tuple(cell
, 0, j
++);
246 for (auto bit
: sigmap(cell
->getPort("\\B")))
247 sigbit_to_shiftx_offset
[bit
] = std::make_tuple(cell
, 1, j
++);
252 virtual void non_chain_user(const SigBit
&bit
, const Cell
*cell
, IdString port
) override
254 auto it
= sigbit_to_shiftx_offset
.find(bit
);
255 if (it
== sigbit_to_shiftx_offset
.end())
258 if (cell
->type
== "$shiftx" && port
== "\\A")
260 if (cell
->type
== "$mux" && (port
== "\\A" || port
== "\\B"))
263 sigbit_to_shiftx_offset
.erase(it
);
266 virtual bool analyze(vector
<int> &taps
, const vector
<SigBit
> &qbits
) override
268 if (GetSize(taps
) == 1)
269 return taps
[0] >= opts
.minlen
-1 && sigbit_to_shiftx_offset
.count(qbits
[0]);
271 if (taps
.back() < opts
.minlen
-1)
274 Cell
*shiftx
= nullptr;
276 for (int i
= 0; i
< GetSize(taps
); ++i
) {
277 // Check taps are sequential
281 auto it
= sigbit_to_shiftx_offset
.find(qbits
[i
]);
282 if (it
== sigbit_to_shiftx_offset
.end())
285 // Check taps are not connected to a shift register,
286 // or sequential to the same shift register
289 std::tie(shiftx
,offset
,group
) = it
->second
;
294 Cell
*shiftx_
= std::get
<0>(it
->second
);
295 if (shiftx_
!= shiftx
)
297 int offset
= std::get
<1>(it
->second
);
300 int group_
= std::get
<2>(it
->second
);
307 // Only map if $shiftx exclusively covers the shift register
308 if (shiftx
->type
== "$shiftx") {
309 if (GetSize(taps
) > shiftx
->getParam("\\A_WIDTH").as_int())
311 // Due to padding the most significant bits of A may be 1'bx,
312 // and if so, discount them
313 if (GetSize(taps
) < shiftx
->getParam("\\A_WIDTH").as_int()) {
314 const SigSpec A
= shiftx
->getPort("\\A");
315 const int A_width
= shiftx
->getParam("\\A_WIDTH").as_int();
316 for (int i
= GetSize(taps
); i
< A_width
; ++i
)
317 if (A
[i
] != RTLIL::Sx
) return false;
319 else if (GetSize(taps
) != shiftx
->getParam("\\A_WIDTH").as_int())
322 else if (shiftx
->type
== "$mux") {
323 if (GetSize(taps
) != 2)
331 virtual Cell
* fixup(Cell
*cell
, const vector
<int> &taps
, const vector
<SigBit
> &qbits
) override
333 auto bit
= qbits
[taps
.front()];
335 auto it
= sigbit_to_shiftx_offset
.find(bit
);
336 log_assert(it
!= sigbit_to_shiftx_offset
.end());
338 Cell
* newcell
= ShregmapTechXilinx7Static::fixup(cell
, taps
, qbits
);
340 log_assert(newcell
->type
== "$__SHREG_");
341 newcell
->type
= "$__XILINX_SHREG_";
343 Cell
* shiftx
= std::get
<0>(it
->second
);
344 RTLIL::SigSpec l_wire
;
345 if (shiftx
->type
== "$shiftx")
346 l_wire
= shiftx
->getPort("\\B");
347 else if (shiftx
->type
== "$mux")
348 l_wire
= shiftx
->getPort("\\S");
351 newcell
->setPort("\\L", l_wire
);
352 newcell
->setPort("\\Q", shiftx
->getPort("\\Y"));
353 shiftx
->setPort("\\Y", cell
->module
->addWire(NEW_ID
));
360 struct ShregmapWorker
365 const ShregmapOptions
&opts
;
366 int dff_count
, shreg_count
;
368 pool
<Cell
*> remove_cells
;
369 pool
<SigBit
> remove_init
;
371 dict
<SigBit
, bool> sigbit_init
;
372 dict
<SigBit
, Cell
*> sigbit_chain_next
;
373 dict
<SigBit
, Cell
*> sigbit_chain_prev
;
374 pool
<SigBit
> sigbit_with_non_chain_users
;
375 pool
<Cell
*> chain_start_cells
;
377 void make_sigbit_chain_next_prev()
379 for (auto wire
: module
->wires())
381 if (wire
->port_output
|| wire
->get_bool_attribute("\\keep")) {
382 for (auto bit
: sigmap(wire
)) {
383 sigbit_with_non_chain_users
.insert(bit
);
384 if (opts
.tech
) opts
.tech
->non_chain_user(bit
, nullptr, {});
388 if (wire
->attributes
.count("\\init")) {
389 SigSpec initsig
= sigmap(wire
);
390 Const initval
= wire
->attributes
.at("\\init");
391 for (int i
= 0; i
< GetSize(initsig
) && i
< GetSize(initval
); i
++)
392 if (initval
[i
] == State::S0
&& !opts
.zinit
)
393 sigbit_init
[initsig
[i
]] = false;
394 else if (initval
[i
] == State::S1
)
395 sigbit_init
[initsig
[i
]] = true;
399 for (auto cell
: module
->cells())
401 if (opts
.ffcells
.count(cell
->type
) && !cell
->get_bool_attribute("\\keep"))
403 IdString d_port
= opts
.ffcells
.at(cell
->type
).first
;
404 IdString q_port
= opts
.ffcells
.at(cell
->type
).second
;
406 SigBit d_bit
= sigmap(cell
->getPort(d_port
).as_bit());
407 SigBit q_bit
= sigmap(cell
->getPort(q_port
).as_bit());
409 if (opts
.init
|| sigbit_init
.count(q_bit
) == 0)
411 if (sigbit_chain_next
.count(d_bit
)) {
412 sigbit_with_non_chain_users
.insert(d_bit
);
414 sigbit_chain_next
[d_bit
] = cell
;
416 sigbit_chain_prev
[q_bit
] = cell
;
421 for (auto conn
: cell
->connections())
422 if (cell
->input(conn
.first
))
423 for (auto bit
: sigmap(conn
.second
)) {
424 sigbit_with_non_chain_users
.insert(bit
);
425 if (opts
.tech
) opts
.tech
->non_chain_user(bit
, cell
, conn
.first
);
430 void find_chain_start_cells()
432 for (auto it
: sigbit_chain_next
)
434 if (opts
.tech
== nullptr && sigbit_with_non_chain_users
.count(it
.first
))
437 if (sigbit_chain_prev
.count(it
.first
) != 0)
439 Cell
*c1
= sigbit_chain_prev
.at(it
.first
);
440 Cell
*c2
= it
.second
;
442 if (c1
->type
!= c2
->type
)
445 if (c1
->parameters
!= c2
->parameters
)
448 IdString d_port
= opts
.ffcells
.at(c1
->type
).first
;
449 IdString q_port
= opts
.ffcells
.at(c1
->type
).second
;
451 auto c1_conn
= c1
->connections();
452 auto c2_conn
= c1
->connections();
454 c1_conn
.erase(d_port
);
455 c1_conn
.erase(q_port
);
457 c2_conn
.erase(d_port
);
458 c2_conn
.erase(q_port
);
460 if (c1_conn
!= c2_conn
)
467 chain_start_cells
.insert(it
.second
);
471 vector
<Cell
*> create_chain(Cell
*start_cell
)
475 Cell
*c
= start_cell
;
480 IdString q_port
= opts
.ffcells
.at(c
->type
).second
;
481 SigBit q_bit
= sigmap(c
->getPort(q_port
).as_bit());
483 if (sigbit_chain_next
.count(q_bit
) == 0)
486 c
= sigbit_chain_next
.at(q_bit
);
487 if (chain_start_cells
.count(c
) != 0)
494 void process_chain(vector
<Cell
*> &chain
)
496 if (GetSize(chain
) < opts
.keep_before
+ opts
.minlen
+ opts
.keep_after
)
499 int cursor
= opts
.keep_before
;
500 while (cursor
< GetSize(chain
) - opts
.keep_after
)
502 int depth
= GetSize(chain
) - opts
.keep_after
- cursor
;
505 depth
= std::min(opts
.maxlen
, depth
);
507 Cell
*first_cell
= chain
[cursor
];
508 IdString q_port
= opts
.ffcells
.at(first_cell
->type
).second
;
509 vector
<SigBit
> qbits
;
514 if (!opts
.tech
->analyze_first(first_cell
, sigmap
)) {
519 for (int i
= 0; i
< depth
; i
++)
521 Cell
*cell
= chain
[cursor
+i
];
522 auto qbit
= sigmap(cell
->getPort(q_port
));
523 qbits
.push_back(qbit
);
525 if (sigbit_with_non_chain_users
.count(qbit
))
531 if (taps
.empty() || taps
.back() < depth
-1)
532 taps
.push_back(depth
-1);
534 if (opts
.tech
->analyze(taps
, qbits
))
542 for (auto tap
: taps
) {
543 log_assert(depth
< tap
+1);
553 Cell
*last_cell
= chain
[cursor
+depth
-1];
555 log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n",
556 log_id(module
), log_id(first_cell
), log_id(module
), log_id(last_cell
), depth
);
561 string shreg_cell_type_str
= "$__SHREG";
563 shreg_cell_type_str
+= "_";
565 if (first_cell
->type
[1] != '_')
566 shreg_cell_type_str
+= "_";
567 shreg_cell_type_str
+= first_cell
->type
.substr(1);
571 vector
<State
> initval
;
572 for (int i
= depth
-1; i
>= 0; i
--) {
573 SigBit bit
= sigmap(chain
[cursor
+i
]->getPort(q_port
).as_bit());
574 if (sigbit_init
.count(bit
) == 0)
575 initval
.push_back(State::Sx
);
576 else if (sigbit_init
.at(bit
))
577 initval
.push_back(State::S1
);
579 initval
.push_back(State::S0
);
580 remove_init
.insert(bit
);
582 first_cell
->setParam("\\INIT", initval
);
586 for (int i
= depth
-1; i
>= 0; i
--) {
587 SigBit bit
= sigmap(chain
[cursor
+i
]->getPort(q_port
).as_bit());
588 remove_init
.insert(bit
);
593 int param_clkpol
= -1;
596 if (first_cell
->type
== "$_DFF_N_") param_clkpol
= 0;
597 if (first_cell
->type
== "$_DFF_P_") param_clkpol
= 1;
599 if (first_cell
->type
== "$_DFFE_NN_") param_clkpol
= 0, param_enpol
= 0;
600 if (first_cell
->type
== "$_DFFE_NP_") param_clkpol
= 0, param_enpol
= 1;
601 if (first_cell
->type
== "$_DFFE_PN_") param_clkpol
= 1, param_enpol
= 0;
602 if (first_cell
->type
== "$_DFFE_PP_") param_clkpol
= 1, param_enpol
= 1;
604 log_assert(param_clkpol
>= 0);
605 first_cell
->setParam("\\CLKPOL", param_clkpol
);
606 if (opts
.ffe
) first_cell
->setParam("\\ENPOL", param_enpol
);
609 first_cell
->type
= shreg_cell_type_str
;
610 first_cell
->setPort(q_port
, last_cell
->getPort(q_port
));
611 first_cell
->setParam("\\DEPTH", depth
);
613 if (opts
.tech
!= nullptr && opts
.tech
->fixup(first_cell
, taps
, qbits
))
614 remove_cells
.insert(first_cell
);
616 for (int i
= 1; i
< depth
; i
++)
617 remove_cells
.insert(chain
[cursor
+i
]);
624 for (auto cell
: remove_cells
)
625 module
->remove(cell
);
627 for (auto wire
: module
->wires())
629 if (wire
->attributes
.count("\\init") == 0)
632 SigSpec initsig
= sigmap(wire
);
633 Const
&initval
= wire
->attributes
.at("\\init");
635 for (int i
= 0; i
< GetSize(initsig
) && i
< GetSize(initval
); i
++)
636 if (remove_init
.count(initsig
[i
]))
637 initval
[i
] = State::Sx
;
639 if (SigSpec(initval
).is_fully_undef())
640 wire
->attributes
.erase("\\init");
643 remove_cells
.clear();
644 sigbit_chain_next
.clear();
645 sigbit_chain_prev
.clear();
646 chain_start_cells
.clear();
649 ShregmapWorker(Module
*module
, const ShregmapOptions
&opts
) :
650 module(module
), sigmap(module
), opts(opts
), dff_count(0), shreg_count(0)
653 opts
.tech
->init(module
, sigmap
);
655 make_sigbit_chain_next_prev();
656 find_chain_start_cells();
658 for (auto c
: chain_start_cells
) {
659 vector
<Cell
*> chain
= create_chain(c
);
660 process_chain(chain
);
667 struct ShregmapPass
: public Pass
{
668 ShregmapPass() : Pass("shregmap", "map shift registers") { }
669 void help() YS_OVERRIDE
671 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
673 log(" shregmap [options] [selection]\n");
675 log("This pass converts chains of $_DFF_[NP]_ gates to target specific shift register\n");
676 log("primitives. The generated shift register will be of type $__SHREG_DFF_[NP]_ and\n");
677 log("will use the same interface as the original $_DFF_*_ cells. The cell parameter\n");
678 log("'DEPTH' will contain the depth of the shift register. Use a target-specific\n");
679 log("'techmap' map file to convert those cells to the actual target cells.\n");
682 log(" minimum length of shift register (default = 2)\n");
683 log(" (this is the length after -keep_before and -keep_after)\n");
686 log(" maximum length of shift register (default = no limit)\n");
687 log(" larger chains will be mapped to multiple shift register instances\n");
689 log(" -keep_before N\n");
690 log(" number of DFFs to keep before the shift register (default = 0)\n");
692 log(" -keep_after N\n");
693 log(" number of DFFs to keep after the shift register (default = 0)\n");
695 log(" -clkpol pos|neg|any\n");
696 log(" limit match to only positive or negative edge clocks. (default = any)\n");
698 log(" -enpol pos|neg|none|any_or_none|any\n");
699 log(" limit match to FFs with the specified enable polarity. (default = none)\n");
701 log(" -match <cell_type>[:<d_port_name>:<q_port_name>]\n");
702 log(" match the specified cells instead of $_DFF_N_ and $_DFF_P_. If\n");
703 log(" ':<d_port_name>:<q_port_name>' is omitted then 'D' and 'Q' is used\n");
704 log(" by default. E.g. the option '-clkpol pos' is just an alias for\n");
705 log(" '-match $_DFF_P_', which is an alias for '-match $_DFF_P_:D:Q'.\n");
708 log(" instead of encoding the clock and enable polarity in the cell name by\n");
709 log(" deriving from the original cell name, simply name all generated cells\n");
710 log(" $__SHREG_ and use CLKPOL and ENPOL parameters. An ENPOL value of 2 is\n");
711 log(" used to denote cells without enable input. The ENPOL parameter is\n");
712 log(" omitted when '-enpol none' (or no -enpol option) is passed.\n");
715 log(" assume the shift register is automatically zero-initialized, so it\n");
716 log(" becomes legal to merge zero initialized FFs into the shift register.\n");
719 log(" map initialized registers to the shift reg, add an INIT parameter to\n");
720 log(" generated cells with the initialization value. (first bit to shift out\n");
721 log(" in LSB position)\n");
723 log(" -tech greenpak4\n");
724 log(" map to greenpak4 shift registers.\n");
726 log(" -tech xilinx\n");
727 log(" map to xilinx dynamic-length shift registers.\n");
730 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
732 ShregmapOptions opts
;
733 string clkpol
, enpol
;
735 log_header(design
, "Executing SHREGMAP pass (map shift registers).\n");
738 for (argidx
= 1; argidx
< args
.size(); argidx
++)
740 if (args
[argidx
] == "-clkpol" && argidx
+1 < args
.size()) {
741 clkpol
= args
[++argidx
];
744 if (args
[argidx
] == "-enpol" && argidx
+1 < args
.size()) {
745 enpol
= args
[++argidx
];
748 if (args
[argidx
] == "-match" && argidx
+1 < args
.size()) {
749 vector
<string
> match_args
= split_tokens(args
[++argidx
], ":");
750 if (GetSize(match_args
) < 2)
751 match_args
.push_back("D");
752 if (GetSize(match_args
) < 3)
753 match_args
.push_back("Q");
754 IdString
id_cell_type(RTLIL::escape_id(match_args
[0]));
755 IdString
id_d_port_name(RTLIL::escape_id(match_args
[1]));
756 IdString
id_q_port_name(RTLIL::escape_id(match_args
[2]));
757 opts
.ffcells
[id_cell_type
] = make_pair(id_d_port_name
, id_q_port_name
);
760 if (args
[argidx
] == "-minlen" && argidx
+1 < args
.size()) {
761 opts
.minlen
= atoi(args
[++argidx
].c_str());
764 if (args
[argidx
] == "-maxlen" && argidx
+1 < args
.size()) {
765 opts
.maxlen
= atoi(args
[++argidx
].c_str());
768 if (args
[argidx
] == "-keep_before" && argidx
+1 < args
.size()) {
769 opts
.keep_before
= atoi(args
[++argidx
].c_str());
772 if (args
[argidx
] == "-keep_after" && argidx
+1 < args
.size()) {
773 opts
.keep_after
= atoi(args
[++argidx
].c_str());
776 if (args
[argidx
] == "-tech" && argidx
+1 < args
.size() && opts
.tech
== nullptr) {
777 string tech
= args
[++argidx
];
778 if (tech
== "greenpak4") {
781 opts
.tech
= new ShregmapTechGreenpak4
;
783 else if (tech
== "xilinx_static" || tech
== "xilinx_dynamic") {
785 opts
.ffcells
["$_DFF_P_"] = make_pair(IdString("\\D"), IdString("\\Q"));
786 opts
.ffcells
["$_DFF_N_"] = make_pair(IdString("\\D"), IdString("\\Q"));
787 opts
.ffcells
["$_DFFE_PP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
788 opts
.ffcells
["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
789 opts
.ffcells
["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
790 opts
.ffcells
["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
791 opts
.ffcells
["\\FDRE"] = make_pair(IdString("\\D"), IdString("\\Q"));
792 opts
.ffcells
["\\FDRE_1"] = make_pair(IdString("\\D"), IdString("\\Q"));
793 opts
.ffcells
["\\FDSE"] = make_pair(IdString("\\D"), IdString("\\Q"));
794 opts
.ffcells
["\\FDSE_1"] = make_pair(IdString("\\D"), IdString("\\Q"));
795 opts
.ffcells
["\\FDCE"] = make_pair(IdString("\\D"), IdString("\\Q"));
796 opts
.ffcells
["\\FDCE_1"] = make_pair(IdString("\\D"), IdString("\\Q"));
797 opts
.ffcells
["\\FDPE"] = make_pair(IdString("\\D"), IdString("\\Q"));
798 opts
.ffcells
["\\FDPE_1"] = make_pair(IdString("\\D"), IdString("\\Q"));
799 if (tech
== "xilinx_static")
800 opts
.tech
= new ShregmapTechXilinx7Static(opts
);
801 else if (tech
== "xilinx_dynamic")
802 opts
.tech
= new ShregmapTechXilinx7Dynamic(opts
);
809 if (args
[argidx
] == "-zinit") {
813 if (args
[argidx
] == "-init") {
817 if (args
[argidx
] == "-params") {
823 extra_args(args
, argidx
, design
);
825 if (opts
.zinit
&& opts
.init
)
826 log_cmd_error("Options -zinit and -init are exclusive!\n");
828 if (opts
.ffcells
.empty())
830 bool clk_pos
= clkpol
== "" || clkpol
== "pos" || clkpol
== "any";
831 bool clk_neg
= clkpol
== "" || clkpol
== "neg" || clkpol
== "any";
833 bool en_none
= enpol
== "" || enpol
== "none" || enpol
== "any_or_none";
834 bool en_pos
= enpol
== "pos" || enpol
== "any" || enpol
== "any_or_none";
835 bool en_neg
= enpol
== "neg" || enpol
== "any" || enpol
== "any_or_none";
837 if (clk_pos
&& en_none
)
838 opts
.ffcells
["$_DFF_P_"] = make_pair(IdString("\\D"), IdString("\\Q"));
839 if (clk_neg
&& en_none
)
840 opts
.ffcells
["$_DFF_N_"] = make_pair(IdString("\\D"), IdString("\\Q"));
842 if (clk_pos
&& en_pos
)
843 opts
.ffcells
["$_DFFE_PP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
844 if (clk_pos
&& en_neg
)
845 opts
.ffcells
["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
847 if (clk_neg
&& en_pos
)
848 opts
.ffcells
["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
849 if (clk_neg
&& en_neg
)
850 opts
.ffcells
["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
852 if (en_pos
|| en_neg
)
858 log_cmd_error("Options -clkpol and -match are exclusive!\n");
860 log_cmd_error("Options -enpol and -match are exclusive!\n");
862 log_cmd_error("Options -params and -match are exclusive!\n");
868 for (auto module
: design
->selected_modules()) {
869 ShregmapWorker
worker(module
, opts
);
870 dff_count
+= worker
.dff_count
;
871 shreg_count
+= worker
.shreg_count
;
874 log("Converted %d dff cells into %d shift registers.\n", dff_count
, shreg_count
);
876 if (opts
.tech
!= nullptr) {
883 PRIVATE_NAMESPACE_END