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Revert "Refactor to ShregmapTechXilinx7Static"
[yosys.git] / passes / techmap / shregmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22
23 USING_YOSYS_NAMESPACE
24 PRIVATE_NAMESPACE_BEGIN
25
26 struct ShregmapTech
27 {
28 virtual ~ShregmapTech() { }
29 virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {}
30 virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {}
31 virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) = 0;
32 virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) = 0;
33 };
34
35 struct ShregmapOptions
36 {
37 int minlen, maxlen;
38 int keep_before, keep_after;
39 bool zinit, init, params, ffe;
40 dict<IdString, pair<IdString, IdString>> ffcells;
41 ShregmapTech *tech;
42
43 ShregmapOptions()
44 {
45 minlen = 2;
46 maxlen = 0;
47 keep_before = 0;
48 keep_after = 0;
49 zinit = false;
50 init = false;
51 params = false;
52 ffe = false;
53 tech = nullptr;
54 }
55 };
56
57 struct ShregmapTechGreenpak4 : ShregmapTech
58 {
59 virtual bool analyze(vector<int> &taps, const vector<SigBit> &/*qbits*/) override
60 {
61 if (GetSize(taps) > 2 && taps[0] == 0 && taps[2] < 17) {
62 taps.clear();
63 return true;
64 }
65
66 if (GetSize(taps) > 2)
67 return false;
68
69 if (taps.back() > 16) return false;
70
71 return true;
72 }
73
74 virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) override
75 {
76 auto D = cell->getPort("\\D");
77 auto C = cell->getPort("\\C");
78
79 auto newcell = cell->module->addCell(NEW_ID, "\\GP_SHREG");
80 newcell->setPort("\\nRST", State::S1);
81 newcell->setPort("\\CLK", C);
82 newcell->setPort("\\IN", D);
83
84 int i = 0;
85 for (auto tap : taps) {
86 newcell->setPort(i ? "\\OUTB" : "\\OUTA", tap.second);
87 newcell->setParam(i ? "\\OUTB_TAP" : "\\OUTA_TAP", tap.first + 1);
88 i++;
89 }
90
91 cell->setParam("\\OUTA_INVERT", 0);
92 return false;
93 }
94 };
95
96 struct ShregmapTechXilinx7Dynamic : ShregmapTech
97 {
98 dict<SigBit, std::tuple<Cell*,int,int>> sigbit_to_shiftx_offset;
99 const ShregmapOptions &opts;
100
101 ShregmapTechXilinx7Dynamic(const ShregmapOptions &opts) : opts(opts) {}
102
103 virtual void init(const Module* module, const SigMap &sigmap) override
104 {
105 for (const auto &i : module->cells_) {
106 auto cell = i.second;
107 if (cell->type == "$shiftx") {
108 if (cell->getParam("\\Y_WIDTH") != 1) continue;
109 int j = 0;
110 for (auto bit : sigmap(cell->getPort("\\A")))
111 sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, j++, 0);
112 log_assert(j == cell->getParam("\\A_WIDTH").as_int());
113 }
114 else if (cell->type == "$mux") {
115 int j = 0;
116 for (auto bit : sigmap(cell->getPort("\\A")))
117 sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 0, j++);
118 j = 0;
119 for (auto bit : sigmap(cell->getPort("\\B")))
120 sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 1, j++);
121 }
122 }
123 }
124
125 virtual void non_chain_user(const SigBit &bit, const Cell *cell, IdString port) override
126 {
127 auto it = sigbit_to_shiftx_offset.find(bit);
128 if (it == sigbit_to_shiftx_offset.end())
129 return;
130 if (cell) {
131 if (cell->type == "$shiftx" && port == "\\A")
132 return;
133 if (cell->type == "$mux" && (port == "\\A" || port == "\\B"))
134 return;
135 }
136 sigbit_to_shiftx_offset.erase(it);
137 }
138
139 virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) override
140 {
141 if (GetSize(taps) == 1)
142 return taps[0] >= opts.minlen-1 && sigbit_to_shiftx_offset.count(qbits[0]);
143
144 if (taps.back() < opts.minlen-1)
145 return false;
146
147 Cell *shiftx = nullptr;
148 int group = 0;
149 for (int i = 0; i < GetSize(taps); ++i) {
150 auto it = sigbit_to_shiftx_offset.find(qbits[i]);
151 if (it == sigbit_to_shiftx_offset.end())
152 return false;
153
154 // Check taps are sequential
155 if (i != taps[i])
156 return false;
157 // Check taps are not connected to a shift register,
158 // or sequential to the same shift register
159 if (i == 0) {
160 int offset;
161 std::tie(shiftx,offset,group) = it->second;
162 if (offset != i)
163 return false;
164 }
165 else {
166 Cell *shiftx_ = std::get<0>(it->second);
167 if (shiftx_ != shiftx)
168 return false;
169 int offset = std::get<1>(it->second);
170 if (offset != i)
171 return false;
172 int group_ = std::get<2>(it->second);
173 if (group_ != group)
174 return false;
175 }
176 }
177 log_assert(shiftx);
178
179 // Only map if $shiftx exclusively covers the shift register
180 if (shiftx->type == "$shiftx") {
181 if (GetSize(taps) > shiftx->getParam("\\A_WIDTH").as_int())
182 return false;
183 // Due to padding the most significant bits of A may be 1'bx,
184 // and if so, discount them
185 if (GetSize(taps) < shiftx->getParam("\\A_WIDTH").as_int()) {
186 const SigSpec A = shiftx->getPort("\\A");
187 const int A_width = shiftx->getParam("\\A_WIDTH").as_int();
188 for (int i = GetSize(taps); i < A_width; ++i)
189 if (A[i] != RTLIL::Sx) return false;
190 }
191 else if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int())
192 return false;
193 }
194 else if (shiftx->type == "$mux") {
195 if (GetSize(taps) != 2)
196 return false;
197 }
198 else log_abort();
199
200 return true;
201 }
202
203 virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) override
204 {
205 const auto &tap = *taps.begin();
206 auto bit = tap.second;
207
208 auto it = sigbit_to_shiftx_offset.find(bit);
209 log_assert(it != sigbit_to_shiftx_offset.end());
210
211 auto newcell = cell->module->addCell(NEW_ID, "$__XILINX_SHREG_");
212 newcell->set_src_attribute(cell->get_src_attribute());
213 newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH"));
214 newcell->setParam("\\INIT", cell->getParam("\\INIT"));
215
216 if (cell->type.in("$__SHREG_DFF_N_", "$__SHREG_DFF_P_",
217 "$__SHREG_DFFE_NN_", "$__SHREG_DFFE_NP_", "$__SHREG_DFFE_PN_", "$__SHREG_DFFE_PP_")) {
218 int param_clkpol = -1;
219 int param_enpol = 2;
220 if (cell->type == "$__SHREG_DFF_N_") param_clkpol = 0;
221 else if (cell->type == "$__SHREG_DFF_P_") param_clkpol = 1;
222 else if (cell->type == "$__SHREG_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
223 else if (cell->type == "$__SHREG_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
224 else if (cell->type == "$__SHREG_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
225 else if (cell->type == "$__SHREG_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
226 else log_abort();
227
228 log_assert(param_clkpol >= 0);
229 cell->setParam("\\CLKPOL", param_clkpol);
230 cell->setParam("\\ENPOL", param_enpol);
231 }
232 else log_abort();
233
234 newcell->setPort("\\C", cell->getPort("\\C"));
235 newcell->setPort("\\D", cell->getPort("\\D"));
236 if (cell->hasPort("\\E"))
237 newcell->setPort("\\E", cell->getPort("\\E"));
238
239 Cell* shiftx = std::get<0>(it->second);
240 RTLIL::SigSpec l_wire, q_wire;
241 if (shiftx->type == "$shiftx") {
242 l_wire = shiftx->getPort("\\B");
243 q_wire = shiftx->getPort("\\Y");
244 shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
245 }
246 else if (shiftx->type == "$mux") {
247 l_wire = shiftx->getPort("\\S");
248 q_wire = shiftx->getPort("\\Y");
249 shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
250 }
251 else log_abort();
252
253 newcell->setPort("\\Q", q_wire);
254 newcell->setPort("\\L", l_wire);
255
256 return false;
257 }
258 };
259
260
261 struct ShregmapWorker
262 {
263 Module *module;
264 SigMap sigmap;
265
266 const ShregmapOptions &opts;
267 int dff_count, shreg_count;
268
269 pool<Cell*> remove_cells;
270 pool<SigBit> remove_init;
271
272 dict<SigBit, bool> sigbit_init;
273 dict<SigBit, Cell*> sigbit_chain_next;
274 dict<SigBit, Cell*> sigbit_chain_prev;
275 pool<SigBit> sigbit_with_non_chain_users;
276 pool<Cell*> chain_start_cells;
277
278 void make_sigbit_chain_next_prev()
279 {
280 for (auto wire : module->wires())
281 {
282 if (wire->port_output || wire->get_bool_attribute("\\keep")) {
283 for (auto bit : sigmap(wire)) {
284 sigbit_with_non_chain_users.insert(bit);
285 if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {});
286 }
287 }
288
289 if (wire->attributes.count("\\init")) {
290 SigSpec initsig = sigmap(wire);
291 Const initval = wire->attributes.at("\\init");
292 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
293 if (initval[i] == State::S0 && !opts.zinit)
294 sigbit_init[initsig[i]] = false;
295 else if (initval[i] == State::S1)
296 sigbit_init[initsig[i]] = true;
297 }
298 }
299
300 for (auto cell : module->cells())
301 {
302 if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute("\\keep"))
303 {
304 IdString d_port = opts.ffcells.at(cell->type).first;
305 IdString q_port = opts.ffcells.at(cell->type).second;
306
307 SigBit d_bit = sigmap(cell->getPort(d_port).as_bit());
308 SigBit q_bit = sigmap(cell->getPort(q_port).as_bit());
309
310 if (opts.init || sigbit_init.count(q_bit) == 0)
311 {
312 if (sigbit_chain_next.count(d_bit)) {
313 sigbit_with_non_chain_users.insert(d_bit);
314 } else
315 sigbit_chain_next[d_bit] = cell;
316
317 sigbit_chain_prev[q_bit] = cell;
318 continue;
319 }
320 }
321
322 for (auto conn : cell->connections())
323 if (cell->input(conn.first))
324 for (auto bit : sigmap(conn.second)) {
325 sigbit_with_non_chain_users.insert(bit);
326 if (opts.tech) opts.tech->non_chain_user(bit, cell, conn.first);
327 }
328 }
329 }
330
331 void find_chain_start_cells()
332 {
333 for (auto it : sigbit_chain_next)
334 {
335 if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first))
336 goto start_cell;
337
338 if (sigbit_chain_prev.count(it.first) != 0)
339 {
340 Cell *c1 = sigbit_chain_prev.at(it.first);
341 Cell *c2 = it.second;
342
343 if (c1->type != c2->type)
344 goto start_cell;
345
346 if (c1->parameters != c2->parameters)
347 goto start_cell;
348
349 IdString d_port = opts.ffcells.at(c1->type).first;
350 IdString q_port = opts.ffcells.at(c1->type).second;
351
352 auto c1_conn = c1->connections();
353 auto c2_conn = c1->connections();
354
355 c1_conn.erase(d_port);
356 c1_conn.erase(q_port);
357
358 c2_conn.erase(d_port);
359 c2_conn.erase(q_port);
360
361 if (c1_conn != c2_conn)
362 goto start_cell;
363
364 continue;
365 }
366
367 start_cell:
368 chain_start_cells.insert(it.second);
369 }
370 }
371
372 vector<Cell*> create_chain(Cell *start_cell)
373 {
374 vector<Cell*> chain;
375
376 Cell *c = start_cell;
377 while (c != nullptr)
378 {
379 chain.push_back(c);
380
381 IdString q_port = opts.ffcells.at(c->type).second;
382 SigBit q_bit = sigmap(c->getPort(q_port).as_bit());
383
384 if (sigbit_chain_next.count(q_bit) == 0)
385 break;
386
387 c = sigbit_chain_next.at(q_bit);
388 if (chain_start_cells.count(c) != 0)
389 break;
390 }
391
392 return chain;
393 }
394
395 void process_chain(vector<Cell*> &chain)
396 {
397 if (GetSize(chain) < opts.keep_before + opts.minlen + opts.keep_after)
398 return;
399
400 int cursor = opts.keep_before;
401 while (cursor < GetSize(chain) - opts.keep_after)
402 {
403 int depth = GetSize(chain) - opts.keep_after - cursor;
404
405 if (opts.maxlen > 0)
406 depth = std::min(opts.maxlen, depth);
407
408 Cell *first_cell = chain[cursor];
409 IdString q_port = opts.ffcells.at(first_cell->type).second;
410 dict<int, SigBit> taps_dict;
411
412 if (opts.tech)
413 {
414 vector<SigBit> qbits;
415 vector<int> taps;
416
417 for (int i = 0; i < depth; i++)
418 {
419 Cell *cell = chain[cursor+i];
420 auto qbit = sigmap(cell->getPort(q_port));
421 qbits.push_back(qbit);
422
423 if (sigbit_with_non_chain_users.count(qbit))
424 taps.push_back(i);
425 }
426
427 while (depth > 0)
428 {
429 if (taps.empty() || taps.back() < depth-1)
430 taps.push_back(depth-1);
431
432 if (opts.tech->analyze(taps, qbits))
433 break;
434
435 taps.pop_back();
436 depth--;
437 }
438
439 depth = 0;
440 for (auto tap : taps) {
441 taps_dict[tap] = qbits.at(tap);
442 log_assert(depth < tap+1);
443 depth = tap+1;
444 }
445 }
446
447 if (depth < 2) {
448 cursor++;
449 continue;
450 }
451
452 Cell *last_cell = chain[cursor+depth-1];
453
454 log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n",
455 log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), depth);
456
457 dff_count += depth;
458 shreg_count += 1;
459
460 string shreg_cell_type_str = "$__SHREG";
461 if (opts.params) {
462 shreg_cell_type_str += "_";
463 } else {
464 if (first_cell->type[1] != '_')
465 shreg_cell_type_str += "_";
466 shreg_cell_type_str += first_cell->type.substr(1);
467 }
468
469 if (opts.init) {
470 vector<State> initval;
471 for (int i = depth-1; i >= 0; i--) {
472 SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
473 if (sigbit_init.count(bit) == 0)
474 initval.push_back(State::Sx);
475 else if (sigbit_init.at(bit))
476 initval.push_back(State::S1);
477 else
478 initval.push_back(State::S0);
479 remove_init.insert(bit);
480 }
481 first_cell->setParam("\\INIT", initval);
482 }
483
484 if (opts.zinit)
485 for (int i = depth-1; i >= 0; i--) {
486 SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
487 remove_init.insert(bit);
488 }
489
490 if (opts.params)
491 {
492 int param_clkpol = -1;
493 int param_enpol = 2;
494
495 if (first_cell->type == "$_DFF_N_") param_clkpol = 0;
496 if (first_cell->type == "$_DFF_P_") param_clkpol = 1;
497
498 if (first_cell->type == "$_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
499 if (first_cell->type == "$_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
500 if (first_cell->type == "$_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
501 if (first_cell->type == "$_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
502
503 log_assert(param_clkpol >= 0);
504 first_cell->setParam("\\CLKPOL", param_clkpol);
505 if (opts.ffe) first_cell->setParam("\\ENPOL", param_enpol);
506 }
507
508 first_cell->type = shreg_cell_type_str;
509 first_cell->setPort(q_port, last_cell->getPort(q_port));
510 first_cell->setParam("\\DEPTH", depth);
511
512 if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
513 remove_cells.insert(first_cell);
514
515 for (int i = 1; i < depth; i++)
516 remove_cells.insert(chain[cursor+i]);
517 cursor += depth;
518 }
519 }
520
521 void cleanup()
522 {
523 for (auto cell : remove_cells)
524 module->remove(cell);
525
526 for (auto wire : module->wires())
527 {
528 if (wire->attributes.count("\\init") == 0)
529 continue;
530
531 SigSpec initsig = sigmap(wire);
532 Const &initval = wire->attributes.at("\\init");
533
534 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
535 if (remove_init.count(initsig[i]))
536 initval[i] = State::Sx;
537
538 if (SigSpec(initval).is_fully_undef())
539 wire->attributes.erase("\\init");
540 }
541
542 remove_cells.clear();
543 sigbit_chain_next.clear();
544 sigbit_chain_prev.clear();
545 chain_start_cells.clear();
546 }
547
548 ShregmapWorker(Module *module, const ShregmapOptions &opts) :
549 module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0)
550 {
551 if (opts.tech)
552 opts.tech->init(module, sigmap);
553
554 make_sigbit_chain_next_prev();
555 find_chain_start_cells();
556
557 for (auto c : chain_start_cells) {
558 vector<Cell*> chain = create_chain(c);
559 process_chain(chain);
560 }
561
562 cleanup();
563 }
564 };
565
566 struct ShregmapPass : public Pass {
567 ShregmapPass() : Pass("shregmap", "map shift registers") { }
568 void help() YS_OVERRIDE
569 {
570 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
571 log("\n");
572 log(" shregmap [options] [selection]\n");
573 log("\n");
574 log("This pass converts chains of $_DFF_[NP]_ gates to target specific shift register\n");
575 log("primitives. The generated shift register will be of type $__SHREG_DFF_[NP]_ and\n");
576 log("will use the same interface as the original $_DFF_*_ cells. The cell parameter\n");
577 log("'DEPTH' will contain the depth of the shift register. Use a target-specific\n");
578 log("'techmap' map file to convert those cells to the actual target cells.\n");
579 log("\n");
580 log(" -minlen N\n");
581 log(" minimum length of shift register (default = 2)\n");
582 log(" (this is the length after -keep_before and -keep_after)\n");
583 log("\n");
584 log(" -maxlen N\n");
585 log(" maximum length of shift register (default = no limit)\n");
586 log(" larger chains will be mapped to multiple shift register instances\n");
587 log("\n");
588 log(" -keep_before N\n");
589 log(" number of DFFs to keep before the shift register (default = 0)\n");
590 log("\n");
591 log(" -keep_after N\n");
592 log(" number of DFFs to keep after the shift register (default = 0)\n");
593 log("\n");
594 log(" -clkpol pos|neg|any\n");
595 log(" limit match to only positive or negative edge clocks. (default = any)\n");
596 log("\n");
597 log(" -enpol pos|neg|none|any_or_none|any\n");
598 log(" limit match to FFs with the specified enable polarity. (default = none)\n");
599 log("\n");
600 log(" -match <cell_type>[:<d_port_name>:<q_port_name>]\n");
601 log(" match the specified cells instead of $_DFF_N_ and $_DFF_P_. If\n");
602 log(" ':<d_port_name>:<q_port_name>' is omitted then 'D' and 'Q' is used\n");
603 log(" by default. E.g. the option '-clkpol pos' is just an alias for\n");
604 log(" '-match $_DFF_P_', which is an alias for '-match $_DFF_P_:D:Q'.\n");
605 log("\n");
606 log(" -params\n");
607 log(" instead of encoding the clock and enable polarity in the cell name by\n");
608 log(" deriving from the original cell name, simply name all generated cells\n");
609 log(" $__SHREG_ and use CLKPOL and ENPOL parameters. An ENPOL value of 2 is\n");
610 log(" used to denote cells without enable input. The ENPOL parameter is\n");
611 log(" omitted when '-enpol none' (or no -enpol option) is passed.\n");
612 log("\n");
613 log(" -zinit\n");
614 log(" assume the shift register is automatically zero-initialized, so it\n");
615 log(" becomes legal to merge zero initialized FFs into the shift register.\n");
616 log("\n");
617 log(" -init\n");
618 log(" map initialized registers to the shift reg, add an INIT parameter to\n");
619 log(" generated cells with the initialization value. (first bit to shift out\n");
620 log(" in LSB position)\n");
621 log("\n");
622 log(" -tech greenpak4\n");
623 log(" map to greenpak4 shift registers.\n");
624 log("\n");
625 log(" -tech xilinx\n");
626 log(" map to xilinx dynamic-length shift registers.\n");
627 log("\n");
628 }
629 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
630 {
631 ShregmapOptions opts;
632 string clkpol, enpol;
633
634 log_header(design, "Executing SHREGMAP pass (map shift registers).\n");
635
636 size_t argidx;
637 for (argidx = 1; argidx < args.size(); argidx++)
638 {
639 if (args[argidx] == "-clkpol" && argidx+1 < args.size()) {
640 clkpol = args[++argidx];
641 continue;
642 }
643 if (args[argidx] == "-enpol" && argidx+1 < args.size()) {
644 enpol = args[++argidx];
645 continue;
646 }
647 if (args[argidx] == "-match" && argidx+1 < args.size()) {
648 vector<string> match_args = split_tokens(args[++argidx], ":");
649 if (GetSize(match_args) < 2)
650 match_args.push_back("D");
651 if (GetSize(match_args) < 3)
652 match_args.push_back("Q");
653 IdString id_cell_type(RTLIL::escape_id(match_args[0]));
654 IdString id_d_port_name(RTLIL::escape_id(match_args[1]));
655 IdString id_q_port_name(RTLIL::escape_id(match_args[2]));
656 opts.ffcells[id_cell_type] = make_pair(id_d_port_name, id_q_port_name);
657 continue;
658 }
659 if (args[argidx] == "-minlen" && argidx+1 < args.size()) {
660 opts.minlen = atoi(args[++argidx].c_str());
661 continue;
662 }
663 if (args[argidx] == "-maxlen" && argidx+1 < args.size()) {
664 opts.maxlen = atoi(args[++argidx].c_str());
665 continue;
666 }
667 if (args[argidx] == "-keep_before" && argidx+1 < args.size()) {
668 opts.keep_before = atoi(args[++argidx].c_str());
669 continue;
670 }
671 if (args[argidx] == "-keep_after" && argidx+1 < args.size()) {
672 opts.keep_after = atoi(args[++argidx].c_str());
673 continue;
674 }
675 if (args[argidx] == "-tech" && argidx+1 < args.size() && opts.tech == nullptr) {
676 string tech = args[++argidx];
677 if (tech == "greenpak4") {
678 clkpol = "pos";
679 opts.zinit = true;
680 opts.tech = new ShregmapTechGreenpak4;
681 }
682 else if (tech == "xilinx_dynamic") {
683 opts.init = true;
684 opts.ffcells["$_DFF_P_"] = make_pair(IdString("\\D"), IdString("\\Q"));
685 opts.ffcells["$_DFF_N_"] = make_pair(IdString("\\D"), IdString("\\Q"));
686 opts.ffcells["$_DFFE_PP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
687 opts.ffcells["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
688 opts.ffcells["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
689 opts.ffcells["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
690 opts.tech = new ShregmapTechXilinx7Dynamic(opts);
691 } else {
692 argidx--;
693 break;
694 }
695 continue;
696 }
697 if (args[argidx] == "-zinit") {
698 opts.zinit = true;
699 continue;
700 }
701 if (args[argidx] == "-init") {
702 opts.init = true;
703 continue;
704 }
705 if (args[argidx] == "-params") {
706 opts.params = true;
707 continue;
708 }
709 break;
710 }
711 extra_args(args, argidx, design);
712
713 if (opts.zinit && opts.init)
714 log_cmd_error("Options -zinit and -init are exclusive!\n");
715
716 if (opts.ffcells.empty())
717 {
718 bool clk_pos = clkpol == "" || clkpol == "pos" || clkpol == "any";
719 bool clk_neg = clkpol == "" || clkpol == "neg" || clkpol == "any";
720
721 bool en_none = enpol == "" || enpol == "none" || enpol == "any_or_none";
722 bool en_pos = enpol == "pos" || enpol == "any" || enpol == "any_or_none";
723 bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none";
724
725 if (clk_pos && en_none)
726 opts.ffcells["$_DFF_P_"] = make_pair(IdString("\\D"), IdString("\\Q"));
727 if (clk_neg && en_none)
728 opts.ffcells["$_DFF_N_"] = make_pair(IdString("\\D"), IdString("\\Q"));
729
730 if (clk_pos && en_pos)
731 opts.ffcells["$_DFFE_PP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
732 if (clk_pos && en_neg)
733 opts.ffcells["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
734
735 if (clk_neg && en_pos)
736 opts.ffcells["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
737 if (clk_neg && en_neg)
738 opts.ffcells["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
739
740 if (en_pos || en_neg)
741 opts.ffe = true;
742 }
743 else
744 {
745 if (!clkpol.empty())
746 log_cmd_error("Options -clkpol and -match are exclusive!\n");
747 if (!enpol.empty())
748 log_cmd_error("Options -enpol and -match are exclusive!\n");
749 if (opts.params)
750 log_cmd_error("Options -params and -match are exclusive!\n");
751 }
752
753 int dff_count = 0;
754 int shreg_count = 0;
755
756 for (auto module : design->selected_modules()) {
757 ShregmapWorker worker(module, opts);
758 dff_count += worker.dff_count;
759 shreg_count += worker.shreg_count;
760 }
761
762 log("Converted %d dff cells into %d shift registers.\n", dff_count, shreg_count);
763
764 if (opts.tech != nullptr) {
765 delete opts.tech;
766 opts.tech = nullptr;
767 }
768 }
769 } ShregmapPass;
770
771 PRIVATE_NAMESPACE_END