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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
[yosys.git] / passes / techmap / shregmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22
23 USING_YOSYS_NAMESPACE
24 PRIVATE_NAMESPACE_BEGIN
25
26 struct ShregmapTech
27 {
28 virtual ~ShregmapTech() { }
29 virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {}
30 virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {}
31 virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) = 0;
32 virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) = 0;
33 };
34
35 struct ShregmapOptions
36 {
37 int minlen, maxlen;
38 int keep_before, keep_after;
39 bool zinit, init, params, ffe;
40 dict<IdString, pair<IdString, IdString>> ffcells;
41 ShregmapTech *tech;
42
43 ShregmapOptions()
44 {
45 minlen = 2;
46 maxlen = 0;
47 keep_before = 0;
48 keep_after = 0;
49 zinit = false;
50 init = false;
51 params = false;
52 ffe = false;
53 tech = nullptr;
54 }
55 };
56
57 struct ShregmapTechGreenpak4 : ShregmapTech
58 {
59 bool analyze(vector<int> &taps, const vector<SigBit> &/*qbits*/)
60 {
61 if (GetSize(taps) > 2 && taps[0] == 0 && taps[2] < 17) {
62 taps.clear();
63 return true;
64 }
65
66 if (GetSize(taps) > 2)
67 return false;
68
69 if (taps.back() > 16) return false;
70
71 return true;
72 }
73
74 bool fixup(Cell *cell, dict<int, SigBit> &taps)
75 {
76 auto D = cell->getPort("\\D");
77 auto C = cell->getPort("\\C");
78
79 auto newcell = cell->module->addCell(NEW_ID, "\\GP_SHREG");
80 newcell->setPort("\\nRST", State::S1);
81 newcell->setPort("\\CLK", C);
82 newcell->setPort("\\IN", D);
83
84 int i = 0;
85 for (auto tap : taps) {
86 newcell->setPort(i ? "\\OUTB" : "\\OUTA", tap.second);
87 newcell->setParam(i ? "\\OUTB_TAP" : "\\OUTA_TAP", tap.first + 1);
88 i++;
89 }
90
91 cell->setParam("\\OUTA_INVERT", 0);
92 return false;
93 }
94 };
95
96 struct ShregmapTechXilinx7 : ShregmapTech
97 {
98 dict<SigBit, std::tuple<Cell*,int,int>> sigbit_to_shiftx_offset;
99 const ShregmapOptions &opts;
100
101 ShregmapTechXilinx7(const ShregmapOptions &opts) : opts(opts) {}
102
103 virtual void init(const Module* module, const SigMap &sigmap) override
104 {
105 for (const auto &i : module->cells_) {
106 auto cell = i.second;
107 if (cell->type == "$shiftx") {
108 if (cell->getParam("\\Y_WIDTH") != 1) continue;
109 int j = 0;
110 for (auto bit : sigmap(cell->getPort("\\A")))
111 sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, j++, 0);
112 log_assert(j == cell->getParam("\\A_WIDTH").as_int());
113 }
114 else if (cell->type == "$mux") {
115 int j = 0;
116 for (auto bit : sigmap(cell->getPort("\\A")))
117 sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 0, j++);
118 j = 0;
119 for (auto bit : sigmap(cell->getPort("\\B")))
120 sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 1, j++);
121 }
122 }
123 }
124
125 virtual void non_chain_user(const SigBit &bit, const Cell *cell, IdString port) override
126 {
127 auto it = sigbit_to_shiftx_offset.find(bit);
128 if (it == sigbit_to_shiftx_offset.end())
129 return;
130 if (cell) {
131 if (cell->type == "$shiftx" && port == "\\A")
132 return;
133 if (cell->type == "$mux" && (port == "\\A" || port == "\\B"))
134 return;
135 }
136 sigbit_to_shiftx_offset.erase(it);
137 }
138
139 virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) override
140 {
141 if (GetSize(taps) == 1)
142 return taps[0] >= opts.minlen-1 && sigbit_to_shiftx_offset.count(qbits[0]);
143
144 if (taps.back() < opts.minlen-1)
145 return false;
146
147 Cell *shiftx = nullptr;
148 int group = 0;
149 for (int i = 0; i < GetSize(taps); ++i) {
150 auto it = sigbit_to_shiftx_offset.find(qbits[i]);
151 if (it == sigbit_to_shiftx_offset.end())
152 return false;
153
154 // Check taps are sequential
155 if (i != taps[i])
156 return false;
157 // Check taps are not connected to a shift register,
158 // or sequential to the same shift register
159 if (i == 0) {
160 int offset;
161 std::tie(shiftx,offset,group) = it->second;
162 if (offset != i)
163 return false;
164 }
165 else {
166 Cell *shiftx_ = std::get<0>(it->second);
167 if (shiftx_ != shiftx)
168 return false;
169 int offset = std::get<1>(it->second);
170 if (offset != i)
171 return false;
172 int group_ = std::get<2>(it->second);
173 if (group_ != group)
174 return false;
175 }
176 }
177 log_assert(shiftx);
178
179 // Only map if $shiftx exclusively covers the shift register
180 if (shiftx->type == "$shiftx") {
181 if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int())
182 return false;
183 }
184 else if (shiftx->type == "$mux") {
185 if (GetSize(taps) != 2)
186 return false;
187 }
188 else log_abort();
189
190 return true;
191 }
192
193 virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) override
194 {
195 const auto &tap = *taps.begin();
196 auto bit = tap.second;
197
198 auto it = sigbit_to_shiftx_offset.find(bit);
199 log_assert(it != sigbit_to_shiftx_offset.end());
200
201 auto newcell = cell->module->addCell(NEW_ID, "$__XILINX_SHREG_");
202 newcell->set_src_attribute(cell->get_src_attribute());
203 newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH"));
204 newcell->setParam("\\INIT", cell->getParam("\\INIT"));
205 newcell->setParam("\\CLKPOL", cell->getParam("\\CLKPOL"));
206 newcell->setParam("\\ENPOL", cell->getParam("\\ENPOL"));
207
208 newcell->setPort("\\C", cell->getPort("\\C"));
209 newcell->setPort("\\D", cell->getPort("\\D"));
210 if (cell->hasPort("\\E"))
211 newcell->setPort("\\E", cell->getPort("\\E"));
212
213 Cell* shiftx = std::get<0>(it->second);
214 RTLIL::SigSpec l_wire, q_wire;
215 if (shiftx->type == "$shiftx") {
216 l_wire = shiftx->getPort("\\B");
217 q_wire = shiftx->getPort("\\Y");
218 shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
219 }
220 else if (shiftx->type == "$mux") {
221 l_wire = shiftx->getPort("\\S");
222 q_wire = shiftx->getPort("\\Y");
223 shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
224 }
225 else log_abort();
226
227 newcell->setPort("\\Q", q_wire);
228 newcell->setPort("\\L", l_wire);
229
230 return false;
231 }
232 };
233
234
235 struct ShregmapWorker
236 {
237 Module *module;
238 SigMap sigmap;
239
240 const ShregmapOptions &opts;
241 int dff_count, shreg_count;
242
243 pool<Cell*> remove_cells;
244 pool<SigBit> remove_init;
245
246 dict<SigBit, bool> sigbit_init;
247 dict<SigBit, Cell*> sigbit_chain_next;
248 dict<SigBit, Cell*> sigbit_chain_prev;
249 pool<SigBit> sigbit_with_non_chain_users;
250 pool<Cell*> chain_start_cells;
251
252 void make_sigbit_chain_next_prev()
253 {
254 for (auto wire : module->wires())
255 {
256 if (wire->port_output || wire->get_bool_attribute("\\keep")) {
257 for (auto bit : sigmap(wire)) {
258 sigbit_with_non_chain_users.insert(bit);
259 if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {});
260 }
261 }
262
263 if (wire->attributes.count("\\init")) {
264 SigSpec initsig = sigmap(wire);
265 Const initval = wire->attributes.at("\\init");
266 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
267 if (initval[i] == State::S0 && !opts.zinit)
268 sigbit_init[initsig[i]] = false;
269 else if (initval[i] == State::S1)
270 sigbit_init[initsig[i]] = true;
271 }
272 }
273
274 for (auto cell : module->cells())
275 {
276 if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute("\\keep"))
277 {
278 IdString d_port = opts.ffcells.at(cell->type).first;
279 IdString q_port = opts.ffcells.at(cell->type).second;
280
281 SigBit d_bit = sigmap(cell->getPort(d_port).as_bit());
282 SigBit q_bit = sigmap(cell->getPort(q_port).as_bit());
283
284 if (opts.init || sigbit_init.count(q_bit) == 0)
285 {
286 if (sigbit_chain_next.count(d_bit)) {
287 sigbit_with_non_chain_users.insert(d_bit);
288 } else
289 sigbit_chain_next[d_bit] = cell;
290
291 sigbit_chain_prev[q_bit] = cell;
292 continue;
293 }
294 }
295
296 for (auto conn : cell->connections())
297 if (cell->input(conn.first))
298 for (auto bit : sigmap(conn.second)) {
299 sigbit_with_non_chain_users.insert(bit);
300 if (opts.tech) opts.tech->non_chain_user(bit, cell, conn.first);
301 }
302 }
303 }
304
305 void find_chain_start_cells()
306 {
307 for (auto it : sigbit_chain_next)
308 {
309 if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first))
310 goto start_cell;
311
312 if (sigbit_chain_prev.count(it.first) != 0)
313 {
314 Cell *c1 = sigbit_chain_prev.at(it.first);
315 Cell *c2 = it.second;
316
317 if (c1->type != c2->type)
318 goto start_cell;
319
320 if (c1->parameters != c2->parameters)
321 goto start_cell;
322
323 IdString d_port = opts.ffcells.at(c1->type).first;
324 IdString q_port = opts.ffcells.at(c1->type).second;
325
326 auto c1_conn = c1->connections();
327 auto c2_conn = c1->connections();
328
329 c1_conn.erase(d_port);
330 c1_conn.erase(q_port);
331
332 c2_conn.erase(d_port);
333 c2_conn.erase(q_port);
334
335 if (c1_conn != c2_conn)
336 goto start_cell;
337
338 continue;
339 }
340
341 start_cell:
342 chain_start_cells.insert(it.second);
343 }
344 }
345
346 vector<Cell*> create_chain(Cell *start_cell)
347 {
348 vector<Cell*> chain;
349
350 Cell *c = start_cell;
351 while (c != nullptr)
352 {
353 chain.push_back(c);
354
355 IdString q_port = opts.ffcells.at(c->type).second;
356 SigBit q_bit = sigmap(c->getPort(q_port).as_bit());
357
358 if (sigbit_chain_next.count(q_bit) == 0)
359 break;
360
361 c = sigbit_chain_next.at(q_bit);
362 if (chain_start_cells.count(c) != 0)
363 break;
364 }
365
366 return chain;
367 }
368
369 void process_chain(vector<Cell*> &chain)
370 {
371 if (GetSize(chain) < opts.keep_before + opts.minlen + opts.keep_after)
372 return;
373
374 int cursor = opts.keep_before;
375 while (cursor < GetSize(chain) - opts.keep_after)
376 {
377 int depth = GetSize(chain) - opts.keep_after - cursor;
378
379 if (opts.maxlen > 0)
380 depth = std::min(opts.maxlen, depth);
381
382 Cell *first_cell = chain[cursor];
383 IdString q_port = opts.ffcells.at(first_cell->type).second;
384 dict<int, SigBit> taps_dict;
385
386 if (opts.tech)
387 {
388 vector<SigBit> qbits;
389 vector<int> taps;
390
391 for (int i = 0; i < depth; i++)
392 {
393 Cell *cell = chain[cursor+i];
394 auto qbit = sigmap(cell->getPort(q_port));
395 qbits.push_back(qbit);
396
397 if (sigbit_with_non_chain_users.count(qbit))
398 taps.push_back(i);
399 }
400
401 while (depth > 0)
402 {
403 if (taps.empty() || taps.back() < depth-1)
404 taps.push_back(depth-1);
405
406 if (opts.tech->analyze(taps, qbits))
407 break;
408
409 taps.pop_back();
410 depth--;
411 }
412
413 depth = 0;
414 for (auto tap : taps) {
415 taps_dict[tap] = qbits.at(tap);
416 log_assert(depth < tap+1);
417 depth = tap+1;
418 }
419 }
420
421 if (depth < 2) {
422 cursor++;
423 continue;
424 }
425
426 Cell *last_cell = chain[cursor+depth-1];
427
428 log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n",
429 log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), depth);
430
431 dff_count += depth;
432 shreg_count += 1;
433
434 string shreg_cell_type_str = "$__SHREG";
435 if (opts.params) {
436 shreg_cell_type_str += "_";
437 } else {
438 if (first_cell->type[1] != '_')
439 shreg_cell_type_str += "_";
440 shreg_cell_type_str += first_cell->type.substr(1);
441 }
442
443 if (opts.init) {
444 vector<State> initval;
445 for (int i = depth-1; i >= 0; i--) {
446 SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
447 if (sigbit_init.count(bit) == 0)
448 initval.push_back(State::Sx);
449 else if (sigbit_init.at(bit))
450 initval.push_back(State::S1);
451 else
452 initval.push_back(State::S0);
453 remove_init.insert(bit);
454 }
455 first_cell->setParam("\\INIT", initval);
456 }
457
458 if (opts.zinit)
459 for (int i = depth-1; i >= 0; i--) {
460 SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
461 remove_init.insert(bit);
462 }
463
464 if (opts.params)
465 {
466 int param_clkpol = -1;
467 int param_enpol = 2;
468
469 if (first_cell->type == "$_DFF_N_") param_clkpol = 0;
470 if (first_cell->type == "$_DFF_P_") param_clkpol = 1;
471
472 if (first_cell->type == "$_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
473 if (first_cell->type == "$_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
474 if (first_cell->type == "$_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
475 if (first_cell->type == "$_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
476
477 log_assert(param_clkpol >= 0);
478 first_cell->setParam("\\CLKPOL", param_clkpol);
479 if (opts.ffe) first_cell->setParam("\\ENPOL", param_enpol);
480 }
481
482 first_cell->type = shreg_cell_type_str;
483 first_cell->setPort(q_port, last_cell->getPort(q_port));
484 first_cell->setParam("\\DEPTH", depth);
485
486 if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
487 remove_cells.insert(first_cell);
488
489 for (int i = 1; i < depth; i++)
490 remove_cells.insert(chain[cursor+i]);
491 cursor += depth;
492 }
493 }
494
495 void cleanup()
496 {
497 for (auto cell : remove_cells)
498 module->remove(cell);
499
500 for (auto wire : module->wires())
501 {
502 if (wire->attributes.count("\\init") == 0)
503 continue;
504
505 SigSpec initsig = sigmap(wire);
506 Const &initval = wire->attributes.at("\\init");
507
508 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
509 if (remove_init.count(initsig[i]))
510 initval[i] = State::Sx;
511
512 if (SigSpec(initval).is_fully_undef())
513 wire->attributes.erase("\\init");
514 }
515
516 remove_cells.clear();
517 sigbit_chain_next.clear();
518 sigbit_chain_prev.clear();
519 chain_start_cells.clear();
520 }
521
522 ShregmapWorker(Module *module, const ShregmapOptions &opts) :
523 module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0)
524 {
525 if (opts.tech)
526 opts.tech->init(module, sigmap);
527
528 make_sigbit_chain_next_prev();
529 find_chain_start_cells();
530
531 for (auto c : chain_start_cells) {
532 vector<Cell*> chain = create_chain(c);
533 process_chain(chain);
534 }
535
536 cleanup();
537 }
538 };
539
540 struct ShregmapPass : public Pass {
541 ShregmapPass() : Pass("shregmap", "map shift registers") { }
542 void help() YS_OVERRIDE
543 {
544 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
545 log("\n");
546 log(" shregmap [options] [selection]\n");
547 log("\n");
548 log("This pass converts chains of $_DFF_[NP]_ gates to target specific shift register\n");
549 log("primitives. The generated shift register will be of type $__SHREG_DFF_[NP]_ and\n");
550 log("will use the same interface as the original $_DFF_*_ cells. The cell parameter\n");
551 log("'DEPTH' will contain the depth of the shift register. Use a target-specific\n");
552 log("'techmap' map file to convert those cells to the actual target cells.\n");
553 log("\n");
554 log(" -minlen N\n");
555 log(" minimum length of shift register (default = 2)\n");
556 log(" (this is the length after -keep_before and -keep_after)\n");
557 log("\n");
558 log(" -maxlen N\n");
559 log(" maximum length of shift register (default = no limit)\n");
560 log(" larger chains will be mapped to multiple shift register instances\n");
561 log("\n");
562 log(" -keep_before N\n");
563 log(" number of DFFs to keep before the shift register (default = 0)\n");
564 log("\n");
565 log(" -keep_after N\n");
566 log(" number of DFFs to keep after the shift register (default = 0)\n");
567 log("\n");
568 log(" -clkpol pos|neg|any\n");
569 log(" limit match to only positive or negative edge clocks. (default = any)\n");
570 log("\n");
571 log(" -enpol pos|neg|none|any_or_none|any\n");
572 log(" limit match to FFs with the specified enable polarity. (default = none)\n");
573 log("\n");
574 log(" -match <cell_type>[:<d_port_name>:<q_port_name>]\n");
575 log(" match the specified cells instead of $_DFF_N_ and $_DFF_P_. If\n");
576 log(" ':<d_port_name>:<q_port_name>' is omitted then 'D' and 'Q' is used\n");
577 log(" by default. E.g. the option '-clkpol pos' is just an alias for\n");
578 log(" '-match $_DFF_P_', which is an alias for '-match $_DFF_P_:D:Q'.\n");
579 log("\n");
580 log(" -params\n");
581 log(" instead of encoding the clock and enable polarity in the cell name by\n");
582 log(" deriving from the original cell name, simply name all generated cells\n");
583 log(" $__SHREG_ and use CLKPOL and ENPOL parameters. An ENPOL value of 2 is\n");
584 log(" used to denote cells without enable input. The ENPOL parameter is\n");
585 log(" omitted when '-enpol none' (or no -enpol option) is passed.\n");
586 log("\n");
587 log(" -zinit\n");
588 log(" assume the shift register is automatically zero-initialized, so it\n");
589 log(" becomes legal to merge zero initialized FFs into the shift register.\n");
590 log("\n");
591 log(" -init\n");
592 log(" map initialized registers to the shift reg, add an INIT parameter to\n");
593 log(" generated cells with the initialization value. (first bit to shift out\n");
594 log(" in LSB position)\n");
595 log("\n");
596 log(" -tech greenpak4\n");
597 log(" map to greenpak4 shift registers.\n");
598 log("\n");
599 }
600 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
601 {
602 ShregmapOptions opts;
603 string clkpol, enpol;
604
605 log_header(design, "Executing SHREGMAP pass (map shift registers).\n");
606
607 size_t argidx;
608 for (argidx = 1; argidx < args.size(); argidx++)
609 {
610 if (args[argidx] == "-clkpol" && argidx+1 < args.size()) {
611 clkpol = args[++argidx];
612 continue;
613 }
614 if (args[argidx] == "-enpol" && argidx+1 < args.size()) {
615 enpol = args[++argidx];
616 continue;
617 }
618 if (args[argidx] == "-match" && argidx+1 < args.size()) {
619 vector<string> match_args = split_tokens(args[++argidx], ":");
620 if (GetSize(match_args) < 2)
621 match_args.push_back("D");
622 if (GetSize(match_args) < 3)
623 match_args.push_back("Q");
624 IdString id_cell_type(RTLIL::escape_id(match_args[0]));
625 IdString id_d_port_name(RTLIL::escape_id(match_args[1]));
626 IdString id_q_port_name(RTLIL::escape_id(match_args[2]));
627 opts.ffcells[id_cell_type] = make_pair(id_d_port_name, id_q_port_name);
628 continue;
629 }
630 if (args[argidx] == "-minlen" && argidx+1 < args.size()) {
631 opts.minlen = atoi(args[++argidx].c_str());
632 continue;
633 }
634 if (args[argidx] == "-maxlen" && argidx+1 < args.size()) {
635 opts.maxlen = atoi(args[++argidx].c_str());
636 continue;
637 }
638 if (args[argidx] == "-keep_before" && argidx+1 < args.size()) {
639 opts.keep_before = atoi(args[++argidx].c_str());
640 continue;
641 }
642 if (args[argidx] == "-keep_after" && argidx+1 < args.size()) {
643 opts.keep_after = atoi(args[++argidx].c_str());
644 continue;
645 }
646 if (args[argidx] == "-tech" && argidx+1 < args.size() && opts.tech == nullptr) {
647 string tech = args[++argidx];
648 if (tech == "greenpak4") {
649 clkpol = "pos";
650 opts.zinit = true;
651 opts.tech = new ShregmapTechGreenpak4;
652 }
653 else if (tech == "xilinx") {
654 opts.init = true;
655 opts.params = true;
656 enpol = "any_or_none";
657 opts.tech = new ShregmapTechXilinx7(opts);
658 } else {
659 argidx--;
660 break;
661 }
662 continue;
663 }
664 if (args[argidx] == "-zinit") {
665 opts.zinit = true;
666 continue;
667 }
668 if (args[argidx] == "-init") {
669 opts.init = true;
670 continue;
671 }
672 if (args[argidx] == "-params") {
673 opts.params = true;
674 continue;
675 }
676 break;
677 }
678 extra_args(args, argidx, design);
679
680 if (opts.zinit && opts.init)
681 log_cmd_error("Options -zinit and -init are exclusive!\n");
682
683 if (opts.ffcells.empty())
684 {
685 bool clk_pos = clkpol == "" || clkpol == "pos" || clkpol == "any";
686 bool clk_neg = clkpol == "" || clkpol == "neg" || clkpol == "any";
687
688 bool en_none = enpol == "" || enpol == "none" || enpol == "any_or_none";
689 bool en_pos = enpol == "pos" || enpol == "any" || enpol == "any_or_none";
690 bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none";
691
692 if (clk_pos && en_none)
693 opts.ffcells["$_DFF_P_"] = make_pair(IdString("\\D"), IdString("\\Q"));
694 if (clk_neg && en_none)
695 opts.ffcells["$_DFF_N_"] = make_pair(IdString("\\D"), IdString("\\Q"));
696
697 if (clk_pos && en_pos)
698 opts.ffcells["$_DFFE_PP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
699 if (clk_pos && en_neg)
700 opts.ffcells["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
701
702 if (clk_neg && en_pos)
703 opts.ffcells["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
704 if (clk_neg && en_neg)
705 opts.ffcells["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
706
707 if (en_pos || en_neg)
708 opts.ffe = true;
709 }
710 else
711 {
712 if (!clkpol.empty())
713 log_cmd_error("Options -clkpol and -match are exclusive!\n");
714 if (!enpol.empty())
715 log_cmd_error("Options -enpol and -match are exclusive!\n");
716 if (opts.params)
717 log_cmd_error("Options -params and -match are exclusive!\n");
718 }
719
720 int dff_count = 0;
721 int shreg_count = 0;
722
723 for (auto module : design->selected_modules()) {
724 ShregmapWorker worker(module, opts);
725 dff_count += worker.dff_count;
726 shreg_count += worker.shreg_count;
727 }
728
729 log("Converted %d dff cells into %d shift registers.\n", dff_count, shreg_count);
730
731 if (opts.tech != nullptr) {
732 delete opts.tech;
733 opts.tech = nullptr;
734 }
735 }
736 } ShregmapPass;
737
738 PRIVATE_NAMESPACE_END