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Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
[yosys.git] / passes / techmap / shregmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22
23 USING_YOSYS_NAMESPACE
24 PRIVATE_NAMESPACE_BEGIN
25
26 struct ShregmapTech
27 {
28 virtual ~ShregmapTech() { }
29 virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {}
30 virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {}
31 virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) = 0;
32 virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) = 0;
33 };
34
35 struct ShregmapOptions
36 {
37 int minlen, maxlen;
38 int keep_before, keep_after;
39 bool zinit, init, params, ffe;
40 dict<IdString, pair<IdString, IdString>> ffcells;
41 ShregmapTech *tech;
42
43 ShregmapOptions()
44 {
45 minlen = 2;
46 maxlen = 0;
47 keep_before = 0;
48 keep_after = 0;
49 zinit = false;
50 init = false;
51 params = false;
52 ffe = false;
53 tech = nullptr;
54 }
55 };
56
57 struct ShregmapTechGreenpak4 : ShregmapTech
58 {
59 bool analyze(vector<int> &taps, const vector<SigBit> &/*qbits*/)
60 {
61 if (GetSize(taps) > 2 && taps[0] == 0 && taps[2] < 17) {
62 taps.clear();
63 return true;
64 }
65
66 if (GetSize(taps) > 2)
67 return false;
68
69 if (taps.back() > 16) return false;
70
71 return true;
72 }
73
74 bool fixup(Cell *cell, dict<int, SigBit> &taps)
75 {
76 auto D = cell->getPort("\\D");
77 auto C = cell->getPort("\\C");
78
79 auto newcell = cell->module->addCell(NEW_ID, "\\GP_SHREG");
80 newcell->setPort("\\nRST", State::S1);
81 newcell->setPort("\\CLK", C);
82 newcell->setPort("\\IN", D);
83
84 int i = 0;
85 for (auto tap : taps) {
86 newcell->setPort(i ? "\\OUTB" : "\\OUTA", tap.second);
87 newcell->setParam(i ? "\\OUTB_TAP" : "\\OUTA_TAP", tap.first + 1);
88 i++;
89 }
90
91 cell->setParam("\\OUTA_INVERT", 0);
92 return false;
93 }
94 };
95
96 struct ShregmapTechXilinx7 : ShregmapTech
97 {
98 dict<SigBit, std::tuple<Cell*,int,int>> sigbit_to_shiftx_offset;
99 const ShregmapOptions &opts;
100
101 ShregmapTechXilinx7(const ShregmapOptions &opts) : opts(opts) {}
102
103 virtual void init(const Module* module, const SigMap &sigmap) override
104 {
105 for (const auto &i : module->cells_) {
106 auto cell = i.second;
107 if (cell->type == "$shiftx") {
108 if (cell->getParam("\\Y_WIDTH") != 1) continue;
109 int j = 0;
110 for (auto bit : sigmap(cell->getPort("\\A")))
111 sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, j++, 0);
112 log_assert(j == cell->getParam("\\A_WIDTH").as_int());
113 }
114 else if (cell->type == "$mux") {
115 int j = 0;
116 for (auto bit : sigmap(cell->getPort("\\A")))
117 sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 0, j++);
118 j = 0;
119 for (auto bit : sigmap(cell->getPort("\\B")))
120 sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 1, j++);
121 }
122 }
123 }
124
125 virtual void non_chain_user(const SigBit &bit, const Cell *cell, IdString port) override
126 {
127 auto it = sigbit_to_shiftx_offset.find(bit);
128 if (it == sigbit_to_shiftx_offset.end())
129 return;
130 if (cell) {
131 if (cell->type == "$shiftx" && port == "\\A")
132 return;
133 if (cell->type == "$mux" && (port == "\\A" || port == "\\B"))
134 return;
135 }
136 sigbit_to_shiftx_offset.erase(it);
137 }
138
139 virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) override
140 {
141 if (GetSize(taps) == 1)
142 return taps[0] >= opts.minlen-1 && sigbit_to_shiftx_offset.count(qbits[0]);
143
144 if (taps.back() < opts.minlen-1)
145 return false;
146
147 Cell *shiftx = nullptr;
148 int group = 0;
149 for (int i = 0; i < GetSize(taps); ++i) {
150 auto it = sigbit_to_shiftx_offset.find(qbits[i]);
151 if (it == sigbit_to_shiftx_offset.end())
152 return false;
153
154 // Check taps are sequential
155 if (i != taps[i])
156 return false;
157 // Check taps are not connected to a shift register,
158 // or sequential to the same shift register
159 if (i == 0) {
160 int offset;
161 std::tie(shiftx,offset,group) = it->second;
162 if (offset != i)
163 return false;
164 }
165 else {
166 Cell *shiftx_ = std::get<0>(it->second);
167 if (shiftx_ != shiftx)
168 return false;
169 int offset = std::get<1>(it->second);
170 if (offset != i)
171 return false;
172 int group_ = std::get<2>(it->second);
173 if (group_ != group)
174 return false;
175 }
176 }
177 log_assert(shiftx);
178
179 // Only map if $shiftx exclusively covers the shift register
180 if (shiftx->type == "$shiftx") {
181 if (GetSize(taps) > shiftx->getParam("\\A_WIDTH").as_int())
182 return false;
183 // Due to padding the most significant bits of A may be 1'bx,
184 // and if so, discount them
185 if (GetSize(taps) < shiftx->getParam("\\A_WIDTH").as_int()) {
186 const SigSpec A = shiftx->getPort("\\A");
187 const int A_width = shiftx->getParam("\\A_WIDTH").as_int();
188 for (int i = GetSize(taps); i < A_width; ++i)
189 if (A[i] != RTLIL::Sx) return false;
190 }
191 else if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int())
192 return false;
193 }
194 else if (shiftx->type == "$mux") {
195 if (GetSize(taps) != 2)
196 return false;
197 }
198 else log_abort();
199
200 return true;
201 }
202
203 virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) override
204 {
205 const auto &tap = *taps.begin();
206 auto bit = tap.second;
207
208 auto it = sigbit_to_shiftx_offset.find(bit);
209 log_assert(it != sigbit_to_shiftx_offset.end());
210
211 auto newcell = cell->module->addCell(NEW_ID, "$__XILINX_SHREG_");
212 newcell->set_src_attribute(cell->get_src_attribute());
213 newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH"));
214 newcell->setParam("\\INIT", cell->getParam("\\INIT"));
215 newcell->setParam("\\CLKPOL", cell->getParam("\\CLKPOL"));
216 newcell->setParam("\\ENPOL", cell->getParam("\\ENPOL"));
217
218 newcell->setPort("\\C", cell->getPort("\\C"));
219 newcell->setPort("\\D", cell->getPort("\\D"));
220 if (cell->hasPort("\\E"))
221 newcell->setPort("\\E", cell->getPort("\\E"));
222
223 Cell* shiftx = std::get<0>(it->second);
224 RTLIL::SigSpec l_wire, q_wire;
225 if (shiftx->type == "$shiftx") {
226 l_wire = shiftx->getPort("\\B");
227 q_wire = shiftx->getPort("\\Y");
228 shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
229 }
230 else if (shiftx->type == "$mux") {
231 l_wire = shiftx->getPort("\\S");
232 q_wire = shiftx->getPort("\\Y");
233 shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
234 }
235 else log_abort();
236
237 newcell->setPort("\\Q", q_wire);
238 newcell->setPort("\\L", l_wire);
239
240 return false;
241 }
242 };
243
244
245 struct ShregmapWorker
246 {
247 Module *module;
248 SigMap sigmap;
249
250 const ShregmapOptions &opts;
251 int dff_count, shreg_count;
252
253 pool<Cell*> remove_cells;
254 pool<SigBit> remove_init;
255
256 dict<SigBit, bool> sigbit_init;
257 dict<SigBit, Cell*> sigbit_chain_next;
258 dict<SigBit, Cell*> sigbit_chain_prev;
259 pool<SigBit> sigbit_with_non_chain_users;
260 pool<Cell*> chain_start_cells;
261
262 void make_sigbit_chain_next_prev()
263 {
264 for (auto wire : module->wires())
265 {
266 if (wire->port_output || wire->get_bool_attribute("\\keep")) {
267 for (auto bit : sigmap(wire)) {
268 sigbit_with_non_chain_users.insert(bit);
269 if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {});
270 }
271 }
272
273 if (wire->attributes.count("\\init")) {
274 SigSpec initsig = sigmap(wire);
275 Const initval = wire->attributes.at("\\init");
276 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
277 if (initval[i] == State::S0 && !opts.zinit)
278 sigbit_init[initsig[i]] = false;
279 else if (initval[i] == State::S1)
280 sigbit_init[initsig[i]] = true;
281 }
282 }
283
284 for (auto cell : module->cells())
285 {
286 if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute("\\keep"))
287 {
288 IdString d_port = opts.ffcells.at(cell->type).first;
289 IdString q_port = opts.ffcells.at(cell->type).second;
290
291 SigBit d_bit = sigmap(cell->getPort(d_port).as_bit());
292 SigBit q_bit = sigmap(cell->getPort(q_port).as_bit());
293
294 if (opts.init || sigbit_init.count(q_bit) == 0)
295 {
296 auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell));
297 if (!r.second)
298 sigbit_with_non_chain_users.insert(d_bit);
299
300 sigbit_chain_prev[q_bit] = cell;
301 continue;
302 }
303 }
304
305 for (auto conn : cell->connections())
306 if (cell->input(conn.first))
307 for (auto bit : sigmap(conn.second)) {
308 sigbit_with_non_chain_users.insert(bit);
309 if (opts.tech) opts.tech->non_chain_user(bit, cell, conn.first);
310 }
311 }
312 }
313
314 void find_chain_start_cells()
315 {
316 for (auto it : sigbit_chain_next)
317 {
318 Cell *c1, *c2 = it.second;
319
320 if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first))
321 goto start_cell;
322
323 c1 = sigbit_chain_prev.at(it.first, nullptr);
324 if (c1 != nullptr)
325 {
326 if (c1->type != c2->type)
327 goto start_cell;
328
329 if (c1->parameters != c2->parameters)
330 goto start_cell;
331
332 IdString d_port = opts.ffcells.at(c1->type).first;
333 IdString q_port = opts.ffcells.at(c1->type).second;
334
335 // If the previous cell's D has other non chain users,
336 // then it is possible that this previous cell could
337 // be a start of the chain
338 SigBit d_bit = sigmap(c1->getPort(d_port).as_bit());
339 if (sigbit_with_non_chain_users.count(d_bit)) {
340 c2 = c1;
341 goto start_cell;
342 }
343
344 auto c1_conn = c1->connections();
345 auto c2_conn = c1->connections();
346
347 c1_conn.erase(d_port);
348 c1_conn.erase(q_port);
349
350 c2_conn.erase(d_port);
351 c2_conn.erase(q_port);
352
353 if (c1_conn != c2_conn)
354 goto start_cell;
355
356 continue;
357 }
358
359 start_cell:
360 chain_start_cells.insert(c2);
361 }
362 }
363
364 vector<Cell*> create_chain(Cell *start_cell)
365 {
366 vector<Cell*> chain;
367
368 Cell *c = start_cell;
369 while (c != nullptr)
370 {
371 chain.push_back(c);
372
373 IdString q_port = opts.ffcells.at(c->type).second;
374 SigBit q_bit = sigmap(c->getPort(q_port).as_bit());
375
376 if (sigbit_chain_next.count(q_bit) == 0)
377 break;
378
379 c = sigbit_chain_next.at(q_bit);
380 if (chain_start_cells.count(c) != 0)
381 break;
382 }
383
384 return chain;
385 }
386
387 void process_chain(vector<Cell*> &chain)
388 {
389 if (GetSize(chain) < opts.keep_before + opts.minlen + opts.keep_after)
390 return;
391
392 int cursor = opts.keep_before;
393 while (cursor < GetSize(chain) - opts.keep_after)
394 {
395 int depth = GetSize(chain) - opts.keep_after - cursor;
396
397 if (opts.maxlen > 0)
398 depth = std::min(opts.maxlen, depth);
399
400 Cell *first_cell = chain[cursor];
401 IdString q_port = opts.ffcells.at(first_cell->type).second;
402 dict<int, SigBit> taps_dict;
403
404 if (opts.tech)
405 {
406 vector<SigBit> qbits;
407 vector<int> taps;
408
409 for (int i = 0; i < depth; i++)
410 {
411 Cell *cell = chain[cursor+i];
412 auto qbit = sigmap(cell->getPort(q_port));
413 qbits.push_back(qbit);
414
415 if (sigbit_with_non_chain_users.count(qbit))
416 taps.push_back(i);
417 }
418
419 while (depth > 0)
420 {
421 if (taps.empty() || taps.back() < depth-1)
422 taps.push_back(depth-1);
423
424 if (opts.tech->analyze(taps, qbits))
425 break;
426
427 taps.pop_back();
428 depth--;
429 }
430
431 depth = 0;
432 for (auto tap : taps) {
433 taps_dict[tap] = qbits.at(tap);
434 log_assert(depth < tap+1);
435 depth = tap+1;
436 }
437 }
438
439 if (depth < 2) {
440 cursor++;
441 continue;
442 }
443
444 Cell *last_cell = chain[cursor+depth-1];
445
446 log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n",
447 log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), depth);
448
449 dff_count += depth;
450 shreg_count += 1;
451
452 string shreg_cell_type_str = "$__SHREG";
453 if (opts.params) {
454 shreg_cell_type_str += "_";
455 } else {
456 if (first_cell->type[1] != '_')
457 shreg_cell_type_str += "_";
458 shreg_cell_type_str += first_cell->type.substr(1);
459 }
460
461 if (opts.init) {
462 vector<State> initval;
463 for (int i = depth-1; i >= 0; i--) {
464 SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
465 if (sigbit_init.count(bit) == 0)
466 initval.push_back(State::Sx);
467 else if (sigbit_init.at(bit))
468 initval.push_back(State::S1);
469 else
470 initval.push_back(State::S0);
471 remove_init.insert(bit);
472 }
473 first_cell->setParam("\\INIT", initval);
474 }
475
476 if (opts.zinit)
477 for (int i = depth-1; i >= 0; i--) {
478 SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
479 remove_init.insert(bit);
480 }
481
482 if (opts.params)
483 {
484 int param_clkpol = -1;
485 int param_enpol = 2;
486
487 if (first_cell->type == "$_DFF_N_") param_clkpol = 0;
488 if (first_cell->type == "$_DFF_P_") param_clkpol = 1;
489
490 if (first_cell->type == "$_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
491 if (first_cell->type == "$_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
492 if (first_cell->type == "$_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
493 if (first_cell->type == "$_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
494
495 log_assert(param_clkpol >= 0);
496 first_cell->setParam("\\CLKPOL", param_clkpol);
497 if (opts.ffe) first_cell->setParam("\\ENPOL", param_enpol);
498 }
499
500 first_cell->type = shreg_cell_type_str;
501 first_cell->setPort(q_port, last_cell->getPort(q_port));
502 first_cell->setParam("\\DEPTH", depth);
503
504 if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
505 remove_cells.insert(first_cell);
506
507 for (int i = 1; i < depth; i++)
508 remove_cells.insert(chain[cursor+i]);
509 cursor += depth;
510 }
511 }
512
513 void cleanup()
514 {
515 for (auto cell : remove_cells)
516 module->remove(cell);
517
518 for (auto wire : module->wires())
519 {
520 if (wire->attributes.count("\\init") == 0)
521 continue;
522
523 SigSpec initsig = sigmap(wire);
524 Const &initval = wire->attributes.at("\\init");
525
526 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
527 if (remove_init.count(initsig[i]))
528 initval[i] = State::Sx;
529
530 if (SigSpec(initval).is_fully_undef())
531 wire->attributes.erase("\\init");
532 }
533
534 remove_cells.clear();
535 sigbit_chain_next.clear();
536 sigbit_chain_prev.clear();
537 chain_start_cells.clear();
538 }
539
540 ShregmapWorker(Module *module, const ShregmapOptions &opts) :
541 module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0)
542 {
543 if (opts.tech)
544 opts.tech->init(module, sigmap);
545
546 make_sigbit_chain_next_prev();
547 find_chain_start_cells();
548
549 for (auto c : chain_start_cells) {
550 vector<Cell*> chain = create_chain(c);
551 process_chain(chain);
552 }
553
554 cleanup();
555 }
556 };
557
558 struct ShregmapPass : public Pass {
559 ShregmapPass() : Pass("shregmap", "map shift registers") { }
560 void help() YS_OVERRIDE
561 {
562 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
563 log("\n");
564 log(" shregmap [options] [selection]\n");
565 log("\n");
566 log("This pass converts chains of $_DFF_[NP]_ gates to target specific shift register\n");
567 log("primitives. The generated shift register will be of type $__SHREG_DFF_[NP]_ and\n");
568 log("will use the same interface as the original $_DFF_*_ cells. The cell parameter\n");
569 log("'DEPTH' will contain the depth of the shift register. Use a target-specific\n");
570 log("'techmap' map file to convert those cells to the actual target cells.\n");
571 log("\n");
572 log(" -minlen N\n");
573 log(" minimum length of shift register (default = 2)\n");
574 log(" (this is the length after -keep_before and -keep_after)\n");
575 log("\n");
576 log(" -maxlen N\n");
577 log(" maximum length of shift register (default = no limit)\n");
578 log(" larger chains will be mapped to multiple shift register instances\n");
579 log("\n");
580 log(" -keep_before N\n");
581 log(" number of DFFs to keep before the shift register (default = 0)\n");
582 log("\n");
583 log(" -keep_after N\n");
584 log(" number of DFFs to keep after the shift register (default = 0)\n");
585 log("\n");
586 log(" -clkpol pos|neg|any\n");
587 log(" limit match to only positive or negative edge clocks. (default = any)\n");
588 log("\n");
589 log(" -enpol pos|neg|none|any_or_none|any\n");
590 log(" limit match to FFs with the specified enable polarity. (default = none)\n");
591 log("\n");
592 log(" -match <cell_type>[:<d_port_name>:<q_port_name>]\n");
593 log(" match the specified cells instead of $_DFF_N_ and $_DFF_P_. If\n");
594 log(" ':<d_port_name>:<q_port_name>' is omitted then 'D' and 'Q' is used\n");
595 log(" by default. E.g. the option '-clkpol pos' is just an alias for\n");
596 log(" '-match $_DFF_P_', which is an alias for '-match $_DFF_P_:D:Q'.\n");
597 log("\n");
598 log(" -params\n");
599 log(" instead of encoding the clock and enable polarity in the cell name by\n");
600 log(" deriving from the original cell name, simply name all generated cells\n");
601 log(" $__SHREG_ and use CLKPOL and ENPOL parameters. An ENPOL value of 2 is\n");
602 log(" used to denote cells without enable input. The ENPOL parameter is\n");
603 log(" omitted when '-enpol none' (or no -enpol option) is passed.\n");
604 log("\n");
605 log(" -zinit\n");
606 log(" assume the shift register is automatically zero-initialized, so it\n");
607 log(" becomes legal to merge zero initialized FFs into the shift register.\n");
608 log("\n");
609 log(" -init\n");
610 log(" map initialized registers to the shift reg, add an INIT parameter to\n");
611 log(" generated cells with the initialization value. (first bit to shift out\n");
612 log(" in LSB position)\n");
613 log("\n");
614 log(" -tech greenpak4\n");
615 log(" map to greenpak4 shift registers.\n");
616 log("\n");
617 log(" -tech xilinx\n");
618 log(" map to xilinx dynamic-length shift registers.\n");
619 log("\n");
620 }
621 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
622 {
623 ShregmapOptions opts;
624 string clkpol, enpol;
625
626 log_header(design, "Executing SHREGMAP pass (map shift registers).\n");
627
628 size_t argidx;
629 for (argidx = 1; argidx < args.size(); argidx++)
630 {
631 if (args[argidx] == "-clkpol" && argidx+1 < args.size()) {
632 clkpol = args[++argidx];
633 continue;
634 }
635 if (args[argidx] == "-enpol" && argidx+1 < args.size()) {
636 enpol = args[++argidx];
637 continue;
638 }
639 if (args[argidx] == "-match" && argidx+1 < args.size()) {
640 vector<string> match_args = split_tokens(args[++argidx], ":");
641 if (GetSize(match_args) < 2)
642 match_args.push_back("D");
643 if (GetSize(match_args) < 3)
644 match_args.push_back("Q");
645 IdString id_cell_type(RTLIL::escape_id(match_args[0]));
646 IdString id_d_port_name(RTLIL::escape_id(match_args[1]));
647 IdString id_q_port_name(RTLIL::escape_id(match_args[2]));
648 opts.ffcells[id_cell_type] = make_pair(id_d_port_name, id_q_port_name);
649 continue;
650 }
651 if (args[argidx] == "-minlen" && argidx+1 < args.size()) {
652 opts.minlen = atoi(args[++argidx].c_str());
653 continue;
654 }
655 if (args[argidx] == "-maxlen" && argidx+1 < args.size()) {
656 opts.maxlen = atoi(args[++argidx].c_str());
657 continue;
658 }
659 if (args[argidx] == "-keep_before" && argidx+1 < args.size()) {
660 opts.keep_before = atoi(args[++argidx].c_str());
661 continue;
662 }
663 if (args[argidx] == "-keep_after" && argidx+1 < args.size()) {
664 opts.keep_after = atoi(args[++argidx].c_str());
665 continue;
666 }
667 if (args[argidx] == "-tech" && argidx+1 < args.size() && opts.tech == nullptr) {
668 string tech = args[++argidx];
669 if (tech == "greenpak4") {
670 clkpol = "pos";
671 opts.zinit = true;
672 opts.tech = new ShregmapTechGreenpak4;
673 }
674 else if (tech == "xilinx") {
675 opts.init = true;
676 opts.params = true;
677 enpol = "any_or_none";
678 opts.tech = new ShregmapTechXilinx7(opts);
679 } else {
680 argidx--;
681 break;
682 }
683 continue;
684 }
685 if (args[argidx] == "-zinit") {
686 opts.zinit = true;
687 continue;
688 }
689 if (args[argidx] == "-init") {
690 opts.init = true;
691 continue;
692 }
693 if (args[argidx] == "-params") {
694 opts.params = true;
695 continue;
696 }
697 break;
698 }
699 extra_args(args, argidx, design);
700
701 if (opts.zinit && opts.init)
702 log_cmd_error("Options -zinit and -init are exclusive!\n");
703
704 if (opts.ffcells.empty())
705 {
706 bool clk_pos = clkpol == "" || clkpol == "pos" || clkpol == "any";
707 bool clk_neg = clkpol == "" || clkpol == "neg" || clkpol == "any";
708
709 bool en_none = enpol == "" || enpol == "none" || enpol == "any_or_none";
710 bool en_pos = enpol == "pos" || enpol == "any" || enpol == "any_or_none";
711 bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none";
712
713 if (clk_pos && en_none)
714 opts.ffcells["$_DFF_P_"] = make_pair(IdString("\\D"), IdString("\\Q"));
715 if (clk_neg && en_none)
716 opts.ffcells["$_DFF_N_"] = make_pair(IdString("\\D"), IdString("\\Q"));
717
718 if (clk_pos && en_pos)
719 opts.ffcells["$_DFFE_PP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
720 if (clk_pos && en_neg)
721 opts.ffcells["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
722
723 if (clk_neg && en_pos)
724 opts.ffcells["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
725 if (clk_neg && en_neg)
726 opts.ffcells["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
727
728 if (en_pos || en_neg)
729 opts.ffe = true;
730 }
731 else
732 {
733 if (!clkpol.empty())
734 log_cmd_error("Options -clkpol and -match are exclusive!\n");
735 if (!enpol.empty())
736 log_cmd_error("Options -enpol and -match are exclusive!\n");
737 if (opts.params)
738 log_cmd_error("Options -params and -match are exclusive!\n");
739 }
740
741 int dff_count = 0;
742 int shreg_count = 0;
743
744 for (auto module : design->selected_modules()) {
745 ShregmapWorker worker(module, opts);
746 dff_count += worker.dff_count;
747 shreg_count += worker.shreg_count;
748 }
749
750 log("Converted %d dff cells into %d shift registers.\n", dff_count, shreg_count);
751
752 if (opts.tech != nullptr) {
753 delete opts.tech;
754 opts.tech = nullptr;
755 }
756 }
757 } ShregmapPass;
758
759 PRIVATE_NAMESPACE_END