2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
24 PRIVATE_NAMESPACE_BEGIN
28 virtual ~ShregmapTech() { }
29 virtual bool analyze(vector
<int> &taps
) = 0;
30 virtual bool fixup(Cell
*cell
, dict
<int, SigBit
> &taps
) = 0;
33 struct ShregmapOptions
36 int keep_before
, keep_after
;
37 bool zinit
, init
, params
, ffe
;
38 dict
<IdString
, pair
<IdString
, IdString
>> ffcells
;
55 struct ShregmapTechGreenpak4
: ShregmapTech
57 bool analyze(vector
<int> &taps
)
59 if (GetSize(taps
) > 2 && taps
[0] == 0 && taps
[2] < 17) {
64 if (GetSize(taps
) > 2)
67 if (taps
.back() > 16) return false;
72 bool fixup(Cell
*cell
, dict
<int, SigBit
> &taps
)
74 auto D
= cell
->getPort(ID(D
));
75 auto C
= cell
->getPort(ID(C
));
77 auto newcell
= cell
->module
->addCell(NEW_ID
, ID(GP_SHREG
));
78 newcell
->setPort(ID(nRST
), State::S1
);
79 newcell
->setPort(ID(CLK
), C
);
80 newcell
->setPort(ID(IN
), D
);
83 for (auto tap
: taps
) {
84 newcell
->setPort(i
? ID(OUTB
) : ID(OUTA
), tap
.second
);
85 newcell
->setParam(i
? ID(OUTB_TAP
) : ID(OUTA_TAP
), tap
.first
+ 1);
89 cell
->setParam(ID(OUTA_INVERT
), 0);
99 const ShregmapOptions
&opts
;
100 int dff_count
, shreg_count
;
102 pool
<Cell
*> remove_cells
;
103 pool
<SigBit
> remove_init
;
105 dict
<SigBit
, bool> sigbit_init
;
106 dict
<SigBit
, Cell
*> sigbit_chain_next
;
107 dict
<SigBit
, Cell
*> sigbit_chain_prev
;
108 pool
<SigBit
> sigbit_with_non_chain_users
;
109 pool
<Cell
*> chain_start_cells
;
111 void make_sigbit_chain_next_prev()
113 for (auto wire
: module
->wires())
115 if (wire
->port_output
|| wire
->get_bool_attribute(ID::keep
)) {
116 for (auto bit
: sigmap(wire
))
117 sigbit_with_non_chain_users
.insert(bit
);
120 if (wire
->attributes
.count(ID(init
))) {
121 SigSpec initsig
= sigmap(wire
);
122 Const initval
= wire
->attributes
.at(ID(init
));
123 for (int i
= 0; i
< GetSize(initsig
) && i
< GetSize(initval
); i
++)
124 if (initval
[i
] == State::S0
&& !opts
.zinit
)
125 sigbit_init
[initsig
[i
]] = false;
126 else if (initval
[i
] == State::S1
)
127 sigbit_init
[initsig
[i
]] = true;
131 for (auto cell
: module
->cells())
133 if (opts
.ffcells
.count(cell
->type
) && !cell
->get_bool_attribute(ID::keep
))
135 IdString d_port
= opts
.ffcells
.at(cell
->type
).first
;
136 IdString q_port
= opts
.ffcells
.at(cell
->type
).second
;
138 SigBit d_bit
= sigmap(cell
->getPort(d_port
).as_bit());
139 SigBit q_bit
= sigmap(cell
->getPort(q_port
).as_bit());
141 if (opts
.init
|| sigbit_init
.count(q_bit
) == 0)
143 auto r
= sigbit_chain_next
.insert(std::make_pair(d_bit
, cell
));
145 sigbit_with_non_chain_users
.insert(d_bit
);
147 sigbit_chain_prev
[q_bit
] = cell
;
152 for (auto conn
: cell
->connections())
153 if (cell
->input(conn
.first
))
154 for (auto bit
: sigmap(conn
.second
))
155 sigbit_with_non_chain_users
.insert(bit
);
159 void find_chain_start_cells()
161 for (auto it
: sigbit_chain_next
)
163 Cell
*c1
, *c2
= it
.second
;
165 if (opts
.tech
== nullptr && sigbit_with_non_chain_users
.count(it
.first
))
168 c1
= sigbit_chain_prev
.at(it
.first
, nullptr);
171 if (c1
->type
!= c2
->type
)
174 if (c1
->parameters
!= c2
->parameters
)
177 IdString d_port
= opts
.ffcells
.at(c1
->type
).first
;
178 IdString q_port
= opts
.ffcells
.at(c1
->type
).second
;
180 // If the previous cell's D has other non chain users,
181 // then it is possible that this previous cell could
182 // be a start of the chain
183 SigBit d_bit
= sigmap(c1
->getPort(d_port
).as_bit());
184 if (sigbit_with_non_chain_users
.count(d_bit
)) {
189 auto c1_conn
= c1
->connections();
190 auto c2_conn
= c1
->connections();
192 c1_conn
.erase(d_port
);
193 c1_conn
.erase(q_port
);
195 c2_conn
.erase(d_port
);
196 c2_conn
.erase(q_port
);
198 if (c1_conn
!= c2_conn
)
205 chain_start_cells
.insert(c2
);
209 vector
<Cell
*> create_chain(Cell
*start_cell
)
213 Cell
*c
= start_cell
;
218 IdString q_port
= opts
.ffcells
.at(c
->type
).second
;
219 SigBit q_bit
= sigmap(c
->getPort(q_port
).as_bit());
221 if (sigbit_chain_next
.count(q_bit
) == 0)
224 c
= sigbit_chain_next
.at(q_bit
);
225 if (chain_start_cells
.count(c
) != 0)
232 void process_chain(vector
<Cell
*> &chain
)
234 if (GetSize(chain
) < opts
.keep_before
+ opts
.minlen
+ opts
.keep_after
)
237 int cursor
= opts
.keep_before
;
238 while (cursor
< GetSize(chain
) - opts
.keep_after
)
240 int depth
= GetSize(chain
) - opts
.keep_after
- cursor
;
243 depth
= std::min(opts
.maxlen
, depth
);
245 Cell
*first_cell
= chain
[cursor
];
246 IdString q_port
= opts
.ffcells
.at(first_cell
->type
).second
;
247 dict
<int, SigBit
> taps_dict
;
251 vector
<SigBit
> qbits
;
254 for (int i
= 0; i
< depth
; i
++)
256 Cell
*cell
= chain
[cursor
+i
];
257 auto qbit
= sigmap(cell
->getPort(q_port
));
258 qbits
.push_back(qbit
);
260 if (sigbit_with_non_chain_users
.count(qbit
))
266 if (taps
.empty() || taps
.back() < depth
-1)
267 taps
.push_back(depth
-1);
269 if (opts
.tech
->analyze(taps
))
277 for (auto tap
: taps
) {
278 taps_dict
[tap
] = qbits
.at(tap
);
279 log_assert(depth
< tap
+1);
289 Cell
*last_cell
= chain
[cursor
+depth
-1];
291 log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n",
292 log_id(module
), log_id(first_cell
), log_id(module
), log_id(last_cell
), depth
);
297 string shreg_cell_type_str
= "$__SHREG";
299 shreg_cell_type_str
+= "_";
301 if (first_cell
->type
[1] != '_')
302 shreg_cell_type_str
+= "_";
303 shreg_cell_type_str
+= first_cell
->type
.substr(1);
307 vector
<State
> initval
;
308 for (int i
= depth
-1; i
>= 0; i
--) {
309 SigBit bit
= sigmap(chain
[cursor
+i
]->getPort(q_port
).as_bit());
310 if (sigbit_init
.count(bit
) == 0)
311 initval
.push_back(State::Sx
);
312 else if (sigbit_init
.at(bit
))
313 initval
.push_back(State::S1
);
315 initval
.push_back(State::S0
);
316 remove_init
.insert(bit
);
318 first_cell
->setParam(ID(INIT
), initval
);
322 for (int i
= depth
-1; i
>= 0; i
--) {
323 SigBit bit
= sigmap(chain
[cursor
+i
]->getPort(q_port
).as_bit());
324 remove_init
.insert(bit
);
329 int param_clkpol
= -1;
332 if (first_cell
->type
== ID($_DFF_N_
)) param_clkpol
= 0;
333 if (first_cell
->type
== ID($_DFF_P_
)) param_clkpol
= 1;
335 if (first_cell
->type
== ID($_DFFE_NN_
)) param_clkpol
= 0, param_enpol
= 0;
336 if (first_cell
->type
== ID($_DFFE_NP_
)) param_clkpol
= 0, param_enpol
= 1;
337 if (first_cell
->type
== ID($_DFFE_PN_
)) param_clkpol
= 1, param_enpol
= 0;
338 if (first_cell
->type
== ID($_DFFE_PP_
)) param_clkpol
= 1, param_enpol
= 1;
340 log_assert(param_clkpol
>= 0);
341 first_cell
->setParam(ID(CLKPOL
), param_clkpol
);
342 if (opts
.ffe
) first_cell
->setParam(ID(ENPOL
), param_enpol
);
345 first_cell
->type
= shreg_cell_type_str
;
346 first_cell
->setPort(q_port
, last_cell
->getPort(q_port
));
347 first_cell
->setParam(ID(DEPTH
), depth
);
349 if (opts
.tech
!= nullptr && !opts
.tech
->fixup(first_cell
, taps_dict
))
350 remove_cells
.insert(first_cell
);
352 for (int i
= 1; i
< depth
; i
++)
353 remove_cells
.insert(chain
[cursor
+i
]);
360 for (auto cell
: remove_cells
)
361 module
->remove(cell
);
363 for (auto wire
: module
->wires())
365 if (wire
->attributes
.count(ID(init
)) == 0)
368 SigSpec initsig
= sigmap(wire
);
369 Const
&initval
= wire
->attributes
.at(ID(init
));
371 for (int i
= 0; i
< GetSize(initsig
) && i
< GetSize(initval
); i
++)
372 if (remove_init
.count(initsig
[i
]))
373 initval
[i
] = State::Sx
;
375 if (SigSpec(initval
).is_fully_undef())
376 wire
->attributes
.erase(ID(init
));
379 remove_cells
.clear();
380 sigbit_chain_next
.clear();
381 sigbit_chain_prev
.clear();
382 chain_start_cells
.clear();
385 ShregmapWorker(Module
*module
, const ShregmapOptions
&opts
) :
386 module(module
), sigmap(module
), opts(opts
), dff_count(0), shreg_count(0)
388 make_sigbit_chain_next_prev();
389 find_chain_start_cells();
391 for (auto c
: chain_start_cells
) {
392 vector
<Cell
*> chain
= create_chain(c
);
393 process_chain(chain
);
400 struct ShregmapPass
: public Pass
{
401 ShregmapPass() : Pass("shregmap", "map shift registers") { }
402 void help() YS_OVERRIDE
404 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
406 log(" shregmap [options] [selection]\n");
408 log("This pass converts chains of $_DFF_[NP]_ gates to target specific shift register\n");
409 log("primitives. The generated shift register will be of type $__SHREG_DFF_[NP]_ and\n");
410 log("will use the same interface as the original $_DFF_*_ cells. The cell parameter\n");
411 log("'DEPTH' will contain the depth of the shift register. Use a target-specific\n");
412 log("'techmap' map file to convert those cells to the actual target cells.\n");
415 log(" minimum length of shift register (default = 2)\n");
416 log(" (this is the length after -keep_before and -keep_after)\n");
419 log(" maximum length of shift register (default = no limit)\n");
420 log(" larger chains will be mapped to multiple shift register instances\n");
422 log(" -keep_before N\n");
423 log(" number of DFFs to keep before the shift register (default = 0)\n");
425 log(" -keep_after N\n");
426 log(" number of DFFs to keep after the shift register (default = 0)\n");
428 log(" -clkpol pos|neg|any\n");
429 log(" limit match to only positive or negative edge clocks. (default = any)\n");
431 log(" -enpol pos|neg|none|any_or_none|any\n");
432 log(" limit match to FFs with the specified enable polarity. (default = none)\n");
434 log(" -match <cell_type>[:<d_port_name>:<q_port_name>]\n");
435 log(" match the specified cells instead of $_DFF_N_ and $_DFF_P_. If\n");
436 log(" ':<d_port_name>:<q_port_name>' is omitted then 'D' and 'Q' is used\n");
437 log(" by default. E.g. the option '-clkpol pos' is just an alias for\n");
438 log(" '-match $_DFF_P_', which is an alias for '-match $_DFF_P_:D:Q'.\n");
441 log(" instead of encoding the clock and enable polarity in the cell name by\n");
442 log(" deriving from the original cell name, simply name all generated cells\n");
443 log(" $__SHREG_ and use CLKPOL and ENPOL parameters. An ENPOL value of 2 is\n");
444 log(" used to denote cells without enable input. The ENPOL parameter is\n");
445 log(" omitted when '-enpol none' (or no -enpol option) is passed.\n");
448 log(" assume the shift register is automatically zero-initialized, so it\n");
449 log(" becomes legal to merge zero initialized FFs into the shift register.\n");
452 log(" map initialized registers to the shift reg, add an INIT parameter to\n");
453 log(" generated cells with the initialization value. (first bit to shift out\n");
454 log(" in LSB position)\n");
456 log(" -tech greenpak4\n");
457 log(" map to greenpak4 shift registers.\n");
460 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
462 ShregmapOptions opts
;
463 string clkpol
, enpol
;
465 log_header(design
, "Executing SHREGMAP pass (map shift registers).\n");
468 for (argidx
= 1; argidx
< args
.size(); argidx
++)
470 if (args
[argidx
] == "-clkpol" && argidx
+1 < args
.size()) {
471 clkpol
= args
[++argidx
];
474 if (args
[argidx
] == "-enpol" && argidx
+1 < args
.size()) {
475 enpol
= args
[++argidx
];
478 if (args
[argidx
] == "-match" && argidx
+1 < args
.size()) {
479 vector
<string
> match_args
= split_tokens(args
[++argidx
], ":");
480 if (GetSize(match_args
) < 2)
481 match_args
.push_back("D");
482 if (GetSize(match_args
) < 3)
483 match_args
.push_back("Q");
484 IdString
id_cell_type(RTLIL::escape_id(match_args
[0]));
485 IdString
id_d_port_name(RTLIL::escape_id(match_args
[1]));
486 IdString
id_q_port_name(RTLIL::escape_id(match_args
[2]));
487 opts
.ffcells
[id_cell_type
] = make_pair(id_d_port_name
, id_q_port_name
);
490 if (args
[argidx
] == "-minlen" && argidx
+1 < args
.size()) {
491 opts
.minlen
= atoi(args
[++argidx
].c_str());
494 if (args
[argidx
] == "-maxlen" && argidx
+1 < args
.size()) {
495 opts
.maxlen
= atoi(args
[++argidx
].c_str());
498 if (args
[argidx
] == "-keep_before" && argidx
+1 < args
.size()) {
499 opts
.keep_before
= atoi(args
[++argidx
].c_str());
502 if (args
[argidx
] == "-keep_after" && argidx
+1 < args
.size()) {
503 opts
.keep_after
= atoi(args
[++argidx
].c_str());
506 if (args
[argidx
] == "-tech" && argidx
+1 < args
.size() && opts
.tech
== nullptr) {
507 string tech
= args
[++argidx
];
508 if (tech
== "greenpak4") {
511 opts
.tech
= new ShregmapTechGreenpak4
;
518 if (args
[argidx
] == "-zinit") {
522 if (args
[argidx
] == "-init") {
526 if (args
[argidx
] == "-params") {
532 extra_args(args
, argidx
, design
);
534 if (opts
.zinit
&& opts
.init
)
535 log_cmd_error("Options -zinit and -init are exclusive!\n");
537 if (opts
.ffcells
.empty())
539 bool clk_pos
= clkpol
== "" || clkpol
== "pos" || clkpol
== "any";
540 bool clk_neg
= clkpol
== "" || clkpol
== "neg" || clkpol
== "any";
542 bool en_none
= enpol
== "" || enpol
== "none" || enpol
== "any_or_none";
543 bool en_pos
= enpol
== "pos" || enpol
== "any" || enpol
== "any_or_none";
544 bool en_neg
= enpol
== "neg" || enpol
== "any" || enpol
== "any_or_none";
546 if (clk_pos
&& en_none
)
547 opts
.ffcells
[ID($_DFF_P_
)] = make_pair(IdString(ID(D
)), IdString(ID(Q
)));
548 if (clk_neg
&& en_none
)
549 opts
.ffcells
[ID($_DFF_N_
)] = make_pair(IdString(ID(D
)), IdString(ID(Q
)));
551 if (clk_pos
&& en_pos
)
552 opts
.ffcells
[ID($_DFFE_PP_
)] = make_pair(IdString(ID(D
)), IdString(ID(Q
)));
553 if (clk_pos
&& en_neg
)
554 opts
.ffcells
[ID($_DFFE_PN_
)] = make_pair(IdString(ID(D
)), IdString(ID(Q
)));
556 if (clk_neg
&& en_pos
)
557 opts
.ffcells
[ID($_DFFE_NP_
)] = make_pair(IdString(ID(D
)), IdString(ID(Q
)));
558 if (clk_neg
&& en_neg
)
559 opts
.ffcells
[ID($_DFFE_NN_
)] = make_pair(IdString(ID(D
)), IdString(ID(Q
)));
561 if (en_pos
|| en_neg
)
567 log_cmd_error("Options -clkpol and -match are exclusive!\n");
569 log_cmd_error("Options -enpol and -match are exclusive!\n");
571 log_cmd_error("Options -params and -match are exclusive!\n");
577 for (auto module
: design
->selected_modules()) {
578 ShregmapWorker
worker(module
, opts
);
579 dff_count
+= worker
.dff_count
;
580 shreg_count
+= worker
.shreg_count
;
583 log("Converted %d dff cells into %d shift registers.\n", dff_count
, shreg_count
);
585 if (opts
.tech
!= nullptr) {
592 PRIVATE_NAMESPACE_END