2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
24 PRIVATE_NAMESPACE_BEGIN
28 virtual ~ShregmapTech() { }
29 virtual void init(const Module
* /*module*/, const SigMap
&/*sigmap*/) {}
30 virtual void non_chain_user(const SigBit
&/*bit*/, const Cell
* /*cell*/, IdString
/*port*/) {}
31 virtual bool analyze(vector
<int> &taps
, const vector
<SigBit
> &qbits
) = 0;
32 virtual bool fixup(Cell
*cell
, dict
<int, SigBit
> &taps
) = 0;
35 struct ShregmapOptions
38 int keep_before
, keep_after
;
39 bool zinit
, init
, params
, ffe
;
40 dict
<IdString
, pair
<IdString
, IdString
>> ffcells
;
57 struct ShregmapTechGreenpak4
: ShregmapTech
59 bool analyze(vector
<int> &taps
, const vector
<SigBit
> &/*qbits*/)
61 if (GetSize(taps
) > 2 && taps
[0] == 0 && taps
[2] < 17) {
66 if (GetSize(taps
) > 2)
69 if (taps
.back() > 16) return false;
74 bool fixup(Cell
*cell
, dict
<int, SigBit
> &taps
)
76 auto D
= cell
->getPort(ID(D
));
77 auto C
= cell
->getPort(ID(C
));
79 auto newcell
= cell
->module
->addCell(NEW_ID
, ID(GP_SHREG
));
80 newcell
->setPort(ID(nRST
), State::S1
);
81 newcell
->setPort(ID(CLK
), C
);
82 newcell
->setPort(ID(IN
), D
);
85 for (auto tap
: taps
) {
86 newcell
->setPort(i
? ID(OUTB
) : ID(OUTA
), tap
.second
);
87 newcell
->setParam(i
? ID(OUTB_TAP
) : ID(OUTA_TAP
), tap
.first
+ 1);
91 cell
->setParam(ID(OUTA_INVERT
), 0);
96 struct ShregmapTechXilinx7
: ShregmapTech
98 dict
<SigBit
, std::tuple
<Cell
*,int,int>> sigbit_to_shiftx_offset
;
99 const ShregmapOptions
&opts
;
101 ShregmapTechXilinx7(const ShregmapOptions
&opts
) : opts(opts
) {}
103 virtual void init(const Module
* module
, const SigMap
&sigmap
) override
105 for (const auto &i
: module
->cells_
) {
106 auto cell
= i
.second
;
107 if (cell
->type
== ID($shiftx
)) {
108 if (cell
->getParam(ID(Y_WIDTH
)) != 1) continue;
110 for (auto bit
: sigmap(cell
->getPort(ID::A
)))
111 sigbit_to_shiftx_offset
[bit
] = std::make_tuple(cell
, j
++, 0);
112 log_assert(j
== cell
->getParam(ID(A_WIDTH
)).as_int());
114 else if (cell
->type
== ID($mux
)) {
116 for (auto bit
: sigmap(cell
->getPort(ID::A
)))
117 sigbit_to_shiftx_offset
[bit
] = std::make_tuple(cell
, 0, j
++);
119 for (auto bit
: sigmap(cell
->getPort(ID::B
)))
120 sigbit_to_shiftx_offset
[bit
] = std::make_tuple(cell
, 1, j
++);
125 virtual void non_chain_user(const SigBit
&bit
, const Cell
*cell
, IdString port
) override
127 auto it
= sigbit_to_shiftx_offset
.find(bit
);
128 if (it
== sigbit_to_shiftx_offset
.end())
131 if (cell
->type
== ID($shiftx
) && port
== ID::A
)
133 if (cell
->type
== ID($mux
) && port
.in(ID::A
, ID::B
))
136 sigbit_to_shiftx_offset
.erase(it
);
139 virtual bool analyze(vector
<int> &taps
, const vector
<SigBit
> &qbits
) override
141 if (GetSize(taps
) == 1)
142 return taps
[0] >= opts
.minlen
-1 && sigbit_to_shiftx_offset
.count(qbits
[0]);
144 if (taps
.back() < opts
.minlen
-1)
147 Cell
*shiftx
= nullptr;
149 for (int i
= 0; i
< GetSize(taps
); ++i
) {
150 auto it
= sigbit_to_shiftx_offset
.find(qbits
[i
]);
151 if (it
== sigbit_to_shiftx_offset
.end())
154 // Check taps are sequential
157 // Check taps are not connected to a shift register,
158 // or sequential to the same shift register
161 std::tie(shiftx
,offset
,group
) = it
->second
;
166 Cell
*shiftx_
= std::get
<0>(it
->second
);
167 if (shiftx_
!= shiftx
)
169 int offset
= std::get
<1>(it
->second
);
172 int group_
= std::get
<2>(it
->second
);
179 // Only map if $shiftx exclusively covers the shift register
180 if (shiftx
->type
== ID($shiftx
)) {
181 if (GetSize(taps
) > shiftx
->getParam(ID(A_WIDTH
)).as_int())
183 // Due to padding the most significant bits of A may be 1'bx,
184 // and if so, discount them
185 if (GetSize(taps
) < shiftx
->getParam(ID(A_WIDTH
)).as_int()) {
186 const SigSpec A
= shiftx
->getPort(ID::A
);
187 const int A_width
= shiftx
->getParam(ID(A_WIDTH
)).as_int();
188 for (int i
= GetSize(taps
); i
< A_width
; ++i
)
189 if (A
[i
] != RTLIL::Sx
) return false;
191 else if (GetSize(taps
) != shiftx
->getParam(ID(A_WIDTH
)).as_int())
194 else if (shiftx
->type
== ID($mux
)) {
195 if (GetSize(taps
) != 2)
203 virtual bool fixup(Cell
*cell
, dict
<int, SigBit
> &taps
) override
205 const auto &tap
= *taps
.begin();
206 auto bit
= tap
.second
;
208 auto it
= sigbit_to_shiftx_offset
.find(bit
);
209 log_assert(it
!= sigbit_to_shiftx_offset
.end());
211 auto newcell
= cell
->module
->addCell(NEW_ID
, ID($__XILINX_SHREG_
));
212 newcell
->set_src_attribute(cell
->get_src_attribute());
213 newcell
->setParam(ID(DEPTH
), cell
->getParam(ID(DEPTH
)));
214 newcell
->setParam(ID(INIT
), cell
->getParam(ID(INIT
)));
215 newcell
->setParam(ID(CLKPOL
), cell
->getParam(ID(CLKPOL
)));
216 newcell
->setParam(ID(ENPOL
), cell
->getParam(ID(ENPOL
)));
218 newcell
->setPort(ID(C
), cell
->getPort(ID(C
)));
219 newcell
->setPort(ID(D
), cell
->getPort(ID(D
)));
220 if (cell
->hasPort(ID(E
)))
221 newcell
->setPort(ID(E
), cell
->getPort(ID(E
)));
223 Cell
* shiftx
= std::get
<0>(it
->second
);
224 RTLIL::SigSpec l_wire
, q_wire
;
225 if (shiftx
->type
== ID($shiftx
)) {
226 l_wire
= shiftx
->getPort(ID::B
);
227 q_wire
= shiftx
->getPort(ID::Y
);
228 shiftx
->setPort(ID::Y
, cell
->module
->addWire(NEW_ID
));
230 else if (shiftx
->type
== ID($mux
)) {
231 l_wire
= shiftx
->getPort(ID(S
));
232 q_wire
= shiftx
->getPort(ID::Y
);
233 shiftx
->setPort(ID::Y
, cell
->module
->addWire(NEW_ID
));
237 newcell
->setPort(ID(Q
), q_wire
);
238 newcell
->setPort(ID(L
), l_wire
);
245 struct ShregmapWorker
250 const ShregmapOptions
&opts
;
251 int dff_count
, shreg_count
;
253 pool
<Cell
*> remove_cells
;
254 pool
<SigBit
> remove_init
;
256 dict
<SigBit
, bool> sigbit_init
;
257 dict
<SigBit
, Cell
*> sigbit_chain_next
;
258 dict
<SigBit
, Cell
*> sigbit_chain_prev
;
259 pool
<SigBit
> sigbit_with_non_chain_users
;
260 pool
<Cell
*> chain_start_cells
;
262 void make_sigbit_chain_next_prev()
264 for (auto wire
: module
->wires())
266 if (wire
->port_output
|| wire
->get_bool_attribute(ID::keep
)) {
267 for (auto bit
: sigmap(wire
)) {
268 sigbit_with_non_chain_users
.insert(bit
);
269 if (opts
.tech
) opts
.tech
->non_chain_user(bit
, nullptr, {});
273 if (wire
->attributes
.count(ID(init
))) {
274 SigSpec initsig
= sigmap(wire
);
275 Const initval
= wire
->attributes
.at(ID(init
));
276 for (int i
= 0; i
< GetSize(initsig
) && i
< GetSize(initval
); i
++)
277 if (initval
[i
] == State::S0
&& !opts
.zinit
)
278 sigbit_init
[initsig
[i
]] = false;
279 else if (initval
[i
] == State::S1
)
280 sigbit_init
[initsig
[i
]] = true;
284 for (auto cell
: module
->cells())
286 if (opts
.ffcells
.count(cell
->type
) && !cell
->get_bool_attribute(ID::keep
))
288 IdString d_port
= opts
.ffcells
.at(cell
->type
).first
;
289 IdString q_port
= opts
.ffcells
.at(cell
->type
).second
;
291 SigBit d_bit
= sigmap(cell
->getPort(d_port
).as_bit());
292 SigBit q_bit
= sigmap(cell
->getPort(q_port
).as_bit());
294 if (opts
.init
|| sigbit_init
.count(q_bit
) == 0)
296 auto r
= sigbit_chain_next
.insert(std::make_pair(d_bit
, cell
));
298 // Insertion not successful means that d_bit is already
299 // connected to another register, thus mark it as a
300 // non chain user ...
301 sigbit_with_non_chain_users
.insert(d_bit
);
302 // ... and clone d_bit into another wire, and use that
303 // wire as a different key in the d_bit-to-cell dictionary
304 // so that it can be identified as another chain
305 // (omitting this common flop)
306 // Link: https://github.com/YosysHQ/yosys/pull/1085
307 Wire
*wire
= module
->addWire(NEW_ID
);
308 module
->connect(wire
, d_bit
);
309 sigmap
.add(wire
, d_bit
);
310 sigbit_chain_next
.insert(std::make_pair(wire
, cell
));
313 sigbit_chain_prev
[q_bit
] = cell
;
318 for (auto conn
: cell
->connections())
319 if (cell
->input(conn
.first
))
320 for (auto bit
: sigmap(conn
.second
)) {
321 sigbit_with_non_chain_users
.insert(bit
);
322 if (opts
.tech
) opts
.tech
->non_chain_user(bit
, cell
, conn
.first
);
327 void find_chain_start_cells()
329 for (auto it
: sigbit_chain_next
)
331 if (opts
.tech
== nullptr && sigbit_with_non_chain_users
.count(it
.first
))
334 if (sigbit_chain_prev
.count(it
.first
) != 0)
336 Cell
*c1
= sigbit_chain_prev
.at(it
.first
);
337 Cell
*c2
= it
.second
;
339 if (c1
->type
!= c2
->type
)
342 if (c1
->parameters
!= c2
->parameters
)
345 IdString d_port
= opts
.ffcells
.at(c1
->type
).first
;
346 IdString q_port
= opts
.ffcells
.at(c1
->type
).second
;
348 auto c1_conn
= c1
->connections();
349 auto c2_conn
= c1
->connections();
351 c1_conn
.erase(d_port
);
352 c1_conn
.erase(q_port
);
354 c2_conn
.erase(d_port
);
355 c2_conn
.erase(q_port
);
357 if (c1_conn
!= c2_conn
)
364 chain_start_cells
.insert(it
.second
);
368 vector
<Cell
*> create_chain(Cell
*start_cell
)
372 Cell
*c
= start_cell
;
377 IdString q_port
= opts
.ffcells
.at(c
->type
).second
;
378 SigBit q_bit
= sigmap(c
->getPort(q_port
).as_bit());
380 if (sigbit_chain_next
.count(q_bit
) == 0)
383 c
= sigbit_chain_next
.at(q_bit
);
384 if (chain_start_cells
.count(c
) != 0)
391 void process_chain(vector
<Cell
*> &chain
)
393 if (GetSize(chain
) < opts
.keep_before
+ opts
.minlen
+ opts
.keep_after
)
396 int cursor
= opts
.keep_before
;
397 while (cursor
< GetSize(chain
) - opts
.keep_after
)
399 int depth
= GetSize(chain
) - opts
.keep_after
- cursor
;
402 depth
= std::min(opts
.maxlen
, depth
);
404 Cell
*first_cell
= chain
[cursor
];
405 IdString q_port
= opts
.ffcells
.at(first_cell
->type
).second
;
406 dict
<int, SigBit
> taps_dict
;
410 vector
<SigBit
> qbits
;
413 for (int i
= 0; i
< depth
; i
++)
415 Cell
*cell
= chain
[cursor
+i
];
416 auto qbit
= sigmap(cell
->getPort(q_port
));
417 qbits
.push_back(qbit
);
419 if (sigbit_with_non_chain_users
.count(qbit
))
425 if (taps
.empty() || taps
.back() < depth
-1)
426 taps
.push_back(depth
-1);
428 if (opts
.tech
->analyze(taps
, qbits
))
436 for (auto tap
: taps
) {
437 taps_dict
[tap
] = qbits
.at(tap
);
438 log_assert(depth
< tap
+1);
448 Cell
*last_cell
= chain
[cursor
+depth
-1];
450 log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n",
451 log_id(module
), log_id(first_cell
), log_id(module
), log_id(last_cell
), depth
);
456 string shreg_cell_type_str
= "$__SHREG";
458 shreg_cell_type_str
+= "_";
460 if (first_cell
->type
[1] != '_')
461 shreg_cell_type_str
+= "_";
462 shreg_cell_type_str
+= first_cell
->type
.substr(1);
466 vector
<State
> initval
;
467 for (int i
= depth
-1; i
>= 0; i
--) {
468 SigBit bit
= sigmap(chain
[cursor
+i
]->getPort(q_port
).as_bit());
469 if (sigbit_init
.count(bit
) == 0)
470 initval
.push_back(State::Sx
);
471 else if (sigbit_init
.at(bit
))
472 initval
.push_back(State::S1
);
474 initval
.push_back(State::S0
);
475 remove_init
.insert(bit
);
477 first_cell
->setParam(ID(INIT
), initval
);
481 for (int i
= depth
-1; i
>= 0; i
--) {
482 SigBit bit
= sigmap(chain
[cursor
+i
]->getPort(q_port
).as_bit());
483 remove_init
.insert(bit
);
488 int param_clkpol
= -1;
491 if (first_cell
->type
== ID($_DFF_N_
)) param_clkpol
= 0;
492 if (first_cell
->type
== ID($_DFF_P_
)) param_clkpol
= 1;
494 if (first_cell
->type
== ID($_DFFE_NN_
)) param_clkpol
= 0, param_enpol
= 0;
495 if (first_cell
->type
== ID($_DFFE_NP_
)) param_clkpol
= 0, param_enpol
= 1;
496 if (first_cell
->type
== ID($_DFFE_PN_
)) param_clkpol
= 1, param_enpol
= 0;
497 if (first_cell
->type
== ID($_DFFE_PP_
)) param_clkpol
= 1, param_enpol
= 1;
499 log_assert(param_clkpol
>= 0);
500 first_cell
->setParam(ID(CLKPOL
), param_clkpol
);
501 if (opts
.ffe
) first_cell
->setParam(ID(ENPOL
), param_enpol
);
504 first_cell
->type
= shreg_cell_type_str
;
505 first_cell
->setPort(q_port
, last_cell
->getPort(q_port
));
506 first_cell
->setParam(ID(DEPTH
), depth
);
508 if (opts
.tech
!= nullptr && !opts
.tech
->fixup(first_cell
, taps_dict
))
509 remove_cells
.insert(first_cell
);
511 for (int i
= 1; i
< depth
; i
++)
512 remove_cells
.insert(chain
[cursor
+i
]);
519 for (auto cell
: remove_cells
)
520 module
->remove(cell
);
522 for (auto wire
: module
->wires())
524 if (wire
->attributes
.count(ID(init
)) == 0)
527 SigSpec initsig
= sigmap(wire
);
528 Const
&initval
= wire
->attributes
.at(ID(init
));
530 for (int i
= 0; i
< GetSize(initsig
) && i
< GetSize(initval
); i
++)
531 if (remove_init
.count(initsig
[i
]))
532 initval
[i
] = State::Sx
;
534 if (SigSpec(initval
).is_fully_undef())
535 wire
->attributes
.erase(ID(init
));
538 remove_cells
.clear();
539 sigbit_chain_next
.clear();
540 sigbit_chain_prev
.clear();
541 chain_start_cells
.clear();
544 ShregmapWorker(Module
*module
, const ShregmapOptions
&opts
) :
545 module(module
), sigmap(module
), opts(opts
), dff_count(0), shreg_count(0)
548 opts
.tech
->init(module
, sigmap
);
550 make_sigbit_chain_next_prev();
551 find_chain_start_cells();
553 for (auto c
: chain_start_cells
) {
554 vector
<Cell
*> chain
= create_chain(c
);
555 process_chain(chain
);
562 struct ShregmapPass
: public Pass
{
563 ShregmapPass() : Pass("shregmap", "map shift registers") { }
564 void help() YS_OVERRIDE
566 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
568 log(" shregmap [options] [selection]\n");
570 log("This pass converts chains of $_DFF_[NP]_ gates to target specific shift register\n");
571 log("primitives. The generated shift register will be of type $__SHREG_DFF_[NP]_ and\n");
572 log("will use the same interface as the original $_DFF_*_ cells. The cell parameter\n");
573 log("'DEPTH' will contain the depth of the shift register. Use a target-specific\n");
574 log("'techmap' map file to convert those cells to the actual target cells.\n");
577 log(" minimum length of shift register (default = 2)\n");
578 log(" (this is the length after -keep_before and -keep_after)\n");
581 log(" maximum length of shift register (default = no limit)\n");
582 log(" larger chains will be mapped to multiple shift register instances\n");
584 log(" -keep_before N\n");
585 log(" number of DFFs to keep before the shift register (default = 0)\n");
587 log(" -keep_after N\n");
588 log(" number of DFFs to keep after the shift register (default = 0)\n");
590 log(" -clkpol pos|neg|any\n");
591 log(" limit match to only positive or negative edge clocks. (default = any)\n");
593 log(" -enpol pos|neg|none|any_or_none|any\n");
594 log(" limit match to FFs with the specified enable polarity. (default = none)\n");
596 log(" -match <cell_type>[:<d_port_name>:<q_port_name>]\n");
597 log(" match the specified cells instead of $_DFF_N_ and $_DFF_P_. If\n");
598 log(" ':<d_port_name>:<q_port_name>' is omitted then 'D' and 'Q' is used\n");
599 log(" by default. E.g. the option '-clkpol pos' is just an alias for\n");
600 log(" '-match $_DFF_P_', which is an alias for '-match $_DFF_P_:D:Q'.\n");
603 log(" instead of encoding the clock and enable polarity in the cell name by\n");
604 log(" deriving from the original cell name, simply name all generated cells\n");
605 log(" $__SHREG_ and use CLKPOL and ENPOL parameters. An ENPOL value of 2 is\n");
606 log(" used to denote cells without enable input. The ENPOL parameter is\n");
607 log(" omitted when '-enpol none' (or no -enpol option) is passed.\n");
610 log(" assume the shift register is automatically zero-initialized, so it\n");
611 log(" becomes legal to merge zero initialized FFs into the shift register.\n");
614 log(" map initialized registers to the shift reg, add an INIT parameter to\n");
615 log(" generated cells with the initialization value. (first bit to shift out\n");
616 log(" in LSB position)\n");
618 log(" -tech greenpak4\n");
619 log(" map to greenpak4 shift registers.\n");
620 log(" this option also implies -clkpol pos -zinit\n");
622 log(" -tech xilinx\n");
623 log(" map to xilinx dynamic-length shift registers.\n");
624 log(" this option also implies -params -init\n");
627 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
629 ShregmapOptions opts
;
630 string clkpol
, enpol
;
632 log_header(design
, "Executing SHREGMAP pass (map shift registers).\n");
635 for (argidx
= 1; argidx
< args
.size(); argidx
++)
637 if (args
[argidx
] == "-clkpol" && argidx
+1 < args
.size()) {
638 clkpol
= args
[++argidx
];
641 if (args
[argidx
] == "-enpol" && argidx
+1 < args
.size()) {
642 enpol
= args
[++argidx
];
645 if (args
[argidx
] == "-match" && argidx
+1 < args
.size()) {
646 vector
<string
> match_args
= split_tokens(args
[++argidx
], ":");
647 if (GetSize(match_args
) < 2)
648 match_args
.push_back("D");
649 if (GetSize(match_args
) < 3)
650 match_args
.push_back("Q");
651 IdString
id_cell_type(RTLIL::escape_id(match_args
[0]));
652 IdString
id_d_port_name(RTLIL::escape_id(match_args
[1]));
653 IdString
id_q_port_name(RTLIL::escape_id(match_args
[2]));
654 opts
.ffcells
[id_cell_type
] = make_pair(id_d_port_name
, id_q_port_name
);
657 if (args
[argidx
] == "-minlen" && argidx
+1 < args
.size()) {
658 opts
.minlen
= atoi(args
[++argidx
].c_str());
661 if (args
[argidx
] == "-maxlen" && argidx
+1 < args
.size()) {
662 opts
.maxlen
= atoi(args
[++argidx
].c_str());
665 if (args
[argidx
] == "-keep_before" && argidx
+1 < args
.size()) {
666 opts
.keep_before
= atoi(args
[++argidx
].c_str());
669 if (args
[argidx
] == "-keep_after" && argidx
+1 < args
.size()) {
670 opts
.keep_after
= atoi(args
[++argidx
].c_str());
673 if (args
[argidx
] == "-tech" && argidx
+1 < args
.size() && opts
.tech
== nullptr) {
674 string tech
= args
[++argidx
];
675 if (tech
== "greenpak4") {
678 opts
.tech
= new ShregmapTechGreenpak4
;
680 else if (tech
== "xilinx") {
683 enpol
= "any_or_none";
684 opts
.tech
= new ShregmapTechXilinx7(opts
);
691 if (args
[argidx
] == "-zinit") {
695 if (args
[argidx
] == "-init") {
699 if (args
[argidx
] == "-params") {
705 extra_args(args
, argidx
, design
);
707 if (opts
.zinit
&& opts
.init
)
708 log_cmd_error("Options -zinit and -init are exclusive!\n");
710 if (opts
.ffcells
.empty())
712 bool clk_pos
= clkpol
== "" || clkpol
== "pos" || clkpol
== "any";
713 bool clk_neg
= clkpol
== "" || clkpol
== "neg" || clkpol
== "any";
715 bool en_none
= enpol
== "" || enpol
== "none" || enpol
== "any_or_none";
716 bool en_pos
= enpol
== "pos" || enpol
== "any" || enpol
== "any_or_none";
717 bool en_neg
= enpol
== "neg" || enpol
== "any" || enpol
== "any_or_none";
719 if (clk_pos
&& en_none
)
720 opts
.ffcells
[ID($_DFF_P_
)] = make_pair(IdString(ID(D
)), IdString(ID(Q
)));
721 if (clk_neg
&& en_none
)
722 opts
.ffcells
[ID($_DFF_N_
)] = make_pair(IdString(ID(D
)), IdString(ID(Q
)));
724 if (clk_pos
&& en_pos
)
725 opts
.ffcells
[ID($_DFFE_PP_
)] = make_pair(IdString(ID(D
)), IdString(ID(Q
)));
726 if (clk_pos
&& en_neg
)
727 opts
.ffcells
[ID($_DFFE_PN_
)] = make_pair(IdString(ID(D
)), IdString(ID(Q
)));
729 if (clk_neg
&& en_pos
)
730 opts
.ffcells
[ID($_DFFE_NP_
)] = make_pair(IdString(ID(D
)), IdString(ID(Q
)));
731 if (clk_neg
&& en_neg
)
732 opts
.ffcells
[ID($_DFFE_NN_
)] = make_pair(IdString(ID(D
)), IdString(ID(Q
)));
734 if (en_pos
|| en_neg
)
740 log_cmd_error("Options -clkpol and -match are exclusive!\n");
742 log_cmd_error("Options -enpol and -match are exclusive!\n");
744 log_cmd_error("Options -params and -match are exclusive!\n");
750 for (auto module
: design
->selected_modules()) {
751 ShregmapWorker
worker(module
, opts
);
752 dff_count
+= worker
.dff_count
;
753 shreg_count
+= worker
.shreg_count
;
756 log("Converted %d dff cells into %d shift registers.\n", dff_count
, shreg_count
);
758 if (opts
.tech
!= nullptr) {
765 PRIVATE_NAMESPACE_END