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Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
[yosys.git] / passes / techmap / shregmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22
23 USING_YOSYS_NAMESPACE
24 PRIVATE_NAMESPACE_BEGIN
25
26 struct ShregmapTech
27 {
28 virtual ~ShregmapTech() { }
29 virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {}
30 virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {}
31 virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) = 0;
32 virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) = 0;
33 };
34
35 struct ShregmapOptions
36 {
37 int minlen, maxlen;
38 int keep_before, keep_after;
39 bool zinit, init, params, ffe;
40 dict<IdString, pair<IdString, IdString>> ffcells;
41 ShregmapTech *tech;
42
43 ShregmapOptions()
44 {
45 minlen = 2;
46 maxlen = 0;
47 keep_before = 0;
48 keep_after = 0;
49 zinit = false;
50 init = false;
51 params = false;
52 ffe = false;
53 tech = nullptr;
54 }
55 };
56
57 struct ShregmapTechGreenpak4 : ShregmapTech
58 {
59 bool analyze(vector<int> &taps, const vector<SigBit> &/*qbits*/)
60 {
61 if (GetSize(taps) > 2 && taps[0] == 0 && taps[2] < 17) {
62 taps.clear();
63 return true;
64 }
65
66 if (GetSize(taps) > 2)
67 return false;
68
69 if (taps.back() > 16) return false;
70
71 return true;
72 }
73
74 bool fixup(Cell *cell, dict<int, SigBit> &taps)
75 {
76 auto D = cell->getPort(ID(D));
77 auto C = cell->getPort(ID(C));
78
79 auto newcell = cell->module->addCell(NEW_ID, ID(GP_SHREG));
80 newcell->setPort(ID(nRST), State::S1);
81 newcell->setPort(ID(CLK), C);
82 newcell->setPort(ID(IN), D);
83
84 int i = 0;
85 for (auto tap : taps) {
86 newcell->setPort(i ? ID(OUTB) : ID(OUTA), tap.second);
87 newcell->setParam(i ? ID(OUTB_TAP) : ID(OUTA_TAP), tap.first + 1);
88 i++;
89 }
90
91 cell->setParam(ID(OUTA_INVERT), 0);
92 return false;
93 }
94 };
95
96 struct ShregmapTechXilinx7 : ShregmapTech
97 {
98 dict<SigBit, std::tuple<Cell*,int,int>> sigbit_to_shiftx_offset;
99 const ShregmapOptions &opts;
100
101 ShregmapTechXilinx7(const ShregmapOptions &opts) : opts(opts) {}
102
103 virtual void init(const Module* module, const SigMap &sigmap) override
104 {
105 for (const auto &i : module->cells_) {
106 auto cell = i.second;
107 if (cell->type == ID($shiftx)) {
108 if (cell->getParam(ID(Y_WIDTH)) != 1) continue;
109 int j = 0;
110 for (auto bit : sigmap(cell->getPort(ID(A))))
111 sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, j++, 0);
112 log_assert(j == cell->getParam(ID(A_WIDTH)).as_int());
113 }
114 else if (cell->type == ID($mux)) {
115 int j = 0;
116 for (auto bit : sigmap(cell->getPort(ID(A))))
117 sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 0, j++);
118 j = 0;
119 for (auto bit : sigmap(cell->getPort(ID(B))))
120 sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 1, j++);
121 }
122 }
123 }
124
125 virtual void non_chain_user(const SigBit &bit, const Cell *cell, IdString port) override
126 {
127 auto it = sigbit_to_shiftx_offset.find(bit);
128 if (it == sigbit_to_shiftx_offset.end())
129 return;
130 if (cell) {
131 if (cell->type == ID($shiftx) && port == ID(A))
132 return;
133 if (cell->type == ID($mux) && port.in(ID(A), ID(B)))
134 return;
135 }
136 sigbit_to_shiftx_offset.erase(it);
137 }
138
139 virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) override
140 {
141 if (GetSize(taps) == 1)
142 return taps[0] >= opts.minlen-1 && sigbit_to_shiftx_offset.count(qbits[0]);
143
144 if (taps.back() < opts.minlen-1)
145 return false;
146
147 Cell *shiftx = nullptr;
148 int group = 0;
149 for (int i = 0; i < GetSize(taps); ++i) {
150 auto it = sigbit_to_shiftx_offset.find(qbits[i]);
151 if (it == sigbit_to_shiftx_offset.end())
152 return false;
153
154 // Check taps are sequential
155 if (i != taps[i])
156 return false;
157 // Check taps are not connected to a shift register,
158 // or sequential to the same shift register
159 if (i == 0) {
160 int offset;
161 std::tie(shiftx,offset,group) = it->second;
162 if (offset != i)
163 return false;
164 }
165 else {
166 Cell *shiftx_ = std::get<0>(it->second);
167 if (shiftx_ != shiftx)
168 return false;
169 int offset = std::get<1>(it->second);
170 if (offset != i)
171 return false;
172 int group_ = std::get<2>(it->second);
173 if (group_ != group)
174 return false;
175 }
176 }
177 log_assert(shiftx);
178
179 // Only map if $shiftx exclusively covers the shift register
180 if (shiftx->type == ID($shiftx)) {
181 if (GetSize(taps) > shiftx->getParam(ID(A_WIDTH)).as_int())
182 return false;
183 // Due to padding the most significant bits of A may be 1'bx,
184 // and if so, discount them
185 if (GetSize(taps) < shiftx->getParam(ID(A_WIDTH)).as_int()) {
186 const SigSpec A = shiftx->getPort(ID(A));
187 const int A_width = shiftx->getParam(ID(A_WIDTH)).as_int();
188 for (int i = GetSize(taps); i < A_width; ++i)
189 if (A[i] != RTLIL::Sx) return false;
190 }
191 else if (GetSize(taps) != shiftx->getParam(ID(A_WIDTH)).as_int())
192 return false;
193 }
194 else if (shiftx->type == ID($mux)) {
195 if (GetSize(taps) != 2)
196 return false;
197 }
198 else log_abort();
199
200 return true;
201 }
202
203 virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) override
204 {
205 const auto &tap = *taps.begin();
206 auto bit = tap.second;
207
208 auto it = sigbit_to_shiftx_offset.find(bit);
209 log_assert(it != sigbit_to_shiftx_offset.end());
210
211 auto newcell = cell->module->addCell(NEW_ID, ID($__XILINX_SHREG_));
212 newcell->set_src_attribute(cell->get_src_attribute());
213 newcell->setParam(ID(DEPTH), cell->getParam(ID(DEPTH)));
214 newcell->setParam(ID(INIT), cell->getParam(ID(INIT)));
215 newcell->setParam(ID(CLKPOL), cell->getParam(ID(CLKPOL)));
216 newcell->setParam(ID(ENPOL), cell->getParam(ID(ENPOL)));
217
218 newcell->setPort(ID(C), cell->getPort(ID(C)));
219 newcell->setPort(ID(D), cell->getPort(ID(D)));
220 if (cell->hasPort(ID(E)))
221 newcell->setPort(ID(E), cell->getPort(ID(E)));
222
223 Cell* shiftx = std::get<0>(it->second);
224 RTLIL::SigSpec l_wire, q_wire;
225 if (shiftx->type == ID($shiftx)) {
226 l_wire = shiftx->getPort(ID(B));
227 q_wire = shiftx->getPort(ID(Y));
228 shiftx->setPort(ID(Y), cell->module->addWire(NEW_ID));
229 }
230 else if (shiftx->type == ID($mux)) {
231 l_wire = shiftx->getPort(ID(S));
232 q_wire = shiftx->getPort(ID(Y));
233 shiftx->setPort(ID(Y), cell->module->addWire(NEW_ID));
234 }
235 else log_abort();
236
237 newcell->setPort(ID(Q), q_wire);
238 newcell->setPort(ID(L), l_wire);
239
240 return false;
241 }
242 };
243
244
245 struct ShregmapWorker
246 {
247 Module *module;
248 SigMap sigmap;
249
250 const ShregmapOptions &opts;
251 int dff_count, shreg_count;
252
253 pool<Cell*> remove_cells;
254 pool<SigBit> remove_init;
255
256 dict<SigBit, bool> sigbit_init;
257 dict<SigBit, Cell*> sigbit_chain_next;
258 dict<SigBit, Cell*> sigbit_chain_prev;
259 pool<SigBit> sigbit_with_non_chain_users;
260 pool<Cell*> chain_start_cells;
261
262 void make_sigbit_chain_next_prev()
263 {
264 for (auto wire : module->wires())
265 {
266 if (wire->port_output || wire->get_bool_attribute(ID(keep))) {
267 for (auto bit : sigmap(wire)) {
268 sigbit_with_non_chain_users.insert(bit);
269 if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {});
270 }
271 }
272
273 if (wire->attributes.count(ID(init))) {
274 SigSpec initsig = sigmap(wire);
275 Const initval = wire->attributes.at(ID(init));
276 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
277 if (initval[i] == State::S0 && !opts.zinit)
278 sigbit_init[initsig[i]] = false;
279 else if (initval[i] == State::S1)
280 sigbit_init[initsig[i]] = true;
281 }
282 }
283
284 for (auto cell : module->cells())
285 {
286 if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute(ID(keep)))
287 {
288 IdString d_port = opts.ffcells.at(cell->type).first;
289 IdString q_port = opts.ffcells.at(cell->type).second;
290
291 SigBit d_bit = sigmap(cell->getPort(d_port).as_bit());
292 SigBit q_bit = sigmap(cell->getPort(q_port).as_bit());
293
294 if (opts.init || sigbit_init.count(q_bit) == 0)
295 {
296 auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell));
297 if (!r.second) {
298 // Insertion not successful means that d_bit is already
299 // connected to another register, thus mark it as a
300 // non chain user ...
301 sigbit_with_non_chain_users.insert(d_bit);
302 // ... and clone d_bit into another wire, and use that
303 // wire as a different key in the d_bit-to-cell dictionary
304 // so that it can be identified as another chain
305 // (omitting this common flop)
306 // Link: https://github.com/YosysHQ/yosys/pull/1085
307 Wire *wire = module->addWire(NEW_ID);
308 module->connect(wire, d_bit);
309 sigmap.add(wire, d_bit);
310 sigbit_chain_next.insert(std::make_pair(wire, cell));
311 }
312
313 sigbit_chain_prev[q_bit] = cell;
314 continue;
315 }
316 }
317
318 for (auto conn : cell->connections())
319 if (cell->input(conn.first))
320 for (auto bit : sigmap(conn.second)) {
321 sigbit_with_non_chain_users.insert(bit);
322 if (opts.tech) opts.tech->non_chain_user(bit, cell, conn.first);
323 }
324 }
325 }
326
327 void find_chain_start_cells()
328 {
329 for (auto it : sigbit_chain_next)
330 {
331 if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first))
332 goto start_cell;
333
334 if (sigbit_chain_prev.count(it.first) != 0)
335 {
336 Cell *c1 = sigbit_chain_prev.at(it.first);
337 Cell *c2 = it.second;
338
339 if (c1->type != c2->type)
340 goto start_cell;
341
342 if (c1->parameters != c2->parameters)
343 goto start_cell;
344
345 IdString d_port = opts.ffcells.at(c1->type).first;
346 IdString q_port = opts.ffcells.at(c1->type).second;
347
348 auto c1_conn = c1->connections();
349 auto c2_conn = c1->connections();
350
351 c1_conn.erase(d_port);
352 c1_conn.erase(q_port);
353
354 c2_conn.erase(d_port);
355 c2_conn.erase(q_port);
356
357 if (c1_conn != c2_conn)
358 goto start_cell;
359
360 continue;
361 }
362
363 start_cell:
364 chain_start_cells.insert(it.second);
365 }
366 }
367
368 vector<Cell*> create_chain(Cell *start_cell)
369 {
370 vector<Cell*> chain;
371
372 Cell *c = start_cell;
373 while (c != nullptr)
374 {
375 chain.push_back(c);
376
377 IdString q_port = opts.ffcells.at(c->type).second;
378 SigBit q_bit = sigmap(c->getPort(q_port).as_bit());
379
380 if (sigbit_chain_next.count(q_bit) == 0)
381 break;
382
383 c = sigbit_chain_next.at(q_bit);
384 if (chain_start_cells.count(c) != 0)
385 break;
386 }
387
388 return chain;
389 }
390
391 void process_chain(vector<Cell*> &chain)
392 {
393 if (GetSize(chain) < opts.keep_before + opts.minlen + opts.keep_after)
394 return;
395
396 int cursor = opts.keep_before;
397 while (cursor < GetSize(chain) - opts.keep_after)
398 {
399 int depth = GetSize(chain) - opts.keep_after - cursor;
400
401 if (opts.maxlen > 0)
402 depth = std::min(opts.maxlen, depth);
403
404 Cell *first_cell = chain[cursor];
405 IdString q_port = opts.ffcells.at(first_cell->type).second;
406 dict<int, SigBit> taps_dict;
407
408 if (opts.tech)
409 {
410 vector<SigBit> qbits;
411 vector<int> taps;
412
413 for (int i = 0; i < depth; i++)
414 {
415 Cell *cell = chain[cursor+i];
416 auto qbit = sigmap(cell->getPort(q_port));
417 qbits.push_back(qbit);
418
419 if (sigbit_with_non_chain_users.count(qbit))
420 taps.push_back(i);
421 }
422
423 while (depth > 0)
424 {
425 if (taps.empty() || taps.back() < depth-1)
426 taps.push_back(depth-1);
427
428 if (opts.tech->analyze(taps, qbits))
429 break;
430
431 taps.pop_back();
432 depth--;
433 }
434
435 depth = 0;
436 for (auto tap : taps) {
437 taps_dict[tap] = qbits.at(tap);
438 log_assert(depth < tap+1);
439 depth = tap+1;
440 }
441 }
442
443 if (depth < 2) {
444 cursor++;
445 continue;
446 }
447
448 Cell *last_cell = chain[cursor+depth-1];
449
450 log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n",
451 log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), depth);
452
453 dff_count += depth;
454 shreg_count += 1;
455
456 string shreg_cell_type_str = "$__SHREG";
457 if (opts.params) {
458 shreg_cell_type_str += "_";
459 } else {
460 if (first_cell->type[1] != '_')
461 shreg_cell_type_str += "_";
462 shreg_cell_type_str += first_cell->type.substr(1);
463 }
464
465 if (opts.init) {
466 vector<State> initval;
467 for (int i = depth-1; i >= 0; i--) {
468 SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
469 if (sigbit_init.count(bit) == 0)
470 initval.push_back(State::Sx);
471 else if (sigbit_init.at(bit))
472 initval.push_back(State::S1);
473 else
474 initval.push_back(State::S0);
475 remove_init.insert(bit);
476 }
477 first_cell->setParam(ID(INIT), initval);
478 }
479
480 if (opts.zinit)
481 for (int i = depth-1; i >= 0; i--) {
482 SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
483 remove_init.insert(bit);
484 }
485
486 if (opts.params)
487 {
488 int param_clkpol = -1;
489 int param_enpol = 2;
490
491 if (first_cell->type == ID($_DFF_N_)) param_clkpol = 0;
492 if (first_cell->type == ID($_DFF_P_)) param_clkpol = 1;
493
494 if (first_cell->type == ID($_DFFE_NN_)) param_clkpol = 0, param_enpol = 0;
495 if (first_cell->type == ID($_DFFE_NP_)) param_clkpol = 0, param_enpol = 1;
496 if (first_cell->type == ID($_DFFE_PN_)) param_clkpol = 1, param_enpol = 0;
497 if (first_cell->type == ID($_DFFE_PP_)) param_clkpol = 1, param_enpol = 1;
498
499 log_assert(param_clkpol >= 0);
500 first_cell->setParam(ID(CLKPOL), param_clkpol);
501 if (opts.ffe) first_cell->setParam(ID(ENPOL), param_enpol);
502 }
503
504 first_cell->type = shreg_cell_type_str;
505 first_cell->setPort(q_port, last_cell->getPort(q_port));
506 first_cell->setParam(ID(DEPTH), depth);
507
508 if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
509 remove_cells.insert(first_cell);
510
511 for (int i = 1; i < depth; i++)
512 remove_cells.insert(chain[cursor+i]);
513 cursor += depth;
514 }
515 }
516
517 void cleanup()
518 {
519 for (auto cell : remove_cells)
520 module->remove(cell);
521
522 for (auto wire : module->wires())
523 {
524 if (wire->attributes.count(ID(init)) == 0)
525 continue;
526
527 SigSpec initsig = sigmap(wire);
528 Const &initval = wire->attributes.at(ID(init));
529
530 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
531 if (remove_init.count(initsig[i]))
532 initval[i] = State::Sx;
533
534 if (SigSpec(initval).is_fully_undef())
535 wire->attributes.erase(ID(init));
536 }
537
538 remove_cells.clear();
539 sigbit_chain_next.clear();
540 sigbit_chain_prev.clear();
541 chain_start_cells.clear();
542 }
543
544 ShregmapWorker(Module *module, const ShregmapOptions &opts) :
545 module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0)
546 {
547 if (opts.tech)
548 opts.tech->init(module, sigmap);
549
550 make_sigbit_chain_next_prev();
551 find_chain_start_cells();
552
553 for (auto c : chain_start_cells) {
554 vector<Cell*> chain = create_chain(c);
555 process_chain(chain);
556 }
557
558 cleanup();
559 }
560 };
561
562 struct ShregmapPass : public Pass {
563 ShregmapPass() : Pass("shregmap", "map shift registers") { }
564 void help() YS_OVERRIDE
565 {
566 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
567 log("\n");
568 log(" shregmap [options] [selection]\n");
569 log("\n");
570 log("This pass converts chains of $_DFF_[NP]_ gates to target specific shift register\n");
571 log("primitives. The generated shift register will be of type $__SHREG_DFF_[NP]_ and\n");
572 log("will use the same interface as the original $_DFF_*_ cells. The cell parameter\n");
573 log("'DEPTH' will contain the depth of the shift register. Use a target-specific\n");
574 log("'techmap' map file to convert those cells to the actual target cells.\n");
575 log("\n");
576 log(" -minlen N\n");
577 log(" minimum length of shift register (default = 2)\n");
578 log(" (this is the length after -keep_before and -keep_after)\n");
579 log("\n");
580 log(" -maxlen N\n");
581 log(" maximum length of shift register (default = no limit)\n");
582 log(" larger chains will be mapped to multiple shift register instances\n");
583 log("\n");
584 log(" -keep_before N\n");
585 log(" number of DFFs to keep before the shift register (default = 0)\n");
586 log("\n");
587 log(" -keep_after N\n");
588 log(" number of DFFs to keep after the shift register (default = 0)\n");
589 log("\n");
590 log(" -clkpol pos|neg|any\n");
591 log(" limit match to only positive or negative edge clocks. (default = any)\n");
592 log("\n");
593 log(" -enpol pos|neg|none|any_or_none|any\n");
594 log(" limit match to FFs with the specified enable polarity. (default = none)\n");
595 log("\n");
596 log(" -match <cell_type>[:<d_port_name>:<q_port_name>]\n");
597 log(" match the specified cells instead of $_DFF_N_ and $_DFF_P_. If\n");
598 log(" ':<d_port_name>:<q_port_name>' is omitted then 'D' and 'Q' is used\n");
599 log(" by default. E.g. the option '-clkpol pos' is just an alias for\n");
600 log(" '-match $_DFF_P_', which is an alias for '-match $_DFF_P_:D:Q'.\n");
601 log("\n");
602 log(" -params\n");
603 log(" instead of encoding the clock and enable polarity in the cell name by\n");
604 log(" deriving from the original cell name, simply name all generated cells\n");
605 log(" $__SHREG_ and use CLKPOL and ENPOL parameters. An ENPOL value of 2 is\n");
606 log(" used to denote cells without enable input. The ENPOL parameter is\n");
607 log(" omitted when '-enpol none' (or no -enpol option) is passed.\n");
608 log("\n");
609 log(" -zinit\n");
610 log(" assume the shift register is automatically zero-initialized, so it\n");
611 log(" becomes legal to merge zero initialized FFs into the shift register.\n");
612 log("\n");
613 log(" -init\n");
614 log(" map initialized registers to the shift reg, add an INIT parameter to\n");
615 log(" generated cells with the initialization value. (first bit to shift out\n");
616 log(" in LSB position)\n");
617 log("\n");
618 log(" -tech greenpak4\n");
619 log(" map to greenpak4 shift registers.\n");
620 log(" this option also implies -clkpol pos -zinit\n");
621 log("\n");
622 log(" -tech xilinx\n");
623 log(" map to xilinx dynamic-length shift registers.\n");
624 log(" this option also implies -params -init\n");
625 log("\n");
626 }
627 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
628 {
629 ShregmapOptions opts;
630 string clkpol, enpol;
631
632 log_header(design, "Executing SHREGMAP pass (map shift registers).\n");
633
634 size_t argidx;
635 for (argidx = 1; argidx < args.size(); argidx++)
636 {
637 if (args[argidx] == "-clkpol" && argidx+1 < args.size()) {
638 clkpol = args[++argidx];
639 continue;
640 }
641 if (args[argidx] == "-enpol" && argidx+1 < args.size()) {
642 enpol = args[++argidx];
643 continue;
644 }
645 if (args[argidx] == "-match" && argidx+1 < args.size()) {
646 vector<string> match_args = split_tokens(args[++argidx], ":");
647 if (GetSize(match_args) < 2)
648 match_args.push_back("D");
649 if (GetSize(match_args) < 3)
650 match_args.push_back("Q");
651 IdString id_cell_type(RTLIL::escape_id(match_args[0]));
652 IdString id_d_port_name(RTLIL::escape_id(match_args[1]));
653 IdString id_q_port_name(RTLIL::escape_id(match_args[2]));
654 opts.ffcells[id_cell_type] = make_pair(id_d_port_name, id_q_port_name);
655 continue;
656 }
657 if (args[argidx] == "-minlen" && argidx+1 < args.size()) {
658 opts.minlen = atoi(args[++argidx].c_str());
659 continue;
660 }
661 if (args[argidx] == "-maxlen" && argidx+1 < args.size()) {
662 opts.maxlen = atoi(args[++argidx].c_str());
663 continue;
664 }
665 if (args[argidx] == "-keep_before" && argidx+1 < args.size()) {
666 opts.keep_before = atoi(args[++argidx].c_str());
667 continue;
668 }
669 if (args[argidx] == "-keep_after" && argidx+1 < args.size()) {
670 opts.keep_after = atoi(args[++argidx].c_str());
671 continue;
672 }
673 if (args[argidx] == "-tech" && argidx+1 < args.size() && opts.tech == nullptr) {
674 string tech = args[++argidx];
675 if (tech == "greenpak4") {
676 clkpol = "pos";
677 opts.zinit = true;
678 opts.tech = new ShregmapTechGreenpak4;
679 }
680 else if (tech == "xilinx") {
681 opts.init = true;
682 opts.params = true;
683 enpol = "any_or_none";
684 opts.tech = new ShregmapTechXilinx7(opts);
685 } else {
686 argidx--;
687 break;
688 }
689 continue;
690 }
691 if (args[argidx] == "-zinit") {
692 opts.zinit = true;
693 continue;
694 }
695 if (args[argidx] == "-init") {
696 opts.init = true;
697 continue;
698 }
699 if (args[argidx] == "-params") {
700 opts.params = true;
701 continue;
702 }
703 break;
704 }
705 extra_args(args, argidx, design);
706
707 if (opts.zinit && opts.init)
708 log_cmd_error("Options -zinit and -init are exclusive!\n");
709
710 if (opts.ffcells.empty())
711 {
712 bool clk_pos = clkpol == "" || clkpol == "pos" || clkpol == "any";
713 bool clk_neg = clkpol == "" || clkpol == "neg" || clkpol == "any";
714
715 bool en_none = enpol == "" || enpol == "none" || enpol == "any_or_none";
716 bool en_pos = enpol == "pos" || enpol == "any" || enpol == "any_or_none";
717 bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none";
718
719 if (clk_pos && en_none)
720 opts.ffcells[ID($_DFF_P_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
721 if (clk_neg && en_none)
722 opts.ffcells[ID($_DFF_N_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
723
724 if (clk_pos && en_pos)
725 opts.ffcells[ID($_DFFE_PP_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
726 if (clk_pos && en_neg)
727 opts.ffcells[ID($_DFFE_PN_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
728
729 if (clk_neg && en_pos)
730 opts.ffcells[ID($_DFFE_NP_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
731 if (clk_neg && en_neg)
732 opts.ffcells[ID($_DFFE_NN_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
733
734 if (en_pos || en_neg)
735 opts.ffe = true;
736 }
737 else
738 {
739 if (!clkpol.empty())
740 log_cmd_error("Options -clkpol and -match are exclusive!\n");
741 if (!enpol.empty())
742 log_cmd_error("Options -enpol and -match are exclusive!\n");
743 if (opts.params)
744 log_cmd_error("Options -params and -match are exclusive!\n");
745 }
746
747 int dff_count = 0;
748 int shreg_count = 0;
749
750 for (auto module : design->selected_modules()) {
751 ShregmapWorker worker(module, opts);
752 dff_count += worker.dff_count;
753 shreg_count += worker.shreg_count;
754 }
755
756 log("Converted %d dff cells into %d shift registers.\n", dff_count, shreg_count);
757
758 if (opts.tech != nullptr) {
759 delete opts.tech;
760 opts.tech = nullptr;
761 }
762 }
763 } ShregmapPass;
764
765 PRIVATE_NAMESPACE_END