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Merge branch 'xc7mux' into xaig
[yosys.git] / passes / techmap / shregmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22
23 USING_YOSYS_NAMESPACE
24 PRIVATE_NAMESPACE_BEGIN
25
26 struct ShregmapTech
27 {
28 virtual ~ShregmapTech() { }
29 virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {}
30 virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {}
31 virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) = 0;
32 virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) = 0;
33 };
34
35 struct ShregmapOptions
36 {
37 int minlen, maxlen;
38 int keep_before, keep_after;
39 bool zinit, init, params, ffe;
40 dict<IdString, pair<IdString, IdString>> ffcells;
41 ShregmapTech *tech;
42
43 ShregmapOptions()
44 {
45 minlen = 2;
46 maxlen = 0;
47 keep_before = 0;
48 keep_after = 0;
49 zinit = false;
50 init = false;
51 params = false;
52 ffe = false;
53 tech = nullptr;
54 }
55 };
56
57 struct ShregmapTechGreenpak4 : ShregmapTech
58 {
59 bool analyze(vector<int> &taps, const vector<SigBit> &/*qbits*/)
60 {
61 if (GetSize(taps) > 2 && taps[0] == 0 && taps[2] < 17) {
62 taps.clear();
63 return true;
64 }
65
66 if (GetSize(taps) > 2)
67 return false;
68
69 if (taps.back() > 16) return false;
70
71 return true;
72 }
73
74 bool fixup(Cell *cell, dict<int, SigBit> &taps)
75 {
76 auto D = cell->getPort("\\D");
77 auto C = cell->getPort("\\C");
78
79 auto newcell = cell->module->addCell(NEW_ID, "\\GP_SHREG");
80 newcell->setPort("\\nRST", State::S1);
81 newcell->setPort("\\CLK", C);
82 newcell->setPort("\\IN", D);
83
84 int i = 0;
85 for (auto tap : taps) {
86 newcell->setPort(i ? "\\OUTB" : "\\OUTA", tap.second);
87 newcell->setParam(i ? "\\OUTB_TAP" : "\\OUTA_TAP", tap.first + 1);
88 i++;
89 }
90
91 cell->setParam("\\OUTA_INVERT", 0);
92 return false;
93 }
94 };
95
96 struct ShregmapTechXilinx7 : ShregmapTech
97 {
98 dict<SigBit, std::tuple<Cell*,int,int>> sigbit_to_shiftx_offset;
99 const ShregmapOptions &opts;
100
101 ShregmapTechXilinx7(const ShregmapOptions &opts) : opts(opts) {}
102
103 virtual void init(const Module* module, const SigMap &sigmap) override
104 {
105 for (const auto &i : module->cells_) {
106 auto cell = i.second;
107 if (cell->type == "$shiftx") {
108 if (cell->getParam("\\Y_WIDTH") != 1) continue;
109 int j = 0;
110 for (auto bit : sigmap(cell->getPort("\\A")))
111 sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, j++, 0);
112 log_assert(j == cell->getParam("\\A_WIDTH").as_int());
113 }
114 else if (cell->type == "$mux") {
115 int j = 0;
116 for (auto bit : sigmap(cell->getPort("\\A")))
117 sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 0, j++);
118 j = 0;
119 for (auto bit : sigmap(cell->getPort("\\B")))
120 sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 1, j++);
121 }
122 }
123 }
124
125 virtual void non_chain_user(const SigBit &bit, const Cell *cell, IdString port) override
126 {
127 auto it = sigbit_to_shiftx_offset.find(bit);
128 if (it == sigbit_to_shiftx_offset.end())
129 return;
130 if (cell) {
131 if (cell->type == "$shiftx" && port == "\\A")
132 return;
133 if (cell->type == "$mux" && (port == "\\A" || port == "\\B"))
134 return;
135 }
136 sigbit_to_shiftx_offset.erase(it);
137 }
138
139 virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) override
140 {
141 if (GetSize(taps) == 1)
142 return taps[0] >= opts.minlen-1 && sigbit_to_shiftx_offset.count(qbits[0]);
143
144 if (taps.back() < opts.minlen-1)
145 return false;
146
147 Cell *shiftx = nullptr;
148 int group = 0;
149 for (int i = 0; i < GetSize(taps); ++i) {
150 auto it = sigbit_to_shiftx_offset.find(qbits[i]);
151 if (it == sigbit_to_shiftx_offset.end())
152 return false;
153
154 // Check taps are sequential
155 if (i != taps[i])
156 return false;
157 // Check taps are not connected to a shift register,
158 // or sequential to the same shift register
159 if (i == 0) {
160 int offset;
161 std::tie(shiftx,offset,group) = it->second;
162 if (offset != i)
163 return false;
164 }
165 else {
166 Cell *shiftx_ = std::get<0>(it->second);
167 if (shiftx_ != shiftx)
168 return false;
169 int offset = std::get<1>(it->second);
170 if (offset != i)
171 return false;
172 int group_ = std::get<2>(it->second);
173 if (group_ != group)
174 return false;
175 }
176 }
177 log_assert(shiftx);
178
179 // Only map if $shiftx exclusively covers the shift register
180 if (shiftx->type == "$shiftx") {
181 if (GetSize(taps) > shiftx->getParam("\\A_WIDTH").as_int())
182 return false;
183 // Due to padding the most significant bits of A may be 1'bx,
184 // and if so, discount them
185 if (GetSize(taps) < shiftx->getParam("\\A_WIDTH").as_int()) {
186 const SigSpec A = shiftx->getPort("\\A");
187 const int A_width = shiftx->getParam("\\A_WIDTH").as_int();
188 for (int i = GetSize(taps); i < A_width; ++i)
189 if (A[i] != RTLIL::Sx) return false;
190 }
191 else if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int())
192 return false;
193 }
194 else if (shiftx->type == "$mux") {
195 if (GetSize(taps) != 2)
196 return false;
197 }
198 else log_abort();
199
200 return true;
201 }
202
203 virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) override
204 {
205 const auto &tap = *taps.begin();
206 auto bit = tap.second;
207
208 auto it = sigbit_to_shiftx_offset.find(bit);
209 log_assert(it != sigbit_to_shiftx_offset.end());
210
211 auto newcell = cell->module->addCell(NEW_ID, "$__XILINX_SHREG_");
212 newcell->set_src_attribute(cell->get_src_attribute());
213 newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH"));
214 newcell->setParam("\\INIT", cell->getParam("\\INIT"));
215 newcell->setParam("\\CLKPOL", cell->getParam("\\CLKPOL"));
216 newcell->setParam("\\ENPOL", cell->getParam("\\ENPOL"));
217
218 newcell->setPort("\\C", cell->getPort("\\C"));
219 newcell->setPort("\\D", cell->getPort("\\D"));
220 if (cell->hasPort("\\E"))
221 newcell->setPort("\\E", cell->getPort("\\E"));
222
223 Cell* shiftx = std::get<0>(it->second);
224 RTLIL::SigSpec l_wire, q_wire;
225 if (shiftx->type == "$shiftx") {
226 l_wire = shiftx->getPort("\\B");
227 q_wire = shiftx->getPort("\\Y");
228 shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
229 }
230 else if (shiftx->type == "$mux") {
231 l_wire = shiftx->getPort("\\S");
232 q_wire = shiftx->getPort("\\Y");
233 shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
234 }
235 else log_abort();
236
237 newcell->setPort("\\Q", q_wire);
238 newcell->setPort("\\L", l_wire);
239
240 return false;
241 }
242 };
243
244
245 struct ShregmapWorker
246 {
247 Module *module;
248 SigMap sigmap;
249
250 const ShregmapOptions &opts;
251 int dff_count, shreg_count;
252
253 pool<Cell*> remove_cells;
254 pool<SigBit> remove_init;
255
256 dict<SigBit, bool> sigbit_init;
257 dict<SigBit, Cell*> sigbit_chain_next;
258 dict<SigBit, Cell*> sigbit_chain_prev;
259 pool<SigBit> sigbit_with_non_chain_users;
260 pool<Cell*> chain_start_cells;
261
262 void make_sigbit_chain_next_prev()
263 {
264 for (auto wire : module->wires())
265 {
266 if (wire->port_output || wire->get_bool_attribute("\\keep")) {
267 for (auto bit : sigmap(wire)) {
268 sigbit_with_non_chain_users.insert(bit);
269 if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {});
270 }
271 }
272
273 if (wire->attributes.count("\\init")) {
274 SigSpec initsig = sigmap(wire);
275 Const initval = wire->attributes.at("\\init");
276 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
277 if (initval[i] == State::S0 && !opts.zinit)
278 sigbit_init[initsig[i]] = false;
279 else if (initval[i] == State::S1)
280 sigbit_init[initsig[i]] = true;
281 }
282 }
283
284 for (auto cell : module->cells())
285 {
286 if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute("\\keep"))
287 {
288 IdString d_port = opts.ffcells.at(cell->type).first;
289 IdString q_port = opts.ffcells.at(cell->type).second;
290
291 SigBit d_bit = sigmap(cell->getPort(d_port).as_bit());
292 SigBit q_bit = sigmap(cell->getPort(q_port).as_bit());
293
294 if (opts.init || sigbit_init.count(q_bit) == 0)
295 {
296 if (sigbit_chain_next.count(d_bit)) {
297 sigbit_with_non_chain_users.insert(d_bit);
298 } else
299 sigbit_chain_next[d_bit] = cell;
300
301 sigbit_chain_prev[q_bit] = cell;
302 continue;
303 }
304 }
305
306 for (auto conn : cell->connections())
307 if (cell->input(conn.first))
308 for (auto bit : sigmap(conn.second)) {
309 sigbit_with_non_chain_users.insert(bit);
310 if (opts.tech) opts.tech->non_chain_user(bit, cell, conn.first);
311 }
312 }
313 }
314
315 void find_chain_start_cells()
316 {
317 for (auto it : sigbit_chain_next)
318 {
319 if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first))
320 goto start_cell;
321
322 if (sigbit_chain_prev.count(it.first) != 0)
323 {
324 Cell *c1 = sigbit_chain_prev.at(it.first);
325 Cell *c2 = it.second;
326
327 if (c1->type != c2->type)
328 goto start_cell;
329
330 if (c1->parameters != c2->parameters)
331 goto start_cell;
332
333 IdString d_port = opts.ffcells.at(c1->type).first;
334 IdString q_port = opts.ffcells.at(c1->type).second;
335
336 auto c1_conn = c1->connections();
337 auto c2_conn = c1->connections();
338
339 c1_conn.erase(d_port);
340 c1_conn.erase(q_port);
341
342 c2_conn.erase(d_port);
343 c2_conn.erase(q_port);
344
345 if (c1_conn != c2_conn)
346 goto start_cell;
347
348 continue;
349 }
350
351 start_cell:
352 chain_start_cells.insert(it.second);
353 }
354 }
355
356 vector<Cell*> create_chain(Cell *start_cell)
357 {
358 vector<Cell*> chain;
359
360 Cell *c = start_cell;
361 while (c != nullptr)
362 {
363 chain.push_back(c);
364
365 IdString q_port = opts.ffcells.at(c->type).second;
366 SigBit q_bit = sigmap(c->getPort(q_port).as_bit());
367
368 if (sigbit_chain_next.count(q_bit) == 0)
369 break;
370
371 c = sigbit_chain_next.at(q_bit);
372 if (chain_start_cells.count(c) != 0)
373 break;
374 }
375
376 return chain;
377 }
378
379 void process_chain(vector<Cell*> &chain)
380 {
381 if (GetSize(chain) < opts.keep_before + opts.minlen + opts.keep_after)
382 return;
383
384 int cursor = opts.keep_before;
385 while (cursor < GetSize(chain) - opts.keep_after)
386 {
387 int depth = GetSize(chain) - opts.keep_after - cursor;
388
389 if (opts.maxlen > 0)
390 depth = std::min(opts.maxlen, depth);
391
392 Cell *first_cell = chain[cursor];
393 IdString q_port = opts.ffcells.at(first_cell->type).second;
394 dict<int, SigBit> taps_dict;
395
396 if (opts.tech)
397 {
398 vector<SigBit> qbits;
399 vector<int> taps;
400
401 for (int i = 0; i < depth; i++)
402 {
403 Cell *cell = chain[cursor+i];
404 auto qbit = sigmap(cell->getPort(q_port));
405 qbits.push_back(qbit);
406
407 if (sigbit_with_non_chain_users.count(qbit))
408 taps.push_back(i);
409 }
410
411 while (depth > 0)
412 {
413 if (taps.empty() || taps.back() < depth-1)
414 taps.push_back(depth-1);
415
416 if (opts.tech->analyze(taps, qbits))
417 break;
418
419 taps.pop_back();
420 depth--;
421 }
422
423 depth = 0;
424 for (auto tap : taps) {
425 taps_dict[tap] = qbits.at(tap);
426 log_assert(depth < tap+1);
427 depth = tap+1;
428 }
429 }
430
431 if (depth < 2) {
432 cursor++;
433 continue;
434 }
435
436 Cell *last_cell = chain[cursor+depth-1];
437
438 log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n",
439 log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), depth);
440
441 dff_count += depth;
442 shreg_count += 1;
443
444 string shreg_cell_type_str = "$__SHREG";
445 if (opts.params) {
446 shreg_cell_type_str += "_";
447 } else {
448 if (first_cell->type[1] != '_')
449 shreg_cell_type_str += "_";
450 shreg_cell_type_str += first_cell->type.substr(1);
451 }
452
453 if (opts.init) {
454 vector<State> initval;
455 for (int i = depth-1; i >= 0; i--) {
456 SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
457 if (sigbit_init.count(bit) == 0)
458 initval.push_back(State::Sx);
459 else if (sigbit_init.at(bit))
460 initval.push_back(State::S1);
461 else
462 initval.push_back(State::S0);
463 remove_init.insert(bit);
464 }
465 first_cell->setParam("\\INIT", initval);
466 }
467
468 if (opts.zinit)
469 for (int i = depth-1; i >= 0; i--) {
470 SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
471 remove_init.insert(bit);
472 }
473
474 if (opts.params)
475 {
476 int param_clkpol = -1;
477 int param_enpol = 2;
478
479 if (first_cell->type == "$_DFF_N_") param_clkpol = 0;
480 if (first_cell->type == "$_DFF_P_") param_clkpol = 1;
481
482 if (first_cell->type == "$_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
483 if (first_cell->type == "$_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
484 if (first_cell->type == "$_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
485 if (first_cell->type == "$_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
486
487 log_assert(param_clkpol >= 0);
488 first_cell->setParam("\\CLKPOL", param_clkpol);
489 if (opts.ffe) first_cell->setParam("\\ENPOL", param_enpol);
490 }
491
492 first_cell->type = shreg_cell_type_str;
493 first_cell->setPort(q_port, last_cell->getPort(q_port));
494 first_cell->setParam("\\DEPTH", depth);
495
496 if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
497 remove_cells.insert(first_cell);
498
499 for (int i = 1; i < depth; i++)
500 remove_cells.insert(chain[cursor+i]);
501 cursor += depth;
502 }
503 }
504
505 void cleanup()
506 {
507 for (auto cell : remove_cells)
508 module->remove(cell);
509
510 for (auto wire : module->wires())
511 {
512 if (wire->attributes.count("\\init") == 0)
513 continue;
514
515 SigSpec initsig = sigmap(wire);
516 Const &initval = wire->attributes.at("\\init");
517
518 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
519 if (remove_init.count(initsig[i]))
520 initval[i] = State::Sx;
521
522 if (SigSpec(initval).is_fully_undef())
523 wire->attributes.erase("\\init");
524 }
525
526 remove_cells.clear();
527 sigbit_chain_next.clear();
528 sigbit_chain_prev.clear();
529 chain_start_cells.clear();
530 }
531
532 ShregmapWorker(Module *module, const ShregmapOptions &opts) :
533 module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0)
534 {
535 if (opts.tech)
536 opts.tech->init(module, sigmap);
537
538 make_sigbit_chain_next_prev();
539 find_chain_start_cells();
540
541 for (auto c : chain_start_cells) {
542 vector<Cell*> chain = create_chain(c);
543 process_chain(chain);
544 }
545
546 cleanup();
547 }
548 };
549
550 struct ShregmapPass : public Pass {
551 ShregmapPass() : Pass("shregmap", "map shift registers") { }
552 void help() YS_OVERRIDE
553 {
554 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
555 log("\n");
556 log(" shregmap [options] [selection]\n");
557 log("\n");
558 log("This pass converts chains of $_DFF_[NP]_ gates to target specific shift register\n");
559 log("primitives. The generated shift register will be of type $__SHREG_DFF_[NP]_ and\n");
560 log("will use the same interface as the original $_DFF_*_ cells. The cell parameter\n");
561 log("'DEPTH' will contain the depth of the shift register. Use a target-specific\n");
562 log("'techmap' map file to convert those cells to the actual target cells.\n");
563 log("\n");
564 log(" -minlen N\n");
565 log(" minimum length of shift register (default = 2)\n");
566 log(" (this is the length after -keep_before and -keep_after)\n");
567 log("\n");
568 log(" -maxlen N\n");
569 log(" maximum length of shift register (default = no limit)\n");
570 log(" larger chains will be mapped to multiple shift register instances\n");
571 log("\n");
572 log(" -keep_before N\n");
573 log(" number of DFFs to keep before the shift register (default = 0)\n");
574 log("\n");
575 log(" -keep_after N\n");
576 log(" number of DFFs to keep after the shift register (default = 0)\n");
577 log("\n");
578 log(" -clkpol pos|neg|any\n");
579 log(" limit match to only positive or negative edge clocks. (default = any)\n");
580 log("\n");
581 log(" -enpol pos|neg|none|any_or_none|any\n");
582 log(" limit match to FFs with the specified enable polarity. (default = none)\n");
583 log("\n");
584 log(" -match <cell_type>[:<d_port_name>:<q_port_name>]\n");
585 log(" match the specified cells instead of $_DFF_N_ and $_DFF_P_. If\n");
586 log(" ':<d_port_name>:<q_port_name>' is omitted then 'D' and 'Q' is used\n");
587 log(" by default. E.g. the option '-clkpol pos' is just an alias for\n");
588 log(" '-match $_DFF_P_', which is an alias for '-match $_DFF_P_:D:Q'.\n");
589 log("\n");
590 log(" -params\n");
591 log(" instead of encoding the clock and enable polarity in the cell name by\n");
592 log(" deriving from the original cell name, simply name all generated cells\n");
593 log(" $__SHREG_ and use CLKPOL and ENPOL parameters. An ENPOL value of 2 is\n");
594 log(" used to denote cells without enable input. The ENPOL parameter is\n");
595 log(" omitted when '-enpol none' (or no -enpol option) is passed.\n");
596 log("\n");
597 log(" -zinit\n");
598 log(" assume the shift register is automatically zero-initialized, so it\n");
599 log(" becomes legal to merge zero initialized FFs into the shift register.\n");
600 log("\n");
601 log(" -init\n");
602 log(" map initialized registers to the shift reg, add an INIT parameter to\n");
603 log(" generated cells with the initialization value. (first bit to shift out\n");
604 log(" in LSB position)\n");
605 log("\n");
606 log(" -tech greenpak4\n");
607 log(" map to greenpak4 shift registers.\n");
608 log("\n");
609 log(" -tech xilinx\n");
610 log(" map to xilinx dynamic-length shift registers.\n");
611 log("\n");
612 }
613 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
614 {
615 ShregmapOptions opts;
616 string clkpol, enpol;
617
618 log_header(design, "Executing SHREGMAP pass (map shift registers).\n");
619
620 size_t argidx;
621 for (argidx = 1; argidx < args.size(); argidx++)
622 {
623 if (args[argidx] == "-clkpol" && argidx+1 < args.size()) {
624 clkpol = args[++argidx];
625 continue;
626 }
627 if (args[argidx] == "-enpol" && argidx+1 < args.size()) {
628 enpol = args[++argidx];
629 continue;
630 }
631 if (args[argidx] == "-match" && argidx+1 < args.size()) {
632 vector<string> match_args = split_tokens(args[++argidx], ":");
633 if (GetSize(match_args) < 2)
634 match_args.push_back("D");
635 if (GetSize(match_args) < 3)
636 match_args.push_back("Q");
637 IdString id_cell_type(RTLIL::escape_id(match_args[0]));
638 IdString id_d_port_name(RTLIL::escape_id(match_args[1]));
639 IdString id_q_port_name(RTLIL::escape_id(match_args[2]));
640 opts.ffcells[id_cell_type] = make_pair(id_d_port_name, id_q_port_name);
641 continue;
642 }
643 if (args[argidx] == "-minlen" && argidx+1 < args.size()) {
644 opts.minlen = atoi(args[++argidx].c_str());
645 continue;
646 }
647 if (args[argidx] == "-maxlen" && argidx+1 < args.size()) {
648 opts.maxlen = atoi(args[++argidx].c_str());
649 continue;
650 }
651 if (args[argidx] == "-keep_before" && argidx+1 < args.size()) {
652 opts.keep_before = atoi(args[++argidx].c_str());
653 continue;
654 }
655 if (args[argidx] == "-keep_after" && argidx+1 < args.size()) {
656 opts.keep_after = atoi(args[++argidx].c_str());
657 continue;
658 }
659 if (args[argidx] == "-tech" && argidx+1 < args.size() && opts.tech == nullptr) {
660 string tech = args[++argidx];
661 if (tech == "greenpak4") {
662 clkpol = "pos";
663 opts.zinit = true;
664 opts.tech = new ShregmapTechGreenpak4;
665 }
666 else if (tech == "xilinx") {
667 opts.init = true;
668 opts.params = true;
669 enpol = "any_or_none";
670 opts.tech = new ShregmapTechXilinx7(opts);
671 } else {
672 argidx--;
673 break;
674 }
675 continue;
676 }
677 if (args[argidx] == "-zinit") {
678 opts.zinit = true;
679 continue;
680 }
681 if (args[argidx] == "-init") {
682 opts.init = true;
683 continue;
684 }
685 if (args[argidx] == "-params") {
686 opts.params = true;
687 continue;
688 }
689 break;
690 }
691 extra_args(args, argidx, design);
692
693 if (opts.zinit && opts.init)
694 log_cmd_error("Options -zinit and -init are exclusive!\n");
695
696 if (opts.ffcells.empty())
697 {
698 bool clk_pos = clkpol == "" || clkpol == "pos" || clkpol == "any";
699 bool clk_neg = clkpol == "" || clkpol == "neg" || clkpol == "any";
700
701 bool en_none = enpol == "" || enpol == "none" || enpol == "any_or_none";
702 bool en_pos = enpol == "pos" || enpol == "any" || enpol == "any_or_none";
703 bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none";
704
705 if (clk_pos && en_none)
706 opts.ffcells["$_DFF_P_"] = make_pair(IdString("\\D"), IdString("\\Q"));
707 if (clk_neg && en_none)
708 opts.ffcells["$_DFF_N_"] = make_pair(IdString("\\D"), IdString("\\Q"));
709
710 if (clk_pos && en_pos)
711 opts.ffcells["$_DFFE_PP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
712 if (clk_pos && en_neg)
713 opts.ffcells["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
714
715 if (clk_neg && en_pos)
716 opts.ffcells["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
717 if (clk_neg && en_neg)
718 opts.ffcells["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
719
720 if (en_pos || en_neg)
721 opts.ffe = true;
722 }
723 else
724 {
725 if (!clkpol.empty())
726 log_cmd_error("Options -clkpol and -match are exclusive!\n");
727 if (!enpol.empty())
728 log_cmd_error("Options -enpol and -match are exclusive!\n");
729 if (opts.params)
730 log_cmd_error("Options -params and -match are exclusive!\n");
731 }
732
733 int dff_count = 0;
734 int shreg_count = 0;
735
736 for (auto module : design->selected_modules()) {
737 ShregmapWorker worker(module, opts);
738 dff_count += worker.dff_count;
739 shreg_count += worker.shreg_count;
740 }
741
742 log("Converted %d dff cells into %d shift registers.\n", dff_count, shreg_count);
743
744 if (opts.tech != nullptr) {
745 delete opts.tech;
746 opts.tech = nullptr;
747 }
748 }
749 } ShregmapPass;
750
751 PRIVATE_NAMESPACE_END