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Revert "Continue support for ShregmapTechXilinx7Static"
[yosys.git] / passes / techmap / shregmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22
23 USING_YOSYS_NAMESPACE
24 PRIVATE_NAMESPACE_BEGIN
25
26 struct ShregmapTech
27 {
28 virtual ~ShregmapTech() { }
29 virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {}
30 virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {}
31 virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) = 0;
32 virtual RTLIL::Cell* fixup(Cell *cell, dict<int, SigBit> &taps) = 0;
33 };
34
35 struct ShregmapOptions
36 {
37 int minlen, maxlen;
38 int keep_before, keep_after;
39 bool zinit, init, params, ffe;
40 dict<IdString, pair<IdString, IdString>> ffcells;
41 ShregmapTech *tech;
42
43 ShregmapOptions()
44 {
45 minlen = 2;
46 maxlen = 0;
47 keep_before = 0;
48 keep_after = 0;
49 zinit = false;
50 init = false;
51 params = false;
52 ffe = false;
53 tech = nullptr;
54 }
55 };
56
57 struct ShregmapTechGreenpak4 : ShregmapTech
58 {
59 virtual bool analyze(vector<int> &taps, const vector<SigBit> &/*qbits*/) override
60 {
61 if (GetSize(taps) > 2 && taps[0] == 0 && taps[2] < 17) {
62 taps.clear();
63 return true;
64 }
65
66 if (GetSize(taps) > 2)
67 return false;
68
69 if (taps.back() > 16) return false;
70
71 return true;
72 }
73
74 virtual RTLIL::Cell* fixup(Cell *cell, dict<int, SigBit> &taps) override
75 {
76 auto D = cell->getPort("\\D");
77 auto C = cell->getPort("\\C");
78
79 auto newcell = cell->module->addCell(NEW_ID, "\\GP_SHREG");
80 newcell->setPort("\\nRST", State::S1);
81 newcell->setPort("\\CLK", C);
82 newcell->setPort("\\IN", D);
83
84 int i = 0;
85 for (auto tap : taps) {
86 newcell->setPort(i ? "\\OUTB" : "\\OUTA", tap.second);
87 newcell->setParam(i ? "\\OUTB_TAP" : "\\OUTA_TAP", tap.first + 1);
88 i++;
89 }
90
91 cell->setParam("\\OUTA_INVERT", 0);
92 return newcell;
93 }
94 };
95
96 struct ShregmapTechXilinx7Static : ShregmapTech
97 {
98 const ShregmapOptions &opts;
99
100 ShregmapTechXilinx7Static(const ShregmapOptions &opts) : opts(opts) {}
101
102 virtual bool analyze(vector<int> &taps, const vector<SigBit> &/*qbits*/) override
103 {
104 if (GetSize(taps) == 1)
105 return taps[0] >= opts.minlen-1;
106
107 if (taps.back() < opts.minlen-1)
108 return false;
109
110 return true;
111 }
112
113 virtual RTLIL::Cell* fixup(Cell *cell, dict<int, SigBit> &/*taps*/) override
114 {
115 auto newcell = cell->module->addCell(NEW_ID, "$__SHREG_");
116 newcell->set_src_attribute(cell->get_src_attribute());
117 newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH"));
118 newcell->setParam("\\INIT", cell->getParam("\\INIT"));
119
120 if (cell->type.in("$__SHREG_DFF_N_", "$__SHREG_DFF_P_",
121 "$__SHREG_DFFE_NN_", "$__SHREG_DFFE_NP_", "$__SHREG_DFFE_PN_", "$__SHREG_DFFE_PP_")) {
122 int param_clkpol = -1;
123 int param_enpol = 2;
124 if (cell->type == "$__SHREG_DFF_N_") param_clkpol = 0;
125 else if (cell->type == "$__SHREG_DFF_P_") param_clkpol = 1;
126 else if (cell->type == "$__SHREG_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
127 else if (cell->type == "$__SHREG_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
128 else if (cell->type == "$__SHREG_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
129 else if (cell->type == "$__SHREG_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
130 else log_abort();
131
132 log_assert(param_clkpol >= 0);
133 newcell->setParam("\\CLKPOL", param_clkpol);
134 newcell->setParam("\\ENPOL", param_enpol);
135
136 if (cell->hasPort("\\E"))
137 newcell->setPort("\\E", cell->getPort("\\E"));
138 }
139 else if (cell->type.in("$__SHREG_FDRE_", "$__SHREG_FDSE_", "$__SHREG_FDCE_", "$__SHREG_FDPE_")) {
140 if (cell->getParam("\\IS_C_INVERTED").as_bool())
141 newcell->setParam("\\CLKPOL", 0);
142 else
143 newcell->setParam("\\CLKPOL", 1);
144 newcell->setParam("\\ENPOL", 1);
145
146 newcell->setPort("\\E", cell->getPort("\\CE"));
147 }
148 else if (cell->type.in("$__SHREG_FDRE_1_", "$__SHREG_FDSE_1_", "$__SHREG_FDCE_1_", "$__SHREG_FDPE_1_")) {
149 newcell->setParam("\\CLKPOL", 0);
150
151 newcell->setPort("\\E", cell->getPort("\\CE"));
152 }
153 else log_abort();
154
155 newcell->setParam("\\ENPOL", 1);
156
157 newcell->setPort("\\C", cell->getPort("\\C"));
158 newcell->setPort("\\D", cell->getPort("\\D"));
159 newcell->setPort("\\Q", cell->getPort("\\Q"));
160
161 return newcell;
162 }
163 };
164
165 struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static
166 {
167 dict<SigBit, std::tuple<Cell*,int,int>> sigbit_to_shiftx_offset;
168
169 ShregmapTechXilinx7Dynamic(const ShregmapOptions &opts) : ShregmapTechXilinx7Static(opts) {}
170
171 virtual void init(const Module* module, const SigMap &sigmap) override
172 {
173 for (const auto &i : module->cells_) {
174 auto cell = i.second;
175 if (cell->type == "$shiftx") {
176 if (cell->getParam("\\Y_WIDTH") != 1) continue;
177 int j = 0;
178 for (auto bit : sigmap(cell->getPort("\\A")))
179 sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, j++, 0);
180 log_assert(j == cell->getParam("\\A_WIDTH").as_int());
181 }
182 else if (cell->type == "$mux") {
183 int j = 0;
184 for (auto bit : sigmap(cell->getPort("\\A")))
185 sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 0, j++);
186 j = 0;
187 for (auto bit : sigmap(cell->getPort("\\B")))
188 sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 1, j++);
189 }
190 }
191 }
192
193 virtual void non_chain_user(const SigBit &bit, const Cell *cell, IdString port) override
194 {
195 auto it = sigbit_to_shiftx_offset.find(bit);
196 if (it == sigbit_to_shiftx_offset.end())
197 return;
198 if (cell) {
199 if (cell->type == "$shiftx" && port == "\\A")
200 return;
201 if (cell->type == "$mux" && (port == "\\A" || port == "\\B"))
202 return;
203 }
204 sigbit_to_shiftx_offset.erase(it);
205 }
206
207 virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) override
208 {
209 if (GetSize(taps) == 1)
210 return taps[0] >= opts.minlen-1 && sigbit_to_shiftx_offset.count(qbits[0]);
211
212 if (taps.back() < opts.minlen-1)
213 return false;
214
215 Cell *shiftx = nullptr;
216 int group = 0;
217 for (int i = 0; i < GetSize(taps); ++i) {
218 auto it = sigbit_to_shiftx_offset.find(qbits[i]);
219 if (it == sigbit_to_shiftx_offset.end())
220 return false;
221
222 // Check taps are sequential
223 if (i != taps[i])
224 return false;
225 // Check taps are not connected to a shift register,
226 // or sequential to the same shift register
227 if (i == 0) {
228 int offset;
229 std::tie(shiftx,offset,group) = it->second;
230 if (offset != i)
231 return false;
232 }
233 else {
234 Cell *shiftx_ = std::get<0>(it->second);
235 if (shiftx_ != shiftx)
236 return false;
237 int offset = std::get<1>(it->second);
238 if (offset != i)
239 return false;
240 int group_ = std::get<2>(it->second);
241 if (group_ != group)
242 return false;
243 }
244 }
245 log_assert(shiftx);
246
247 // Only map if $shiftx exclusively covers the shift register
248 if (shiftx->type == "$shiftx") {
249 if (GetSize(taps) > shiftx->getParam("\\A_WIDTH").as_int())
250 return false;
251 // Due to padding the most significant bits of A may be 1'bx,
252 // and if so, discount them
253 if (GetSize(taps) < shiftx->getParam("\\A_WIDTH").as_int()) {
254 const SigSpec A = shiftx->getPort("\\A");
255 const int A_width = shiftx->getParam("\\A_WIDTH").as_int();
256 for (int i = GetSize(taps); i < A_width; ++i)
257 if (A[i] != RTLIL::Sx) return false;
258 }
259 else if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int())
260 return false;
261 }
262 else if (shiftx->type == "$mux") {
263 if (GetSize(taps) != 2)
264 return false;
265 }
266 else log_abort();
267
268 return true;
269 }
270
271 virtual RTLIL::Cell* fixup(Cell *cell, dict<int, SigBit> &taps) override
272 {
273 const auto &tap = *taps.begin();
274 auto bit = tap.second;
275
276 auto it = sigbit_to_shiftx_offset.find(bit);
277 log_assert(it != sigbit_to_shiftx_offset.end());
278
279 RTLIL::Cell* newcell = ShregmapTechXilinx7Static::fixup(cell, taps);
280 log_assert(newcell);
281 log_assert(newcell->type == "$__SHREG_");
282 newcell->type = "$__XILINX_SHREG_";
283
284 Cell* shiftx = std::get<0>(it->second);
285 RTLIL::SigSpec l_wire;
286 if (shiftx->type == "$shiftx")
287 l_wire = shiftx->getPort("\\B");
288 else if (shiftx->type == "$mux")
289 l_wire = shiftx->getPort("\\S");
290 else log_abort();
291
292 newcell->setPort("\\L", l_wire);
293 newcell->setPort("\\Q", shiftx->getPort("\\Y"));
294 shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
295
296 return newcell;
297 }
298 };
299
300
301 struct ShregmapWorker
302 {
303 Module *module;
304 SigMap sigmap;
305
306 const ShregmapOptions &opts;
307 int dff_count, shreg_count;
308
309 pool<Cell*> remove_cells;
310 pool<SigBit> remove_init;
311
312 dict<SigBit, bool> sigbit_init;
313 dict<SigBit, Cell*> sigbit_chain_next;
314 dict<SigBit, Cell*> sigbit_chain_prev;
315 pool<SigBit> sigbit_with_non_chain_users;
316 pool<Cell*> chain_start_cells;
317
318 void make_sigbit_chain_next_prev()
319 {
320 for (auto wire : module->wires())
321 {
322 if (wire->port_output || wire->get_bool_attribute("\\keep")) {
323 for (auto bit : sigmap(wire)) {
324 sigbit_with_non_chain_users.insert(bit);
325 if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {});
326 }
327 }
328
329 if (wire->attributes.count("\\init")) {
330 SigSpec initsig = sigmap(wire);
331 Const initval = wire->attributes.at("\\init");
332 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
333 if (initval[i] == State::S0 && !opts.zinit)
334 sigbit_init[initsig[i]] = false;
335 else if (initval[i] == State::S1)
336 sigbit_init[initsig[i]] = true;
337 }
338 }
339
340 for (auto cell : module->cells())
341 {
342 if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute("\\keep"))
343 {
344 IdString d_port = opts.ffcells.at(cell->type).first;
345 IdString q_port = opts.ffcells.at(cell->type).second;
346
347 SigBit d_bit = sigmap(cell->getPort(d_port).as_bit());
348 SigBit q_bit = sigmap(cell->getPort(q_port).as_bit());
349
350 if (opts.init || sigbit_init.count(q_bit) == 0)
351 {
352 if (sigbit_chain_next.count(d_bit)) {
353 sigbit_with_non_chain_users.insert(d_bit);
354 } else
355 sigbit_chain_next[d_bit] = cell;
356
357 sigbit_chain_prev[q_bit] = cell;
358 continue;
359 }
360 }
361
362 for (auto conn : cell->connections())
363 if (cell->input(conn.first))
364 for (auto bit : sigmap(conn.second)) {
365 sigbit_with_non_chain_users.insert(bit);
366 if (opts.tech) opts.tech->non_chain_user(bit, cell, conn.first);
367 }
368 }
369 }
370
371 void find_chain_start_cells()
372 {
373 for (auto it : sigbit_chain_next)
374 {
375 if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first))
376 goto start_cell;
377
378 if (sigbit_chain_prev.count(it.first) != 0)
379 {
380 Cell *c1 = sigbit_chain_prev.at(it.first);
381 Cell *c2 = it.second;
382
383 if (c1->type != c2->type)
384 goto start_cell;
385
386 if (c1->parameters != c2->parameters)
387 goto start_cell;
388
389 IdString d_port = opts.ffcells.at(c1->type).first;
390 IdString q_port = opts.ffcells.at(c1->type).second;
391
392 auto c1_conn = c1->connections();
393 auto c2_conn = c1->connections();
394
395 c1_conn.erase(d_port);
396 c1_conn.erase(q_port);
397
398 c2_conn.erase(d_port);
399 c2_conn.erase(q_port);
400
401 if (c1_conn != c2_conn)
402 goto start_cell;
403
404 continue;
405 }
406
407 start_cell:
408 chain_start_cells.insert(it.second);
409 }
410 }
411
412 vector<Cell*> create_chain(Cell *start_cell)
413 {
414 vector<Cell*> chain;
415
416 Cell *c = start_cell;
417 while (c != nullptr)
418 {
419 chain.push_back(c);
420
421 IdString q_port = opts.ffcells.at(c->type).second;
422 SigBit q_bit = sigmap(c->getPort(q_port).as_bit());
423
424 if (sigbit_chain_next.count(q_bit) == 0)
425 break;
426
427 c = sigbit_chain_next.at(q_bit);
428 if (chain_start_cells.count(c) != 0)
429 break;
430 }
431
432 return chain;
433 }
434
435 void process_chain(vector<Cell*> &chain)
436 {
437 if (GetSize(chain) < opts.keep_before + opts.minlen + opts.keep_after)
438 return;
439
440 int cursor = opts.keep_before;
441 while (cursor < GetSize(chain) - opts.keep_after)
442 {
443 int depth = GetSize(chain) - opts.keep_after - cursor;
444
445 if (opts.maxlen > 0)
446 depth = std::min(opts.maxlen, depth);
447
448 Cell *first_cell = chain[cursor];
449 IdString q_port = opts.ffcells.at(first_cell->type).second;
450 dict<int, SigBit> taps_dict;
451
452 if (opts.tech)
453 {
454 vector<SigBit> qbits;
455 vector<int> taps;
456
457 for (int i = 0; i < depth; i++)
458 {
459 Cell *cell = chain[cursor+i];
460 auto qbit = sigmap(cell->getPort(q_port));
461 qbits.push_back(qbit);
462
463 if (sigbit_with_non_chain_users.count(qbit))
464 taps.push_back(i);
465 }
466
467 while (depth > 0)
468 {
469 if (taps.empty() || taps.back() < depth-1)
470 taps.push_back(depth-1);
471
472 if (opts.tech->analyze(taps, qbits))
473 break;
474
475 taps.pop_back();
476 depth--;
477 }
478
479 depth = 0;
480 for (auto tap : taps) {
481 taps_dict[tap] = qbits.at(tap);
482 log_assert(depth < tap+1);
483 depth = tap+1;
484 }
485 }
486
487 if (depth < 2) {
488 cursor++;
489 continue;
490 }
491
492 Cell *last_cell = chain[cursor+depth-1];
493
494 log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n",
495 log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), depth);
496
497 dff_count += depth;
498 shreg_count += 1;
499
500 string shreg_cell_type_str = "$__SHREG";
501 if (opts.params) {
502 shreg_cell_type_str += "_";
503 } else {
504 if (first_cell->type[1] != '_')
505 shreg_cell_type_str += "_";
506 shreg_cell_type_str += first_cell->type.substr(1);
507 }
508
509 if (opts.init) {
510 vector<State> initval;
511 for (int i = depth-1; i >= 0; i--) {
512 SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
513 if (sigbit_init.count(bit) == 0)
514 initval.push_back(State::Sx);
515 else if (sigbit_init.at(bit))
516 initval.push_back(State::S1);
517 else
518 initval.push_back(State::S0);
519 remove_init.insert(bit);
520 }
521 first_cell->setParam("\\INIT", initval);
522 }
523
524 if (opts.zinit)
525 for (int i = depth-1; i >= 0; i--) {
526 SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
527 remove_init.insert(bit);
528 }
529
530 if (opts.params)
531 {
532 int param_clkpol = -1;
533 int param_enpol = 2;
534
535 if (first_cell->type == "$_DFF_N_") param_clkpol = 0;
536 if (first_cell->type == "$_DFF_P_") param_clkpol = 1;
537
538 if (first_cell->type == "$_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
539 if (first_cell->type == "$_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
540 if (first_cell->type == "$_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
541 if (first_cell->type == "$_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
542
543 log_assert(param_clkpol >= 0);
544 first_cell->setParam("\\CLKPOL", param_clkpol);
545 if (opts.ffe) first_cell->setParam("\\ENPOL", param_enpol);
546 }
547
548 first_cell->type = shreg_cell_type_str;
549 first_cell->setPort(q_port, last_cell->getPort(q_port));
550 first_cell->setParam("\\DEPTH", depth);
551
552 if (opts.tech != nullptr && opts.tech->fixup(first_cell, taps_dict))
553 remove_cells.insert(first_cell);
554
555 for (int i = 1; i < depth; i++)
556 remove_cells.insert(chain[cursor+i]);
557 cursor += depth;
558 }
559 }
560
561 void cleanup()
562 {
563 for (auto cell : remove_cells)
564 module->remove(cell);
565
566 for (auto wire : module->wires())
567 {
568 if (wire->attributes.count("\\init") == 0)
569 continue;
570
571 SigSpec initsig = sigmap(wire);
572 Const &initval = wire->attributes.at("\\init");
573
574 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
575 if (remove_init.count(initsig[i]))
576 initval[i] = State::Sx;
577
578 if (SigSpec(initval).is_fully_undef())
579 wire->attributes.erase("\\init");
580 }
581
582 remove_cells.clear();
583 sigbit_chain_next.clear();
584 sigbit_chain_prev.clear();
585 chain_start_cells.clear();
586 }
587
588 ShregmapWorker(Module *module, const ShregmapOptions &opts) :
589 module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0)
590 {
591 if (opts.tech)
592 opts.tech->init(module, sigmap);
593
594 make_sigbit_chain_next_prev();
595 find_chain_start_cells();
596
597 for (auto c : chain_start_cells) {
598 vector<Cell*> chain = create_chain(c);
599 process_chain(chain);
600 }
601
602 cleanup();
603 }
604 };
605
606 struct ShregmapPass : public Pass {
607 ShregmapPass() : Pass("shregmap", "map shift registers") { }
608 void help() YS_OVERRIDE
609 {
610 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
611 log("\n");
612 log(" shregmap [options] [selection]\n");
613 log("\n");
614 log("This pass converts chains of $_DFF_[NP]_ gates to target specific shift register\n");
615 log("primitives. The generated shift register will be of type $__SHREG_DFF_[NP]_ and\n");
616 log("will use the same interface as the original $_DFF_*_ cells. The cell parameter\n");
617 log("'DEPTH' will contain the depth of the shift register. Use a target-specific\n");
618 log("'techmap' map file to convert those cells to the actual target cells.\n");
619 log("\n");
620 log(" -minlen N\n");
621 log(" minimum length of shift register (default = 2)\n");
622 log(" (this is the length after -keep_before and -keep_after)\n");
623 log("\n");
624 log(" -maxlen N\n");
625 log(" maximum length of shift register (default = no limit)\n");
626 log(" larger chains will be mapped to multiple shift register instances\n");
627 log("\n");
628 log(" -keep_before N\n");
629 log(" number of DFFs to keep before the shift register (default = 0)\n");
630 log("\n");
631 log(" -keep_after N\n");
632 log(" number of DFFs to keep after the shift register (default = 0)\n");
633 log("\n");
634 log(" -clkpol pos|neg|any\n");
635 log(" limit match to only positive or negative edge clocks. (default = any)\n");
636 log("\n");
637 log(" -enpol pos|neg|none|any_or_none|any\n");
638 log(" limit match to FFs with the specified enable polarity. (default = none)\n");
639 log("\n");
640 log(" -match <cell_type>[:<d_port_name>:<q_port_name>]\n");
641 log(" match the specified cells instead of $_DFF_N_ and $_DFF_P_. If\n");
642 log(" ':<d_port_name>:<q_port_name>' is omitted then 'D' and 'Q' is used\n");
643 log(" by default. E.g. the option '-clkpol pos' is just an alias for\n");
644 log(" '-match $_DFF_P_', which is an alias for '-match $_DFF_P_:D:Q'.\n");
645 log("\n");
646 log(" -params\n");
647 log(" instead of encoding the clock and enable polarity in the cell name by\n");
648 log(" deriving from the original cell name, simply name all generated cells\n");
649 log(" $__SHREG_ and use CLKPOL and ENPOL parameters. An ENPOL value of 2 is\n");
650 log(" used to denote cells without enable input. The ENPOL parameter is\n");
651 log(" omitted when '-enpol none' (or no -enpol option) is passed.\n");
652 log("\n");
653 log(" -zinit\n");
654 log(" assume the shift register is automatically zero-initialized, so it\n");
655 log(" becomes legal to merge zero initialized FFs into the shift register.\n");
656 log("\n");
657 log(" -init\n");
658 log(" map initialized registers to the shift reg, add an INIT parameter to\n");
659 log(" generated cells with the initialization value. (first bit to shift out\n");
660 log(" in LSB position)\n");
661 log("\n");
662 log(" -tech greenpak4\n");
663 log(" map to greenpak4 shift registers.\n");
664 log("\n");
665 log(" -tech xilinx\n");
666 log(" map to xilinx dynamic-length shift registers.\n");
667 log("\n");
668 }
669 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
670 {
671 ShregmapOptions opts;
672 string clkpol, enpol;
673
674 log_header(design, "Executing SHREGMAP pass (map shift registers).\n");
675
676 size_t argidx;
677 for (argidx = 1; argidx < args.size(); argidx++)
678 {
679 if (args[argidx] == "-clkpol" && argidx+1 < args.size()) {
680 clkpol = args[++argidx];
681 continue;
682 }
683 if (args[argidx] == "-enpol" && argidx+1 < args.size()) {
684 enpol = args[++argidx];
685 continue;
686 }
687 if (args[argidx] == "-match" && argidx+1 < args.size()) {
688 vector<string> match_args = split_tokens(args[++argidx], ":");
689 if (GetSize(match_args) < 2)
690 match_args.push_back("D");
691 if (GetSize(match_args) < 3)
692 match_args.push_back("Q");
693 IdString id_cell_type(RTLIL::escape_id(match_args[0]));
694 IdString id_d_port_name(RTLIL::escape_id(match_args[1]));
695 IdString id_q_port_name(RTLIL::escape_id(match_args[2]));
696 opts.ffcells[id_cell_type] = make_pair(id_d_port_name, id_q_port_name);
697 continue;
698 }
699 if (args[argidx] == "-minlen" && argidx+1 < args.size()) {
700 opts.minlen = atoi(args[++argidx].c_str());
701 continue;
702 }
703 if (args[argidx] == "-maxlen" && argidx+1 < args.size()) {
704 opts.maxlen = atoi(args[++argidx].c_str());
705 continue;
706 }
707 if (args[argidx] == "-keep_before" && argidx+1 < args.size()) {
708 opts.keep_before = atoi(args[++argidx].c_str());
709 continue;
710 }
711 if (args[argidx] == "-keep_after" && argidx+1 < args.size()) {
712 opts.keep_after = atoi(args[++argidx].c_str());
713 continue;
714 }
715 if (args[argidx] == "-tech" && argidx+1 < args.size() && opts.tech == nullptr) {
716 string tech = args[++argidx];
717 if (tech == "greenpak4") {
718 clkpol = "pos";
719 opts.zinit = true;
720 opts.tech = new ShregmapTechGreenpak4;
721 }
722 else if (tech == "xilinx_static" || tech == "xilinx_dynamic") {
723 opts.init = true;
724 opts.ffcells["$_DFF_P_"] = make_pair(IdString("\\D"), IdString("\\Q"));
725 opts.ffcells["$_DFF_N_"] = make_pair(IdString("\\D"), IdString("\\Q"));
726 opts.ffcells["$_DFFE_PP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
727 opts.ffcells["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
728 opts.ffcells["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
729 opts.ffcells["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
730 opts.ffcells["FDRE"] = make_pair(IdString("\\D"), IdString("\\Q"));
731 opts.ffcells["FDRE_1"] = make_pair(IdString("\\D"), IdString("\\Q"));
732 opts.ffcells["FDSE"] = make_pair(IdString("\\D"), IdString("\\Q"));
733 opts.ffcells["FDSE_1"] = make_pair(IdString("\\D"), IdString("\\Q"));
734 opts.ffcells["FDCE"] = make_pair(IdString("\\D"), IdString("\\Q"));
735 opts.ffcells["FDCE_1"] = make_pair(IdString("\\D"), IdString("\\Q"));
736 opts.ffcells["FDPE"] = make_pair(IdString("\\D"), IdString("\\Q"));
737 opts.ffcells["FDPE_1"] = make_pair(IdString("\\D"), IdString("\\Q"));
738 if (tech == "xilinx_static")
739 opts.tech = new ShregmapTechXilinx7Dynamic(opts);
740 else if (tech == "xilinx_dynamic")
741 opts.tech = new ShregmapTechXilinx7Dynamic(opts);
742 } else {
743 argidx--;
744 break;
745 }
746 continue;
747 }
748 if (args[argidx] == "-zinit") {
749 opts.zinit = true;
750 continue;
751 }
752 if (args[argidx] == "-init") {
753 opts.init = true;
754 continue;
755 }
756 if (args[argidx] == "-params") {
757 opts.params = true;
758 continue;
759 }
760 break;
761 }
762 extra_args(args, argidx, design);
763
764 if (opts.zinit && opts.init)
765 log_cmd_error("Options -zinit and -init are exclusive!\n");
766
767 if (opts.ffcells.empty())
768 {
769 bool clk_pos = clkpol == "" || clkpol == "pos" || clkpol == "any";
770 bool clk_neg = clkpol == "" || clkpol == "neg" || clkpol == "any";
771
772 bool en_none = enpol == "" || enpol == "none" || enpol == "any_or_none";
773 bool en_pos = enpol == "pos" || enpol == "any" || enpol == "any_or_none";
774 bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none";
775
776 if (clk_pos && en_none)
777 opts.ffcells["$_DFF_P_"] = make_pair(IdString("\\D"), IdString("\\Q"));
778 if (clk_neg && en_none)
779 opts.ffcells["$_DFF_N_"] = make_pair(IdString("\\D"), IdString("\\Q"));
780
781 if (clk_pos && en_pos)
782 opts.ffcells["$_DFFE_PP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
783 if (clk_pos && en_neg)
784 opts.ffcells["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
785
786 if (clk_neg && en_pos)
787 opts.ffcells["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
788 if (clk_neg && en_neg)
789 opts.ffcells["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
790
791 if (en_pos || en_neg)
792 opts.ffe = true;
793 }
794 else
795 {
796 if (!clkpol.empty())
797 log_cmd_error("Options -clkpol and -match are exclusive!\n");
798 if (!enpol.empty())
799 log_cmd_error("Options -enpol and -match are exclusive!\n");
800 if (opts.params)
801 log_cmd_error("Options -params and -match are exclusive!\n");
802 }
803
804 int dff_count = 0;
805 int shreg_count = 0;
806
807 for (auto module : design->selected_modules()) {
808 ShregmapWorker worker(module, opts);
809 dff_count += worker.dff_count;
810 shreg_count += worker.shreg_count;
811 }
812
813 log("Converted %d dff cells into %d shift registers.\n", dff_count, shreg_count);
814
815 if (opts.tech != nullptr) {
816 delete opts.tech;
817 opts.tech = nullptr;
818 }
819 }
820 } ShregmapPass;
821
822 PRIVATE_NAMESPACE_END