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If d_bit already in sigbit_chain_next, create extra wire
[yosys.git] / passes / techmap / shregmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22
23 USING_YOSYS_NAMESPACE
24 PRIVATE_NAMESPACE_BEGIN
25
26 struct ShregmapTech
27 {
28 virtual ~ShregmapTech() { }
29 virtual bool analyze(vector<int> &taps) = 0;
30 virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) = 0;
31 };
32
33 struct ShregmapOptions
34 {
35 int minlen, maxlen;
36 int keep_before, keep_after;
37 bool zinit, init, params, ffe;
38 dict<IdString, pair<IdString, IdString>> ffcells;
39 ShregmapTech *tech;
40
41 ShregmapOptions()
42 {
43 minlen = 2;
44 maxlen = 0;
45 keep_before = 0;
46 keep_after = 0;
47 zinit = false;
48 init = false;
49 params = false;
50 ffe = false;
51 tech = nullptr;
52 }
53 };
54
55 struct ShregmapTechGreenpak4 : ShregmapTech
56 {
57 bool analyze(vector<int> &taps)
58 {
59 if (GetSize(taps) > 2 && taps[0] == 0 && taps[2] < 17) {
60 taps.clear();
61 return true;
62 }
63
64 if (GetSize(taps) > 2)
65 return false;
66
67 if (taps.back() > 16) return false;
68
69 return true;
70 }
71
72 bool fixup(Cell *cell, dict<int, SigBit> &taps)
73 {
74 auto D = cell->getPort(ID(D));
75 auto C = cell->getPort(ID(C));
76
77 auto newcell = cell->module->addCell(NEW_ID, ID(GP_SHREG));
78 newcell->setPort(ID(nRST), State::S1);
79 newcell->setPort(ID(CLK), C);
80 newcell->setPort(ID(IN), D);
81
82 int i = 0;
83 for (auto tap : taps) {
84 newcell->setPort(i ? ID(OUTB) : ID(OUTA), tap.second);
85 newcell->setParam(i ? ID(OUTB_TAP) : ID(OUTA_TAP), tap.first + 1);
86 i++;
87 }
88
89 cell->setParam(ID(OUTA_INVERT), 0);
90 return false;
91 }
92 };
93
94 struct ShregmapWorker
95 {
96 Module *module;
97 SigMap sigmap;
98
99 const ShregmapOptions &opts;
100 int dff_count, shreg_count;
101
102 pool<Cell*> remove_cells;
103 pool<SigBit> remove_init;
104
105 dict<SigBit, bool> sigbit_init;
106 dict<SigBit, Cell*> sigbit_chain_next;
107 dict<SigBit, Cell*> sigbit_chain_prev;
108 pool<SigBit> sigbit_with_non_chain_users;
109 pool<Cell*> chain_start_cells;
110
111 void make_sigbit_chain_next_prev()
112 {
113 for (auto wire : module->wires())
114 {
115 if (wire->port_output || wire->get_bool_attribute(ID::keep)) {
116 for (auto bit : sigmap(wire))
117 sigbit_with_non_chain_users.insert(bit);
118 }
119
120 if (wire->attributes.count(ID(init))) {
121 SigSpec initsig = sigmap(wire);
122 Const initval = wire->attributes.at(ID(init));
123 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
124 if (initval[i] == State::S0 && !opts.zinit)
125 sigbit_init[initsig[i]] = false;
126 else if (initval[i] == State::S1)
127 sigbit_init[initsig[i]] = true;
128 }
129 }
130
131 for (auto cell : module->cells())
132 {
133 if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute(ID::keep))
134 {
135 IdString d_port = opts.ffcells.at(cell->type).first;
136 IdString q_port = opts.ffcells.at(cell->type).second;
137
138 SigBit d_bit = sigmap(cell->getPort(d_port).as_bit());
139 SigBit q_bit = sigmap(cell->getPort(q_port).as_bit());
140
141 if (opts.init || sigbit_init.count(q_bit) == 0)
142 {
143 auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell));
144 if (!r.second) {
145 sigbit_with_non_chain_users.insert(d_bit);
146 Wire *wire = module->addWire(NEW_ID);
147 module->connect(wire, d_bit);
148 sigbit_chain_next.insert(std::make_pair(wire, cell));
149 }
150
151 sigbit_chain_prev[q_bit] = cell;
152 continue;
153 }
154 }
155
156 for (auto conn : cell->connections())
157 if (cell->input(conn.first))
158 for (auto bit : sigmap(conn.second))
159 sigbit_with_non_chain_users.insert(bit);
160 }
161 }
162
163 void find_chain_start_cells()
164 {
165 for (auto it : sigbit_chain_next)
166 {
167 if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first))
168 goto start_cell;
169
170 if (sigbit_chain_prev.count(it.first) != 0)
171 {
172 Cell *c1 = sigbit_chain_prev.at(it.first);
173 Cell *c2 = it.second;
174
175 if (c1->type != c2->type)
176 goto start_cell;
177
178 if (c1->parameters != c2->parameters)
179 goto start_cell;
180
181 IdString d_port = opts.ffcells.at(c1->type).first;
182 IdString q_port = opts.ffcells.at(c1->type).second;
183
184 auto c1_conn = c1->connections();
185 auto c2_conn = c1->connections();
186
187 c1_conn.erase(d_port);
188 c1_conn.erase(q_port);
189
190 c2_conn.erase(d_port);
191 c2_conn.erase(q_port);
192
193 if (c1_conn != c2_conn)
194 goto start_cell;
195
196 continue;
197 }
198
199 start_cell:
200 chain_start_cells.insert(it.second);
201 }
202 }
203
204 vector<Cell*> create_chain(Cell *start_cell)
205 {
206 vector<Cell*> chain;
207
208 Cell *c = start_cell;
209 while (c != nullptr)
210 {
211 chain.push_back(c);
212
213 IdString q_port = opts.ffcells.at(c->type).second;
214 SigBit q_bit = sigmap(c->getPort(q_port).as_bit());
215
216 if (sigbit_chain_next.count(q_bit) == 0)
217 break;
218
219 c = sigbit_chain_next.at(q_bit);
220 if (chain_start_cells.count(c) != 0)
221 break;
222 }
223
224 return chain;
225 }
226
227 void process_chain(vector<Cell*> &chain)
228 {
229 if (GetSize(chain) < opts.keep_before + opts.minlen + opts.keep_after)
230 return;
231
232 int cursor = opts.keep_before;
233 while (cursor < GetSize(chain) - opts.keep_after)
234 {
235 int depth = GetSize(chain) - opts.keep_after - cursor;
236
237 if (opts.maxlen > 0)
238 depth = std::min(opts.maxlen, depth);
239
240 Cell *first_cell = chain[cursor];
241 IdString q_port = opts.ffcells.at(first_cell->type).second;
242 dict<int, SigBit> taps_dict;
243
244 if (opts.tech)
245 {
246 vector<SigBit> qbits;
247 vector<int> taps;
248
249 for (int i = 0; i < depth; i++)
250 {
251 Cell *cell = chain[cursor+i];
252 auto qbit = sigmap(cell->getPort(q_port));
253 qbits.push_back(qbit);
254
255 if (sigbit_with_non_chain_users.count(qbit))
256 taps.push_back(i);
257 }
258
259 while (depth > 0)
260 {
261 if (taps.empty() || taps.back() < depth-1)
262 taps.push_back(depth-1);
263
264 if (opts.tech->analyze(taps))
265 break;
266
267 taps.pop_back();
268 depth--;
269 }
270
271 depth = 0;
272 for (auto tap : taps) {
273 taps_dict[tap] = qbits.at(tap);
274 log_assert(depth < tap+1);
275 depth = tap+1;
276 }
277 }
278
279 if (depth < 2) {
280 cursor++;
281 continue;
282 }
283
284 Cell *last_cell = chain[cursor+depth-1];
285
286 log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n",
287 log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), depth);
288
289 dff_count += depth;
290 shreg_count += 1;
291
292 string shreg_cell_type_str = "$__SHREG";
293 if (opts.params) {
294 shreg_cell_type_str += "_";
295 } else {
296 if (first_cell->type[1] != '_')
297 shreg_cell_type_str += "_";
298 shreg_cell_type_str += first_cell->type.substr(1);
299 }
300
301 if (opts.init) {
302 vector<State> initval;
303 for (int i = depth-1; i >= 0; i--) {
304 SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
305 if (sigbit_init.count(bit) == 0)
306 initval.push_back(State::Sx);
307 else if (sigbit_init.at(bit))
308 initval.push_back(State::S1);
309 else
310 initval.push_back(State::S0);
311 remove_init.insert(bit);
312 }
313 first_cell->setParam(ID(INIT), initval);
314 }
315
316 if (opts.zinit)
317 for (int i = depth-1; i >= 0; i--) {
318 SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
319 remove_init.insert(bit);
320 }
321
322 if (opts.params)
323 {
324 int param_clkpol = -1;
325 int param_enpol = 2;
326
327 if (first_cell->type == ID($_DFF_N_)) param_clkpol = 0;
328 if (first_cell->type == ID($_DFF_P_)) param_clkpol = 1;
329
330 if (first_cell->type == ID($_DFFE_NN_)) param_clkpol = 0, param_enpol = 0;
331 if (first_cell->type == ID($_DFFE_NP_)) param_clkpol = 0, param_enpol = 1;
332 if (first_cell->type == ID($_DFFE_PN_)) param_clkpol = 1, param_enpol = 0;
333 if (first_cell->type == ID($_DFFE_PP_)) param_clkpol = 1, param_enpol = 1;
334
335 log_assert(param_clkpol >= 0);
336 first_cell->setParam(ID(CLKPOL), param_clkpol);
337 if (opts.ffe) first_cell->setParam(ID(ENPOL), param_enpol);
338 }
339
340 first_cell->type = shreg_cell_type_str;
341 first_cell->setPort(q_port, last_cell->getPort(q_port));
342 first_cell->setParam(ID(DEPTH), depth);
343
344 if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
345 remove_cells.insert(first_cell);
346
347 for (int i = 1; i < depth; i++)
348 remove_cells.insert(chain[cursor+i]);
349 cursor += depth;
350 }
351 }
352
353 void cleanup()
354 {
355 for (auto cell : remove_cells)
356 module->remove(cell);
357
358 for (auto wire : module->wires())
359 {
360 if (wire->attributes.count(ID(init)) == 0)
361 continue;
362
363 SigSpec initsig = sigmap(wire);
364 Const &initval = wire->attributes.at(ID(init));
365
366 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
367 if (remove_init.count(initsig[i]))
368 initval[i] = State::Sx;
369
370 if (SigSpec(initval).is_fully_undef())
371 wire->attributes.erase(ID(init));
372 }
373
374 remove_cells.clear();
375 sigbit_chain_next.clear();
376 sigbit_chain_prev.clear();
377 chain_start_cells.clear();
378 }
379
380 ShregmapWorker(Module *module, const ShregmapOptions &opts) :
381 module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0)
382 {
383 make_sigbit_chain_next_prev();
384 find_chain_start_cells();
385
386 for (auto c : chain_start_cells) {
387 vector<Cell*> chain = create_chain(c);
388 process_chain(chain);
389 }
390
391 cleanup();
392 }
393 };
394
395 struct ShregmapPass : public Pass {
396 ShregmapPass() : Pass("shregmap", "map shift registers") { }
397 void help() YS_OVERRIDE
398 {
399 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
400 log("\n");
401 log(" shregmap [options] [selection]\n");
402 log("\n");
403 log("This pass converts chains of $_DFF_[NP]_ gates to target specific shift register\n");
404 log("primitives. The generated shift register will be of type $__SHREG_DFF_[NP]_ and\n");
405 log("will use the same interface as the original $_DFF_*_ cells. The cell parameter\n");
406 log("'DEPTH' will contain the depth of the shift register. Use a target-specific\n");
407 log("'techmap' map file to convert those cells to the actual target cells.\n");
408 log("\n");
409 log(" -minlen N\n");
410 log(" minimum length of shift register (default = 2)\n");
411 log(" (this is the length after -keep_before and -keep_after)\n");
412 log("\n");
413 log(" -maxlen N\n");
414 log(" maximum length of shift register (default = no limit)\n");
415 log(" larger chains will be mapped to multiple shift register instances\n");
416 log("\n");
417 log(" -keep_before N\n");
418 log(" number of DFFs to keep before the shift register (default = 0)\n");
419 log("\n");
420 log(" -keep_after N\n");
421 log(" number of DFFs to keep after the shift register (default = 0)\n");
422 log("\n");
423 log(" -clkpol pos|neg|any\n");
424 log(" limit match to only positive or negative edge clocks. (default = any)\n");
425 log("\n");
426 log(" -enpol pos|neg|none|any_or_none|any\n");
427 log(" limit match to FFs with the specified enable polarity. (default = none)\n");
428 log("\n");
429 log(" -match <cell_type>[:<d_port_name>:<q_port_name>]\n");
430 log(" match the specified cells instead of $_DFF_N_ and $_DFF_P_. If\n");
431 log(" ':<d_port_name>:<q_port_name>' is omitted then 'D' and 'Q' is used\n");
432 log(" by default. E.g. the option '-clkpol pos' is just an alias for\n");
433 log(" '-match $_DFF_P_', which is an alias for '-match $_DFF_P_:D:Q'.\n");
434 log("\n");
435 log(" -params\n");
436 log(" instead of encoding the clock and enable polarity in the cell name by\n");
437 log(" deriving from the original cell name, simply name all generated cells\n");
438 log(" $__SHREG_ and use CLKPOL and ENPOL parameters. An ENPOL value of 2 is\n");
439 log(" used to denote cells without enable input. The ENPOL parameter is\n");
440 log(" omitted when '-enpol none' (or no -enpol option) is passed.\n");
441 log("\n");
442 log(" -zinit\n");
443 log(" assume the shift register is automatically zero-initialized, so it\n");
444 log(" becomes legal to merge zero initialized FFs into the shift register.\n");
445 log("\n");
446 log(" -init\n");
447 log(" map initialized registers to the shift reg, add an INIT parameter to\n");
448 log(" generated cells with the initialization value. (first bit to shift out\n");
449 log(" in LSB position)\n");
450 log("\n");
451 log(" -tech greenpak4\n");
452 log(" map to greenpak4 shift registers.\n");
453 log("\n");
454 }
455 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
456 {
457 ShregmapOptions opts;
458 string clkpol, enpol;
459
460 log_header(design, "Executing SHREGMAP pass (map shift registers).\n");
461
462 size_t argidx;
463 for (argidx = 1; argidx < args.size(); argidx++)
464 {
465 if (args[argidx] == "-clkpol" && argidx+1 < args.size()) {
466 clkpol = args[++argidx];
467 continue;
468 }
469 if (args[argidx] == "-enpol" && argidx+1 < args.size()) {
470 enpol = args[++argidx];
471 continue;
472 }
473 if (args[argidx] == "-match" && argidx+1 < args.size()) {
474 vector<string> match_args = split_tokens(args[++argidx], ":");
475 if (GetSize(match_args) < 2)
476 match_args.push_back("D");
477 if (GetSize(match_args) < 3)
478 match_args.push_back("Q");
479 IdString id_cell_type(RTLIL::escape_id(match_args[0]));
480 IdString id_d_port_name(RTLIL::escape_id(match_args[1]));
481 IdString id_q_port_name(RTLIL::escape_id(match_args[2]));
482 opts.ffcells[id_cell_type] = make_pair(id_d_port_name, id_q_port_name);
483 continue;
484 }
485 if (args[argidx] == "-minlen" && argidx+1 < args.size()) {
486 opts.minlen = atoi(args[++argidx].c_str());
487 continue;
488 }
489 if (args[argidx] == "-maxlen" && argidx+1 < args.size()) {
490 opts.maxlen = atoi(args[++argidx].c_str());
491 continue;
492 }
493 if (args[argidx] == "-keep_before" && argidx+1 < args.size()) {
494 opts.keep_before = atoi(args[++argidx].c_str());
495 continue;
496 }
497 if (args[argidx] == "-keep_after" && argidx+1 < args.size()) {
498 opts.keep_after = atoi(args[++argidx].c_str());
499 continue;
500 }
501 if (args[argidx] == "-tech" && argidx+1 < args.size() && opts.tech == nullptr) {
502 string tech = args[++argidx];
503 if (tech == "greenpak4") {
504 clkpol = "pos";
505 opts.zinit = true;
506 opts.tech = new ShregmapTechGreenpak4;
507 } else {
508 argidx--;
509 break;
510 }
511 continue;
512 }
513 if (args[argidx] == "-zinit") {
514 opts.zinit = true;
515 continue;
516 }
517 if (args[argidx] == "-init") {
518 opts.init = true;
519 continue;
520 }
521 if (args[argidx] == "-params") {
522 opts.params = true;
523 continue;
524 }
525 break;
526 }
527 extra_args(args, argidx, design);
528
529 if (opts.zinit && opts.init)
530 log_cmd_error("Options -zinit and -init are exclusive!\n");
531
532 if (opts.ffcells.empty())
533 {
534 bool clk_pos = clkpol == "" || clkpol == "pos" || clkpol == "any";
535 bool clk_neg = clkpol == "" || clkpol == "neg" || clkpol == "any";
536
537 bool en_none = enpol == "" || enpol == "none" || enpol == "any_or_none";
538 bool en_pos = enpol == "pos" || enpol == "any" || enpol == "any_or_none";
539 bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none";
540
541 if (clk_pos && en_none)
542 opts.ffcells[ID($_DFF_P_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
543 if (clk_neg && en_none)
544 opts.ffcells[ID($_DFF_N_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
545
546 if (clk_pos && en_pos)
547 opts.ffcells[ID($_DFFE_PP_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
548 if (clk_pos && en_neg)
549 opts.ffcells[ID($_DFFE_PN_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
550
551 if (clk_neg && en_pos)
552 opts.ffcells[ID($_DFFE_NP_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
553 if (clk_neg && en_neg)
554 opts.ffcells[ID($_DFFE_NN_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
555
556 if (en_pos || en_neg)
557 opts.ffe = true;
558 }
559 else
560 {
561 if (!clkpol.empty())
562 log_cmd_error("Options -clkpol and -match are exclusive!\n");
563 if (!enpol.empty())
564 log_cmd_error("Options -enpol and -match are exclusive!\n");
565 if (opts.params)
566 log_cmd_error("Options -params and -match are exclusive!\n");
567 }
568
569 int dff_count = 0;
570 int shreg_count = 0;
571
572 for (auto module : design->selected_modules()) {
573 ShregmapWorker worker(module, opts);
574 dff_count += worker.dff_count;
575 shreg_count += worker.shreg_count;
576 }
577
578 log("Converted %d dff cells into %d shift registers.\n", dff_count, shreg_count);
579
580 if (opts.tech != nullptr) {
581 delete opts.tech;
582 opts.tech = nullptr;
583 }
584 }
585 } ShregmapPass;
586
587 PRIVATE_NAMESPACE_END