passes/techmap/simplemap.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "simplemap.h"
  21 #include "kernel/sigtools.h"
  22 #include <stdlib.h>
  23 #include <stdio.h>
  24 #include <string.h>
  25
  26 USING_YOSYS_NAMESPACE
  27 YOSYS_NAMESPACE_BEGIN
  28
  29 void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
  30 {
  31         RTLIL::SigSpec sig_a = cell->getPort("\\A");
  32         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
  33
  34         sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
  35
  36         for (int i = 0; i < GetSize(sig_y); i++) {
  37                 RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
  38                 gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
  39                 gate->setPort("\\A", sig_a[i]);
  40                 gate->setPort("\\Y", sig_y[i]);
  41         }
  42 }
  43
  44 void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
  45 {
  46         RTLIL::SigSpec sig_a = cell->getPort("\\A");
  47         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
  48
  49         sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
  50
  51         module->connect(RTLIL::SigSig(sig_y, sig_a));
  52 }
  53
  54 void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
  55 {
  56         RTLIL::SigSpec sig_a = cell->getPort("\\A");
  57         RTLIL::SigSpec sig_b = cell->getPort("\\B");
  58         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
  59
  60         sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
  61         sig_b.extend_u0(GetSize(sig_y), cell->parameters.at("\\B_SIGNED").as_bool());
  62
  63         if (cell->type == "$xnor")
  64         {
  65                 RTLIL::SigSpec sig_t = module->addWire(NEW_ID, GetSize(sig_y));
  66
  67                 for (int i = 0; i < GetSize(sig_y); i++) {
  68                         RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
  69                         gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
  70                         gate->setPort("\\A", sig_t[i]);
  71                         gate->setPort("\\Y", sig_y[i]);
  72                 }
  73
  74                 sig_y = sig_t;
  75         }
  76
  77         std::string gate_type;
  78         if (cell->type == "$and")  gate_type = "$_AND_";
  79         if (cell->type == "$or")   gate_type = "$_OR_";
  80         if (cell->type == "$xor")  gate_type = "$_XOR_";
  81         if (cell->type == "$xnor") gate_type = "$_XOR_";
  82         log_assert(!gate_type.empty());
  83
  84         for (int i = 0; i < GetSize(sig_y); i++) {
  85                 RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
  86                 gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
  87                 gate->setPort("\\A", sig_a[i]);
  88                 gate->setPort("\\B", sig_b[i]);
  89                 gate->setPort("\\Y", sig_y[i]);
  90         }
  91 }
  92
  93 void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
  94 {
  95         RTLIL::SigSpec sig_a = cell->getPort("\\A");
  96         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
  97
  98         if (sig_y.size() == 0)
  99                 return;
 100
 101         if (sig_a.size() == 0) {
 102                 if (cell->type == "$reduce_and")  module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
 103                 if (cell->type == "$reduce_or")   module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
 104                 if (cell->type == "$reduce_xor")  module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
 105                 if (cell->type == "$reduce_xnor") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
 106                 if (cell->type == "$reduce_bool") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
 107                 return;
 108         }
 109
 110         if (sig_y.size() > 1) {
 111                 module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
 112                 sig_y = sig_y.extract(0, 1);
 113         }
 114
 115         std::string gate_type;
 116         if (cell->type == "$reduce_and")  gate_type = "$_AND_";
 117         if (cell->type == "$reduce_or")   gate_type = "$_OR_";
 118         if (cell->type == "$reduce_xor")  gate_type = "$_XOR_";
 119         if (cell->type == "$reduce_xnor") gate_type = "$_XOR_";
 120         if (cell->type == "$reduce_bool") gate_type = "$_OR_";
 121         log_assert(!gate_type.empty());
 122
 123         RTLIL::Cell *last_output_cell = NULL;
 124
 125         while (sig_a.size() > 1)
 126         {
 127                 RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2);
 128
 129                 for (int i = 0; i < sig_a.size(); i += 2)
 130                 {
 131                         if (i+1 == sig_a.size()) {
 132                                 sig_t.append(sig_a[i]);
 133                                 continue;
 134                         }
 135
 136                         RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 137                         gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
 138                         gate->setPort("\\A", sig_a[i]);
 139                         gate->setPort("\\B", sig_a[i+1]);
 140                         gate->setPort("\\Y", sig_t[i/2]);
 141                         last_output_cell = gate;
 142                 }
 143
 144                 sig_a = sig_t;
 145         }
 146
 147         if (cell->type == "$reduce_xnor") {
 148                 RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
 149                 RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
 150                 gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
 151                 gate->setPort("\\A", sig_a);
 152                 gate->setPort("\\Y", sig_t);
 153                 last_output_cell = gate;
 154                 sig_a = sig_t;
 155         }
 156
 157         if (last_output_cell == NULL) {
 158                 module->connect(RTLIL::SigSig(sig_y, sig_a));
 159         } else {
 160                 last_output_cell->setPort("\\Y", sig_y);
 161         }
 162 }
 163
 164 static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell *cell)
 165 {
 166         while (sig.size() > 1)
 167         {
 168                 RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2);
 169
 170                 for (int i = 0; i < sig.size(); i += 2)
 171                 {
 172                         if (i+1 == sig.size()) {
 173                                 sig_t.append(sig[i]);
 174                                 continue;
 175                         }
 176
 177                         RTLIL::Cell *gate = module->addCell(NEW_ID, "$_OR_");
 178                         gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
 179                         gate->setPort("\\A", sig[i]);
 180                         gate->setPort("\\B", sig[i+1]);
 181                         gate->setPort("\\Y", sig_t[i/2]);
 182                 }
 183
 184                 sig = sig_t;
 185         }
 186
 187         if (sig.size() == 0)
 188                 sig = RTLIL::SigSpec(0, 1);
 189 }
 190
 191 void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
 192 {
 193         RTLIL::SigSpec sig_a = cell->getPort("\\A");
 194         logic_reduce(module, sig_a, cell);
 195
 196         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 197
 198         if (sig_y.size() == 0)
 199                 return;
 200
 201         if (sig_y.size() > 1) {
 202                 module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
 203                 sig_y = sig_y.extract(0, 1);
 204         }
 205
 206         RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
 207         gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
 208         gate->setPort("\\A", sig_a);
 209         gate->setPort("\\Y", sig_y);
 210 }
 211
 212 void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
 213 {
 214         RTLIL::SigSpec sig_a = cell->getPort("\\A");
 215         logic_reduce(module, sig_a, cell);
 216
 217         RTLIL::SigSpec sig_b = cell->getPort("\\B");
 218         logic_reduce(module, sig_b, cell);
 219
 220         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 221
 222         if (sig_y.size() == 0)
 223                 return;
 224
 225         if (sig_y.size() > 1) {
 226                 module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
 227                 sig_y = sig_y.extract(0, 1);
 228         }
 229
 230         std::string gate_type;
 231         if (cell->type == "$logic_and") gate_type = "$_AND_";
 232         if (cell->type == "$logic_or")  gate_type = "$_OR_";
 233         log_assert(!gate_type.empty());
 234
 235         RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 236         gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
 237         gate->setPort("\\A", sig_a);
 238         gate->setPort("\\B", sig_b);
 239         gate->setPort("\\Y", sig_y);
 240 }
 241
 242 void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
 243 {
 244         RTLIL::SigSpec sig_a = cell->getPort("\\A");
 245         RTLIL::SigSpec sig_b = cell->getPort("\\B");
 246         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 247         bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool();
 248         bool is_ne = cell->type == "$ne" || cell->type == "$nex";
 249
 250         RTLIL::SigSpec xor_out = module->addWire(NEW_ID, std::max(GetSize(sig_a), GetSize(sig_b)));
 251         RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
 252         xor_cell->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
 253         simplemap_bitop(module, xor_cell);
 254         module->remove(xor_cell);
 255
 256         RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID);
 257         RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out);
 258         reduce_cell->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
 259         simplemap_reduce(module, reduce_cell);
 260         module->remove(reduce_cell);
 261
 262         if (!is_ne) {
 263                 RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y);
 264                 not_cell->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
 265                 simplemap_lognot(module, not_cell);
 266                 module->remove(not_cell);
 267         }
 268 }
 269
 270 void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
 271 {
 272         RTLIL::SigSpec sig_a = cell->getPort("\\A");
 273         RTLIL::SigSpec sig_b = cell->getPort("\\B");
 274         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 275
 276         for (int i = 0; i < GetSize(sig_y); i++) {
 277                 RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_");
 278                 gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
 279                 gate->setPort("\\A", sig_a[i]);
 280                 gate->setPort("\\B", sig_b[i]);
 281                 gate->setPort("\\S", cell->getPort("\\S"));
 282                 gate->setPort("\\Y", sig_y[i]);
 283         }
 284 }
 285
 286 void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
 287 {
 288         int offset = cell->parameters.at("\\OFFSET").as_int();
 289         RTLIL::SigSpec sig_a = cell->getPort("\\A");
 290         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 291         module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size())));
 292 }
 293
 294 void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
 295 {
 296         RTLIL::SigSpec sig_ab = cell->getPort("\\A");
 297         sig_ab.append(cell->getPort("\\B"));
 298         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 299         module->connect(RTLIL::SigSig(sig_y, sig_ab));
 300 }
 301
 302 void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
 303 {
 304         int width = cell->parameters.at("\\WIDTH").as_int();
 305         char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
 306         char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
 307
 308         RTLIL::SigSpec sig_s = cell->getPort("\\SET");
 309         RTLIL::SigSpec sig_r = cell->getPort("\\CLR");
 310         RTLIL::SigSpec sig_q = cell->getPort("\\Q");
 311
 312         std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol);
 313
 314         for (int i = 0; i < width; i++) {
 315                 RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 316                 gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
 317                 gate->setPort("\\S", sig_s[i]);
 318                 gate->setPort("\\R", sig_r[i]);
 319                 gate->setPort("\\Q", sig_q[i]);
 320         }
 321 }
 322
 323 void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
 324 {
 325         int width = cell->parameters.at("\\WIDTH").as_int();
 326         char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
 327
 328         RTLIL::SigSpec sig_clk = cell->getPort("\\CLK");
 329         RTLIL::SigSpec sig_d = cell->getPort("\\D");
 330         RTLIL::SigSpec sig_q = cell->getPort("\\Q");
 331
 332         std::string gate_type = stringf("$_DFF_%c_", clk_pol);
 333
 334         for (int i = 0; i < width; i++) {
 335                 RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 336                 gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
 337                 gate->setPort("\\C", sig_clk);
 338                 gate->setPort("\\D", sig_d[i]);
 339                 gate->setPort("\\Q", sig_q[i]);
 340         }
 341 }
 342
 343 void simplemap_dffe(RTLIL::Module *module, RTLIL::Cell *cell)
 344 {
 345         int width = cell->parameters.at("\\WIDTH").as_int();
 346         char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
 347         char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N';
 348
 349         RTLIL::SigSpec sig_clk = cell->getPort("\\CLK");
 350         RTLIL::SigSpec sig_en = cell->getPort("\\EN");
 351         RTLIL::SigSpec sig_d = cell->getPort("\\D");
 352         RTLIL::SigSpec sig_q = cell->getPort("\\Q");
 353
 354         std::string gate_type = stringf("$_DFFE_%c%c_", clk_pol, en_pol);
 355
 356         for (int i = 0; i < width; i++) {
 357                 RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 358                 gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
 359                 gate->setPort("\\C", sig_clk);
 360                 gate->setPort("\\E", sig_en);
 361                 gate->setPort("\\D", sig_d[i]);
 362                 gate->setPort("\\Q", sig_q[i]);
 363         }
 364 }
 365
 366 void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
 367 {
 368         int width = cell->parameters.at("\\WIDTH").as_int();
 369         char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
 370         char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
 371         char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
 372
 373         RTLIL::SigSpec sig_clk = cell->getPort("\\CLK");
 374         RTLIL::SigSpec sig_s = cell->getPort("\\SET");
 375         RTLIL::SigSpec sig_r = cell->getPort("\\CLR");
 376         RTLIL::SigSpec sig_d = cell->getPort("\\D");
 377         RTLIL::SigSpec sig_q = cell->getPort("\\Q");
 378
 379         std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol);
 380
 381         for (int i = 0; i < width; i++) {
 382                 RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 383                 gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
 384                 gate->setPort("\\C", sig_clk);
 385                 gate->setPort("\\S", sig_s[i]);
 386                 gate->setPort("\\R", sig_r[i]);
 387                 gate->setPort("\\D", sig_d[i]);
 388                 gate->setPort("\\Q", sig_q[i]);
 389         }
 390 }
 391
 392 void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
 393 {
 394         int width = cell->parameters.at("\\WIDTH").as_int();
 395         char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
 396         char rst_pol = cell->parameters.at("\\ARST_POLARITY").as_bool() ? 'P' : 'N';
 397
 398         std::vector<RTLIL::State> rst_val = cell->parameters.at("\\ARST_VALUE").bits;
 399         while (int(rst_val.size()) < width)
 400                 rst_val.push_back(RTLIL::State::S0);
 401
 402         RTLIL::SigSpec sig_clk = cell->getPort("\\CLK");
 403         RTLIL::SigSpec sig_rst = cell->getPort("\\ARST");
 404         RTLIL::SigSpec sig_d = cell->getPort("\\D");
 405         RTLIL::SigSpec sig_q = cell->getPort("\\Q");
 406
 407         std::string gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol);
 408         std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
 409
 410         for (int i = 0; i < width; i++) {
 411                 RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
 412                 gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
 413                 gate->setPort("\\C", sig_clk);
 414                 gate->setPort("\\R", sig_rst);
 415                 gate->setPort("\\D", sig_d[i]);
 416                 gate->setPort("\\Q", sig_q[i]);
 417         }
 418 }
 419
 420 void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
 421 {
 422         int width = cell->parameters.at("\\WIDTH").as_int();
 423         char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N';
 424
 425         RTLIL::SigSpec sig_en = cell->getPort("\\EN");
 426         RTLIL::SigSpec sig_d = cell->getPort("\\D");
 427         RTLIL::SigSpec sig_q = cell->getPort("\\Q");
 428
 429         std::string gate_type = stringf("$_DLATCH_%c_", en_pol);
 430
 431         for (int i = 0; i < width; i++) {
 432                 RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 433                 gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
 434                 gate->setPort("\\E", sig_en);
 435                 gate->setPort("\\D", sig_d[i]);
 436                 gate->setPort("\\Q", sig_q[i]);
 437         }
 438 }
 439
 440 void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
 441 {
 442         mappers["$not"]         = simplemap_not;
 443         mappers["$pos"]         = simplemap_pos;
 444         mappers["$and"]         = simplemap_bitop;
 445         mappers["$or"]          = simplemap_bitop;
 446         mappers["$xor"]         = simplemap_bitop;
 447         mappers["$xnor"]        = simplemap_bitop;
 448         mappers["$reduce_and"]  = simplemap_reduce;
 449         mappers["$reduce_or"]   = simplemap_reduce;
 450         mappers["$reduce_xor"]  = simplemap_reduce;
 451         mappers["$reduce_xnor"] = simplemap_reduce;
 452         mappers["$reduce_bool"] = simplemap_reduce;
 453         mappers["$logic_not"]   = simplemap_lognot;
 454         mappers["$logic_and"]   = simplemap_logbin;
 455         mappers["$logic_or"]    = simplemap_logbin;
 456         mappers["$eq"]          = simplemap_eqne;
 457         mappers["$eqx"]         = simplemap_eqne;
 458         mappers["$ne"]          = simplemap_eqne;
 459         mappers["$nex"]         = simplemap_eqne;
 460         mappers["$mux"]         = simplemap_mux;
 461         mappers["$slice"]       = simplemap_slice;
 462         mappers["$concat"]      = simplemap_concat;
 463         mappers["$sr"]          = simplemap_sr;
 464         mappers["$dff"]         = simplemap_dff;
 465         mappers["$dffe"]        = simplemap_dffe;
 466         mappers["$dffsr"]       = simplemap_dffsr;
 467         mappers["$adff"]        = simplemap_adff;
 468         mappers["$dlatch"]      = simplemap_dlatch;
 469 }
 470
 471 void simplemap(RTLIL::Module *module, RTLIL::Cell *cell)
 472 {
 473         static std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
 474         static bool initialized_mappers = false;
 475
 476         if (!initialized_mappers) {
 477                 simplemap_get_mappers(mappers);
 478                 initialized_mappers = true;
 479         }
 480
 481         mappers.at(cell->type)(module, cell);
 482 }
 483
 484 YOSYS_NAMESPACE_END
 485 PRIVATE_NAMESPACE_BEGIN
 486
 487 struct SimplemapPass : public Pass {
 488         SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") { }
 489         virtual void help()
 490         {
 491                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 492                 log("\n");
 493                 log("    simplemap [selection]\n");
 494                 log("\n");
 495                 log("This pass maps a small selection of simple coarse-grain cells to yosys gate\n");
 496                 log("primitives. The following internal cell types are mapped by this pass:\n");
 497                 log("\n");
 498                 log("  $not, $pos, $and, $or, $xor, $xnor\n");
 499                 log("  $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
 500                 log("  $logic_not, $logic_and, $logic_or, $mux\n");
 501                 log("  $sr, $dff, $dffsr, $adff, $dlatch\n");
 502                 log("\n");
 503         }
 504         virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 505         {
 506                 log_header("Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
 507                 extra_args(args, 1, design);
 508
 509                 std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
 510                 simplemap_get_mappers(mappers);
 511
 512                 for (auto mod : design->modules()) {
 513                         if (!design->selected(mod))
 514                                 continue;
 515                         std::vector<RTLIL::Cell*> cells = mod->cells();
 516                         for (auto cell : cells) {
 517                                 if (mappers.count(cell->type) == 0)
 518                                         continue;
 519                                 if (!design->selected(mod, cell))
 520                                         continue;
 521                                 log("Mapping %s.%s (%s).\n", log_id(mod), log_id(cell), log_id(cell->type));
 522                                 mappers.at(cell->type)(mod, cell);
 523                                 mod->remove(cell);
 524                         }
 525                 }
 526         }
 527 } SimplemapPass;
 528
 529 PRIVATE_NAMESPACE_END