passes/techmap/simplemap.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "simplemap.h"
  21 #include "kernel/sigtools.h"
  22 #include <stdlib.h>
  23 #include <stdio.h>
  24 #include <string.h>
  25
  26 USING_YOSYS_NAMESPACE
  27 YOSYS_NAMESPACE_BEGIN
  28
  29 void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
  30 {
  31         RTLIL::SigSpec sig_a = cell->getPort("\\A");
  32         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
  33
  34         sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
  35
  36         for (int i = 0; i < GetSize(sig_y); i++) {
  37                 RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
  38                 gate->setPort("\\A", sig_a[i]);
  39                 gate->setPort("\\Y", sig_y[i]);
  40         }
  41 }
  42
  43 void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
  44 {
  45         RTLIL::SigSpec sig_a = cell->getPort("\\A");
  46         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
  47
  48         sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
  49
  50         module->connect(RTLIL::SigSig(sig_y, sig_a));
  51 }
  52
  53 void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
  54 {
  55         RTLIL::SigSpec sig_a = cell->getPort("\\A");
  56         RTLIL::SigSpec sig_b = cell->getPort("\\B");
  57         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
  58
  59         sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
  60         sig_b.extend_u0(GetSize(sig_y), cell->parameters.at("\\B_SIGNED").as_bool());
  61
  62         if (cell->type == "$xnor")
  63         {
  64                 RTLIL::SigSpec sig_t = module->addWire(NEW_ID, GetSize(sig_y));
  65
  66                 for (int i = 0; i < GetSize(sig_y); i++) {
  67                         RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
  68                         gate->setPort("\\A", sig_t[i]);
  69                         gate->setPort("\\Y", sig_y[i]);
  70                 }
  71
  72                 sig_y = sig_t;
  73         }
  74
  75         std::string gate_type;
  76         if (cell->type == "$and")  gate_type = "$_AND_";
  77         if (cell->type == "$or")   gate_type = "$_OR_";
  78         if (cell->type == "$xor")  gate_type = "$_XOR_";
  79         if (cell->type == "$xnor") gate_type = "$_XOR_";
  80         log_assert(!gate_type.empty());
  81
  82         for (int i = 0; i < GetSize(sig_y); i++) {
  83                 RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
  84                 gate->setPort("\\A", sig_a[i]);
  85                 gate->setPort("\\B", sig_b[i]);
  86                 gate->setPort("\\Y", sig_y[i]);
  87         }
  88 }
  89
  90 void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
  91 {
  92         RTLIL::SigSpec sig_a = cell->getPort("\\A");
  93         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
  94
  95         if (sig_y.size() == 0)
  96                 return;
  97
  98         if (sig_a.size() == 0) {
  99                 if (cell->type == "$reduce_and")  module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
 100                 if (cell->type == "$reduce_or")   module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
 101                 if (cell->type == "$reduce_xor")  module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
 102                 if (cell->type == "$reduce_xnor") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
 103                 if (cell->type == "$reduce_bool") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
 104                 return;
 105         }
 106
 107         if (sig_y.size() > 1) {
 108                 module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
 109                 sig_y = sig_y.extract(0, 1);
 110         }
 111
 112         std::string gate_type;
 113         if (cell->type == "$reduce_and")  gate_type = "$_AND_";
 114         if (cell->type == "$reduce_or")   gate_type = "$_OR_";
 115         if (cell->type == "$reduce_xor")  gate_type = "$_XOR_";
 116         if (cell->type == "$reduce_xnor") gate_type = "$_XOR_";
 117         if (cell->type == "$reduce_bool") gate_type = "$_OR_";
 118         log_assert(!gate_type.empty());
 119
 120         RTLIL::Cell *last_output_cell = NULL;
 121
 122         while (sig_a.size() > 1)
 123         {
 124                 RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2);
 125
 126                 for (int i = 0; i < sig_a.size(); i += 2)
 127                 {
 128                         if (i+1 == sig_a.size()) {
 129                                 sig_t.append(sig_a[i]);
 130                                 continue;
 131                         }
 132
 133                         RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 134                         gate->setPort("\\A", sig_a[i]);
 135                         gate->setPort("\\B", sig_a[i+1]);
 136                         gate->setPort("\\Y", sig_t[i/2]);
 137                         last_output_cell = gate;
 138                 }
 139
 140                 sig_a = sig_t;
 141         }
 142
 143         if (cell->type == "$reduce_xnor") {
 144                 RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
 145                 RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
 146                 gate->setPort("\\A", sig_a);
 147                 gate->setPort("\\Y", sig_t);
 148                 last_output_cell = gate;
 149                 sig_a = sig_t;
 150         }
 151
 152         if (last_output_cell == NULL) {
 153                 module->connect(RTLIL::SigSig(sig_y, sig_a));
 154         } else {
 155                 last_output_cell->setPort("\\Y", sig_y);
 156         }
 157 }
 158
 159 static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig)
 160 {
 161         while (sig.size() > 1)
 162         {
 163                 RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2);
 164
 165                 for (int i = 0; i < sig.size(); i += 2)
 166                 {
 167                         if (i+1 == sig.size()) {
 168                                 sig_t.append(sig[i]);
 169                                 continue;
 170                         }
 171
 172                         RTLIL::Cell *gate = module->addCell(NEW_ID, "$_OR_");
 173                         gate->setPort("\\A", sig[i]);
 174                         gate->setPort("\\B", sig[i+1]);
 175                         gate->setPort("\\Y", sig_t[i/2]);
 176                 }
 177
 178                 sig = sig_t;
 179         }
 180
 181         if (sig.size() == 0)
 182                 sig = RTLIL::SigSpec(0, 1);
 183 }
 184
 185 void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
 186 {
 187         RTLIL::SigSpec sig_a = cell->getPort("\\A");
 188         logic_reduce(module, sig_a);
 189
 190         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 191
 192         if (sig_y.size() == 0)
 193                 return;
 194
 195         if (sig_y.size() > 1) {
 196                 module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
 197                 sig_y = sig_y.extract(0, 1);
 198         }
 199
 200         RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
 201         gate->setPort("\\A", sig_a);
 202         gate->setPort("\\Y", sig_y);
 203 }
 204
 205 void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
 206 {
 207         RTLIL::SigSpec sig_a = cell->getPort("\\A");
 208         logic_reduce(module, sig_a);
 209
 210         RTLIL::SigSpec sig_b = cell->getPort("\\B");
 211         logic_reduce(module, sig_b);
 212
 213         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 214
 215         if (sig_y.size() == 0)
 216                 return;
 217
 218         if (sig_y.size() > 1) {
 219                 module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
 220                 sig_y = sig_y.extract(0, 1);
 221         }
 222
 223         std::string gate_type;
 224         if (cell->type == "$logic_and") gate_type = "$_AND_";
 225         if (cell->type == "$logic_or")  gate_type = "$_OR_";
 226         log_assert(!gate_type.empty());
 227
 228         RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 229         gate->setPort("\\A", sig_a);
 230         gate->setPort("\\B", sig_b);
 231         gate->setPort("\\Y", sig_y);
 232 }
 233
 234 void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
 235 {
 236         RTLIL::SigSpec sig_a = cell->getPort("\\A");
 237         RTLIL::SigSpec sig_b = cell->getPort("\\B");
 238         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 239         bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool();
 240         bool is_ne = cell->type == "$ne" || cell->type == "$nex";
 241
 242         RTLIL::SigSpec xor_out = module->addWire(NEW_ID, std::max(GetSize(sig_a), GetSize(sig_b)));
 243         RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
 244
 245         RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID);
 246         RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out);
 247
 248         if (!is_ne)
 249                 module->addNotGate(NEW_ID, reduce_out, sig_y);
 250
 251         simplemap_bitop(module, xor_cell);
 252         module->remove(xor_cell);
 253
 254         simplemap_reduce(module, reduce_cell);
 255         module->remove(reduce_cell);
 256 }
 257
 258 void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
 259 {
 260         RTLIL::SigSpec sig_a = cell->getPort("\\A");
 261         RTLIL::SigSpec sig_b = cell->getPort("\\B");
 262         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 263
 264         for (int i = 0; i < GetSize(sig_y); i++) {
 265                 RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_");
 266                 gate->setPort("\\A", sig_a[i]);
 267                 gate->setPort("\\B", sig_b[i]);
 268                 gate->setPort("\\S", cell->getPort("\\S"));
 269                 gate->setPort("\\Y", sig_y[i]);
 270         }
 271 }
 272
 273 void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
 274 {
 275         int offset = cell->parameters.at("\\OFFSET").as_int();
 276         RTLIL::SigSpec sig_a = cell->getPort("\\A");
 277         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 278         module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size())));
 279 }
 280
 281 void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
 282 {
 283         RTLIL::SigSpec sig_ab = cell->getPort("\\A");
 284         sig_ab.append(cell->getPort("\\B"));
 285         RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 286         module->connect(RTLIL::SigSig(sig_y, sig_ab));
 287 }
 288
 289 void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
 290 {
 291         int width = cell->parameters.at("\\WIDTH").as_int();
 292         char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
 293         char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
 294
 295         RTLIL::SigSpec sig_s = cell->getPort("\\SET");
 296         RTLIL::SigSpec sig_r = cell->getPort("\\CLR");
 297         RTLIL::SigSpec sig_q = cell->getPort("\\Q");
 298
 299         std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol);
 300
 301         for (int i = 0; i < width; i++) {
 302                 RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 303                 gate->setPort("\\S", sig_s[i]);
 304                 gate->setPort("\\R", sig_r[i]);
 305                 gate->setPort("\\Q", sig_q[i]);
 306         }
 307 }
 308
 309 void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
 310 {
 311         int width = cell->parameters.at("\\WIDTH").as_int();
 312         char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
 313
 314         RTLIL::SigSpec sig_clk = cell->getPort("\\CLK");
 315         RTLIL::SigSpec sig_d = cell->getPort("\\D");
 316         RTLIL::SigSpec sig_q = cell->getPort("\\Q");
 317
 318         std::string gate_type = stringf("$_DFF_%c_", clk_pol);
 319
 320         for (int i = 0; i < width; i++) {
 321                 RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 322                 gate->setPort("\\C", sig_clk);
 323                 gate->setPort("\\D", sig_d[i]);
 324                 gate->setPort("\\Q", sig_q[i]);
 325         }
 326 }
 327
 328 void simplemap_dffe(RTLIL::Module *module, RTLIL::Cell *cell)
 329 {
 330         int width = cell->parameters.at("\\WIDTH").as_int();
 331         char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
 332         char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N';
 333
 334         RTLIL::SigSpec sig_clk = cell->getPort("\\CLK");
 335         RTLIL::SigSpec sig_en = cell->getPort("\\EN");
 336         RTLIL::SigSpec sig_d = cell->getPort("\\D");
 337         RTLIL::SigSpec sig_q = cell->getPort("\\Q");
 338
 339         std::string gate_type = stringf("$_DFFE_%c%c_", clk_pol, en_pol);
 340
 341         for (int i = 0; i < width; i++) {
 342                 RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 343                 gate->setPort("\\C", sig_clk);
 344                 gate->setPort("\\E", sig_en);
 345                 gate->setPort("\\D", sig_d[i]);
 346                 gate->setPort("\\Q", sig_q[i]);
 347         }
 348 }
 349
 350 void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
 351 {
 352         int width = cell->parameters.at("\\WIDTH").as_int();
 353         char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
 354         char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
 355         char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
 356
 357         RTLIL::SigSpec sig_clk = cell->getPort("\\CLK");
 358         RTLIL::SigSpec sig_s = cell->getPort("\\SET");
 359         RTLIL::SigSpec sig_r = cell->getPort("\\CLR");
 360         RTLIL::SigSpec sig_d = cell->getPort("\\D");
 361         RTLIL::SigSpec sig_q = cell->getPort("\\Q");
 362
 363         std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol);
 364
 365         for (int i = 0; i < width; i++) {
 366                 RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 367                 gate->setPort("\\C", sig_clk);
 368                 gate->setPort("\\S", sig_s[i]);
 369                 gate->setPort("\\R", sig_r[i]);
 370                 gate->setPort("\\D", sig_d[i]);
 371                 gate->setPort("\\Q", sig_q[i]);
 372         }
 373 }
 374
 375 void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
 376 {
 377         int width = cell->parameters.at("\\WIDTH").as_int();
 378         char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
 379         char rst_pol = cell->parameters.at("\\ARST_POLARITY").as_bool() ? 'P' : 'N';
 380
 381         std::vector<RTLIL::State> rst_val = cell->parameters.at("\\ARST_VALUE").bits;
 382         while (int(rst_val.size()) < width)
 383                 rst_val.push_back(RTLIL::State::S0);
 384
 385         RTLIL::SigSpec sig_clk = cell->getPort("\\CLK");
 386         RTLIL::SigSpec sig_rst = cell->getPort("\\ARST");
 387         RTLIL::SigSpec sig_d = cell->getPort("\\D");
 388         RTLIL::SigSpec sig_q = cell->getPort("\\Q");
 389
 390         std::string gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol);
 391         std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
 392
 393         for (int i = 0; i < width; i++) {
 394                 RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
 395                 gate->setPort("\\C", sig_clk);
 396                 gate->setPort("\\R", sig_rst);
 397                 gate->setPort("\\D", sig_d[i]);
 398                 gate->setPort("\\Q", sig_q[i]);
 399         }
 400 }
 401
 402 void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
 403 {
 404         int width = cell->parameters.at("\\WIDTH").as_int();
 405         char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N';
 406
 407         RTLIL::SigSpec sig_en = cell->getPort("\\EN");
 408         RTLIL::SigSpec sig_d = cell->getPort("\\D");
 409         RTLIL::SigSpec sig_q = cell->getPort("\\Q");
 410
 411         std::string gate_type = stringf("$_DLATCH_%c_", en_pol);
 412
 413         for (int i = 0; i < width; i++) {
 414                 RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
 415                 gate->setPort("\\E", sig_en);
 416                 gate->setPort("\\D", sig_d[i]);
 417                 gate->setPort("\\Q", sig_q[i]);
 418         }
 419 }
 420
 421 void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
 422 {
 423         mappers["$not"]         = simplemap_not;
 424         mappers["$pos"]         = simplemap_pos;
 425         mappers["$and"]         = simplemap_bitop;
 426         mappers["$or"]          = simplemap_bitop;
 427         mappers["$xor"]         = simplemap_bitop;
 428         mappers["$xnor"]        = simplemap_bitop;
 429         mappers["$reduce_and"]  = simplemap_reduce;
 430         mappers["$reduce_or"]   = simplemap_reduce;
 431         mappers["$reduce_xor"]  = simplemap_reduce;
 432         mappers["$reduce_xnor"] = simplemap_reduce;
 433         mappers["$reduce_bool"] = simplemap_reduce;
 434         mappers["$logic_not"]   = simplemap_lognot;
 435         mappers["$logic_and"]   = simplemap_logbin;
 436         mappers["$logic_or"]    = simplemap_logbin;
 437         mappers["$eq"]          = simplemap_eqne;
 438         mappers["$eqx"]         = simplemap_eqne;
 439         mappers["$ne"]          = simplemap_eqne;
 440         mappers["$nex"]         = simplemap_eqne;
 441         mappers["$mux"]         = simplemap_mux;
 442         mappers["$slice"]       = simplemap_slice;
 443         mappers["$concat"]      = simplemap_concat;
 444         mappers["$sr"]          = simplemap_sr;
 445         mappers["$dff"]         = simplemap_dff;
 446         mappers["$dffe"]        = simplemap_dffe;
 447         mappers["$dffsr"]       = simplemap_dffsr;
 448         mappers["$adff"]        = simplemap_adff;
 449         mappers["$dlatch"]      = simplemap_dlatch;
 450 }
 451
 452 void simplemap(RTLIL::Module *module, RTLIL::Cell *cell)
 453 {
 454         static std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
 455         static bool initialized_mappers = false;
 456
 457         if (!initialized_mappers) {
 458                 simplemap_get_mappers(mappers);
 459                 initialized_mappers = true;
 460         }
 461
 462         mappers.at(cell->type)(module, cell);
 463 }
 464
 465 YOSYS_NAMESPACE_END
 466 PRIVATE_NAMESPACE_BEGIN
 467
 468 struct SimplemapPass : public Pass {
 469         SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") { }
 470         virtual void help()
 471         {
 472                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 473                 log("\n");
 474                 log("    simplemap [selection]\n");
 475                 log("\n");
 476                 log("This pass maps a small selection of simple coarse-grain cells to yosys gate\n");
 477                 log("primitives. The following internal cell types are mapped by this pass:\n");
 478                 log("\n");
 479                 log("  $not, $pos, $and, $or, $xor, $xnor\n");
 480                 log("  $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
 481                 log("  $logic_not, $logic_and, $logic_or, $mux\n");
 482                 log("  $sr, $dff, $dffsr, $adff, $dlatch\n");
 483                 log("\n");
 484         }
 485         virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 486         {
 487                 log_header("Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
 488                 extra_args(args, 1, design);
 489
 490                 std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
 491                 simplemap_get_mappers(mappers);
 492
 493                 for (auto mod : design->modules()) {
 494                         if (!design->selected(mod))
 495                                 continue;
 496                         std::vector<RTLIL::Cell*> cells = mod->cells();
 497                         for (auto cell : cells) {
 498                                 if (mappers.count(cell->type) == 0)
 499                                         continue;
 500                                 if (!design->selected(mod, cell))
 501                                         continue;
 502                                 log("Mapping %s.%s (%s).\n", log_id(mod), log_id(cell), log_id(cell->type));
 503                                 mappers.at(cell->type)(mod, cell);
 504                                 mod->remove(cell);
 505                         }
 506                 }
 507         }
 508 } SimplemapPass;
 509
 510 PRIVATE_NAMESPACE_END