2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "simplemap.h"
21 #include "kernel/sigtools.h"
29 void simplemap_not(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
31 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
32 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
34 sig_a
.extend_u0(GetSize(sig_y
), cell
->parameters
.at("\\A_SIGNED").as_bool());
36 for (int i
= 0; i
< GetSize(sig_y
); i
++) {
37 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, "$_NOT_");
38 gate
->add_strpool_attribute("\\src", cell
->get_strpool_attribute("\\src"));
39 gate
->setPort("\\A", sig_a
[i
]);
40 gate
->setPort("\\Y", sig_y
[i
]);
44 void simplemap_pos(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
46 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
47 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
49 sig_a
.extend_u0(GetSize(sig_y
), cell
->parameters
.at("\\A_SIGNED").as_bool());
51 module
->connect(RTLIL::SigSig(sig_y
, sig_a
));
54 void simplemap_bitop(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
56 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
57 RTLIL::SigSpec sig_b
= cell
->getPort("\\B");
58 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
60 sig_a
.extend_u0(GetSize(sig_y
), cell
->parameters
.at("\\A_SIGNED").as_bool());
61 sig_b
.extend_u0(GetSize(sig_y
), cell
->parameters
.at("\\B_SIGNED").as_bool());
63 if (cell
->type
== "$xnor")
65 RTLIL::SigSpec sig_t
= module
->addWire(NEW_ID
, GetSize(sig_y
));
67 for (int i
= 0; i
< GetSize(sig_y
); i
++) {
68 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, "$_NOT_");
69 gate
->add_strpool_attribute("\\src", cell
->get_strpool_attribute("\\src"));
70 gate
->setPort("\\A", sig_t
[i
]);
71 gate
->setPort("\\Y", sig_y
[i
]);
77 std::string gate_type
;
78 if (cell
->type
== "$and") gate_type
= "$_AND_";
79 if (cell
->type
== "$or") gate_type
= "$_OR_";
80 if (cell
->type
== "$xor") gate_type
= "$_XOR_";
81 if (cell
->type
== "$xnor") gate_type
= "$_XOR_";
82 log_assert(!gate_type
.empty());
84 for (int i
= 0; i
< GetSize(sig_y
); i
++) {
85 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, gate_type
);
86 gate
->add_strpool_attribute("\\src", cell
->get_strpool_attribute("\\src"));
87 gate
->setPort("\\A", sig_a
[i
]);
88 gate
->setPort("\\B", sig_b
[i
]);
89 gate
->setPort("\\Y", sig_y
[i
]);
93 void simplemap_reduce(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
95 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
96 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
98 if (sig_y
.size() == 0)
101 if (sig_a
.size() == 0) {
102 if (cell
->type
== "$reduce_and") module
->connect(RTLIL::SigSig(sig_y
, RTLIL::SigSpec(1, sig_y
.size())));
103 if (cell
->type
== "$reduce_or") module
->connect(RTLIL::SigSig(sig_y
, RTLIL::SigSpec(0, sig_y
.size())));
104 if (cell
->type
== "$reduce_xor") module
->connect(RTLIL::SigSig(sig_y
, RTLIL::SigSpec(0, sig_y
.size())));
105 if (cell
->type
== "$reduce_xnor") module
->connect(RTLIL::SigSig(sig_y
, RTLIL::SigSpec(1, sig_y
.size())));
106 if (cell
->type
== "$reduce_bool") module
->connect(RTLIL::SigSig(sig_y
, RTLIL::SigSpec(0, sig_y
.size())));
110 if (sig_y
.size() > 1) {
111 module
->connect(RTLIL::SigSig(sig_y
.extract(1, sig_y
.size()-1), RTLIL::SigSpec(0, sig_y
.size()-1)));
112 sig_y
= sig_y
.extract(0, 1);
115 std::string gate_type
;
116 if (cell
->type
== "$reduce_and") gate_type
= "$_AND_";
117 if (cell
->type
== "$reduce_or") gate_type
= "$_OR_";
118 if (cell
->type
== "$reduce_xor") gate_type
= "$_XOR_";
119 if (cell
->type
== "$reduce_xnor") gate_type
= "$_XOR_";
120 if (cell
->type
== "$reduce_bool") gate_type
= "$_OR_";
121 log_assert(!gate_type
.empty());
123 RTLIL::Cell
*last_output_cell
= NULL
;
125 while (sig_a
.size() > 1)
127 RTLIL::SigSpec sig_t
= module
->addWire(NEW_ID
, sig_a
.size() / 2);
129 for (int i
= 0; i
< sig_a
.size(); i
+= 2)
131 if (i
+1 == sig_a
.size()) {
132 sig_t
.append(sig_a
[i
]);
136 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, gate_type
);
137 gate
->add_strpool_attribute("\\src", cell
->get_strpool_attribute("\\src"));
138 gate
->setPort("\\A", sig_a
[i
]);
139 gate
->setPort("\\B", sig_a
[i
+1]);
140 gate
->setPort("\\Y", sig_t
[i
/2]);
141 last_output_cell
= gate
;
147 if (cell
->type
== "$reduce_xnor") {
148 RTLIL::SigSpec sig_t
= module
->addWire(NEW_ID
);
149 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, "$_NOT_");
150 gate
->add_strpool_attribute("\\src", cell
->get_strpool_attribute("\\src"));
151 gate
->setPort("\\A", sig_a
);
152 gate
->setPort("\\Y", sig_t
);
153 last_output_cell
= gate
;
157 if (last_output_cell
== NULL
) {
158 module
->connect(RTLIL::SigSig(sig_y
, sig_a
));
160 last_output_cell
->setPort("\\Y", sig_y
);
164 static void logic_reduce(RTLIL::Module
*module
, RTLIL::SigSpec
&sig
, RTLIL::Cell
*cell
)
166 while (sig
.size() > 1)
168 RTLIL::SigSpec sig_t
= module
->addWire(NEW_ID
, sig
.size() / 2);
170 for (int i
= 0; i
< sig
.size(); i
+= 2)
172 if (i
+1 == sig
.size()) {
173 sig_t
.append(sig
[i
]);
177 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, "$_OR_");
178 gate
->add_strpool_attribute("\\src", cell
->get_strpool_attribute("\\src"));
179 gate
->setPort("\\A", sig
[i
]);
180 gate
->setPort("\\B", sig
[i
+1]);
181 gate
->setPort("\\Y", sig_t
[i
/2]);
188 sig
= RTLIL::SigSpec(0, 1);
191 void simplemap_lognot(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
193 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
194 logic_reduce(module
, sig_a
, cell
);
196 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
198 if (sig_y
.size() == 0)
201 if (sig_y
.size() > 1) {
202 module
->connect(RTLIL::SigSig(sig_y
.extract(1, sig_y
.size()-1), RTLIL::SigSpec(0, sig_y
.size()-1)));
203 sig_y
= sig_y
.extract(0, 1);
206 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, "$_NOT_");
207 gate
->add_strpool_attribute("\\src", cell
->get_strpool_attribute("\\src"));
208 gate
->setPort("\\A", sig_a
);
209 gate
->setPort("\\Y", sig_y
);
212 void simplemap_logbin(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
214 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
215 logic_reduce(module
, sig_a
, cell
);
217 RTLIL::SigSpec sig_b
= cell
->getPort("\\B");
218 logic_reduce(module
, sig_b
, cell
);
220 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
222 if (sig_y
.size() == 0)
225 if (sig_y
.size() > 1) {
226 module
->connect(RTLIL::SigSig(sig_y
.extract(1, sig_y
.size()-1), RTLIL::SigSpec(0, sig_y
.size()-1)));
227 sig_y
= sig_y
.extract(0, 1);
230 std::string gate_type
;
231 if (cell
->type
== "$logic_and") gate_type
= "$_AND_";
232 if (cell
->type
== "$logic_or") gate_type
= "$_OR_";
233 log_assert(!gate_type
.empty());
235 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, gate_type
);
236 gate
->add_strpool_attribute("\\src", cell
->get_strpool_attribute("\\src"));
237 gate
->setPort("\\A", sig_a
);
238 gate
->setPort("\\B", sig_b
);
239 gate
->setPort("\\Y", sig_y
);
242 void simplemap_eqne(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
244 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
245 RTLIL::SigSpec sig_b
= cell
->getPort("\\B");
246 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
247 bool is_signed
= cell
->parameters
.at("\\A_SIGNED").as_bool();
248 bool is_ne
= cell
->type
== "$ne" || cell
->type
== "$nex";
250 RTLIL::SigSpec xor_out
= module
->addWire(NEW_ID
, std::max(GetSize(sig_a
), GetSize(sig_b
)));
251 RTLIL::Cell
*xor_cell
= module
->addXor(NEW_ID
, sig_a
, sig_b
, xor_out
, is_signed
);
252 xor_cell
->add_strpool_attribute("\\src", cell
->get_strpool_attribute("\\src"));
253 simplemap_bitop(module
, xor_cell
);
254 module
->remove(xor_cell
);
256 RTLIL::SigSpec reduce_out
= is_ne
? sig_y
: module
->addWire(NEW_ID
);
257 RTLIL::Cell
*reduce_cell
= module
->addReduceOr(NEW_ID
, xor_out
, reduce_out
);
258 reduce_cell
->add_strpool_attribute("\\src", cell
->get_strpool_attribute("\\src"));
259 simplemap_reduce(module
, reduce_cell
);
260 module
->remove(reduce_cell
);
263 RTLIL::Cell
*not_cell
= module
->addLogicNot(NEW_ID
, reduce_out
, sig_y
);
264 not_cell
->add_strpool_attribute("\\src", cell
->get_strpool_attribute("\\src"));
265 simplemap_lognot(module
, not_cell
);
266 module
->remove(not_cell
);
270 void simplemap_mux(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
272 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
273 RTLIL::SigSpec sig_b
= cell
->getPort("\\B");
274 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
276 for (int i
= 0; i
< GetSize(sig_y
); i
++) {
277 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, "$_MUX_");
278 gate
->add_strpool_attribute("\\src", cell
->get_strpool_attribute("\\src"));
279 gate
->setPort("\\A", sig_a
[i
]);
280 gate
->setPort("\\B", sig_b
[i
]);
281 gate
->setPort("\\S", cell
->getPort("\\S"));
282 gate
->setPort("\\Y", sig_y
[i
]);
286 void simplemap_lut(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
288 SigSpec lut_ctrl
= cell
->getPort("\\A");
289 SigSpec lut_data
= cell
->getParam("\\LUT");
290 lut_data
.extend_u0(1 << cell
->getParam("\\WIDTH").as_int());
292 for (int idx
= 0; GetSize(lut_data
) > 1; idx
++) {
293 SigSpec sig_s
= lut_ctrl
[idx
];
294 SigSpec new_lut_data
= module
->addWire(NEW_ID
, GetSize(lut_data
)/2);
295 for (int i
= 0; i
< GetSize(lut_data
); i
+= 2) {
296 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, "$_MUX_");
297 gate
->add_strpool_attribute("\\src", cell
->get_strpool_attribute("\\src"));
298 gate
->setPort("\\A", lut_data
[i
]);
299 gate
->setPort("\\B", lut_data
[i
+1]);
300 gate
->setPort("\\S", lut_ctrl
[idx
]);
301 gate
->setPort("\\Y", new_lut_data
[i
/2]);
303 lut_data
= new_lut_data
;
306 module
->connect(cell
->getPort("\\Y"), lut_data
);
309 void simplemap_slice(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
311 int offset
= cell
->parameters
.at("\\OFFSET").as_int();
312 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
313 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
314 module
->connect(RTLIL::SigSig(sig_y
, sig_a
.extract(offset
, sig_y
.size())));
317 void simplemap_concat(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
319 RTLIL::SigSpec sig_ab
= cell
->getPort("\\A");
320 sig_ab
.append(cell
->getPort("\\B"));
321 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
322 module
->connect(RTLIL::SigSig(sig_y
, sig_ab
));
325 void simplemap_sr(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
327 int width
= cell
->parameters
.at("\\WIDTH").as_int();
328 char set_pol
= cell
->parameters
.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
329 char clr_pol
= cell
->parameters
.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
331 RTLIL::SigSpec sig_s
= cell
->getPort("\\SET");
332 RTLIL::SigSpec sig_r
= cell
->getPort("\\CLR");
333 RTLIL::SigSpec sig_q
= cell
->getPort("\\Q");
335 std::string gate_type
= stringf("$_SR_%c%c_", set_pol
, clr_pol
);
337 for (int i
= 0; i
< width
; i
++) {
338 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, gate_type
);
339 gate
->add_strpool_attribute("\\src", cell
->get_strpool_attribute("\\src"));
340 gate
->setPort("\\S", sig_s
[i
]);
341 gate
->setPort("\\R", sig_r
[i
]);
342 gate
->setPort("\\Q", sig_q
[i
]);
346 void simplemap_dff(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
348 int width
= cell
->parameters
.at("\\WIDTH").as_int();
349 char clk_pol
= cell
->parameters
.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
351 RTLIL::SigSpec sig_clk
= cell
->getPort("\\CLK");
352 RTLIL::SigSpec sig_d
= cell
->getPort("\\D");
353 RTLIL::SigSpec sig_q
= cell
->getPort("\\Q");
355 std::string gate_type
= stringf("$_DFF_%c_", clk_pol
);
357 for (int i
= 0; i
< width
; i
++) {
358 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, gate_type
);
359 gate
->add_strpool_attribute("\\src", cell
->get_strpool_attribute("\\src"));
360 gate
->setPort("\\C", sig_clk
);
361 gate
->setPort("\\D", sig_d
[i
]);
362 gate
->setPort("\\Q", sig_q
[i
]);
366 void simplemap_dffe(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
368 int width
= cell
->parameters
.at("\\WIDTH").as_int();
369 char clk_pol
= cell
->parameters
.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
370 char en_pol
= cell
->parameters
.at("\\EN_POLARITY").as_bool() ? 'P' : 'N';
372 RTLIL::SigSpec sig_clk
= cell
->getPort("\\CLK");
373 RTLIL::SigSpec sig_en
= cell
->getPort("\\EN");
374 RTLIL::SigSpec sig_d
= cell
->getPort("\\D");
375 RTLIL::SigSpec sig_q
= cell
->getPort("\\Q");
377 std::string gate_type
= stringf("$_DFFE_%c%c_", clk_pol
, en_pol
);
379 for (int i
= 0; i
< width
; i
++) {
380 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, gate_type
);
381 gate
->add_strpool_attribute("\\src", cell
->get_strpool_attribute("\\src"));
382 gate
->setPort("\\C", sig_clk
);
383 gate
->setPort("\\E", sig_en
);
384 gate
->setPort("\\D", sig_d
[i
]);
385 gate
->setPort("\\Q", sig_q
[i
]);
389 void simplemap_dffsr(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
391 int width
= cell
->parameters
.at("\\WIDTH").as_int();
392 char clk_pol
= cell
->parameters
.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
393 char set_pol
= cell
->parameters
.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
394 char clr_pol
= cell
->parameters
.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
396 RTLIL::SigSpec sig_clk
= cell
->getPort("\\CLK");
397 RTLIL::SigSpec sig_s
= cell
->getPort("\\SET");
398 RTLIL::SigSpec sig_r
= cell
->getPort("\\CLR");
399 RTLIL::SigSpec sig_d
= cell
->getPort("\\D");
400 RTLIL::SigSpec sig_q
= cell
->getPort("\\Q");
402 std::string gate_type
= stringf("$_DFFSR_%c%c%c_", clk_pol
, set_pol
, clr_pol
);
404 for (int i
= 0; i
< width
; i
++) {
405 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, gate_type
);
406 gate
->add_strpool_attribute("\\src", cell
->get_strpool_attribute("\\src"));
407 gate
->setPort("\\C", sig_clk
);
408 gate
->setPort("\\S", sig_s
[i
]);
409 gate
->setPort("\\R", sig_r
[i
]);
410 gate
->setPort("\\D", sig_d
[i
]);
411 gate
->setPort("\\Q", sig_q
[i
]);
415 void simplemap_adff(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
417 int width
= cell
->parameters
.at("\\WIDTH").as_int();
418 char clk_pol
= cell
->parameters
.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
419 char rst_pol
= cell
->parameters
.at("\\ARST_POLARITY").as_bool() ? 'P' : 'N';
421 std::vector
<RTLIL::State
> rst_val
= cell
->parameters
.at("\\ARST_VALUE").bits
;
422 while (int(rst_val
.size()) < width
)
423 rst_val
.push_back(RTLIL::State::S0
);
425 RTLIL::SigSpec sig_clk
= cell
->getPort("\\CLK");
426 RTLIL::SigSpec sig_rst
= cell
->getPort("\\ARST");
427 RTLIL::SigSpec sig_d
= cell
->getPort("\\D");
428 RTLIL::SigSpec sig_q
= cell
->getPort("\\Q");
430 std::string gate_type_0
= stringf("$_DFF_%c%c0_", clk_pol
, rst_pol
);
431 std::string gate_type_1
= stringf("$_DFF_%c%c1_", clk_pol
, rst_pol
);
433 for (int i
= 0; i
< width
; i
++) {
434 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, rst_val
.at(i
) == RTLIL::State::S1
? gate_type_1
: gate_type_0
);
435 gate
->add_strpool_attribute("\\src", cell
->get_strpool_attribute("\\src"));
436 gate
->setPort("\\C", sig_clk
);
437 gate
->setPort("\\R", sig_rst
);
438 gate
->setPort("\\D", sig_d
[i
]);
439 gate
->setPort("\\Q", sig_q
[i
]);
443 void simplemap_dlatch(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
445 int width
= cell
->parameters
.at("\\WIDTH").as_int();
446 char en_pol
= cell
->parameters
.at("\\EN_POLARITY").as_bool() ? 'P' : 'N';
448 RTLIL::SigSpec sig_en
= cell
->getPort("\\EN");
449 RTLIL::SigSpec sig_d
= cell
->getPort("\\D");
450 RTLIL::SigSpec sig_q
= cell
->getPort("\\Q");
452 std::string gate_type
= stringf("$_DLATCH_%c_", en_pol
);
454 for (int i
= 0; i
< width
; i
++) {
455 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, gate_type
);
456 gate
->add_strpool_attribute("\\src", cell
->get_strpool_attribute("\\src"));
457 gate
->setPort("\\E", sig_en
);
458 gate
->setPort("\\D", sig_d
[i
]);
459 gate
->setPort("\\Q", sig_q
[i
]);
463 void simplemap_get_mappers(std::map
<RTLIL::IdString
, void(*)(RTLIL::Module
*, RTLIL::Cell
*)> &mappers
)
465 mappers
["$not"] = simplemap_not
;
466 mappers
["$pos"] = simplemap_pos
;
467 mappers
["$and"] = simplemap_bitop
;
468 mappers
["$or"] = simplemap_bitop
;
469 mappers
["$xor"] = simplemap_bitop
;
470 mappers
["$xnor"] = simplemap_bitop
;
471 mappers
["$reduce_and"] = simplemap_reduce
;
472 mappers
["$reduce_or"] = simplemap_reduce
;
473 mappers
["$reduce_xor"] = simplemap_reduce
;
474 mappers
["$reduce_xnor"] = simplemap_reduce
;
475 mappers
["$reduce_bool"] = simplemap_reduce
;
476 mappers
["$logic_not"] = simplemap_lognot
;
477 mappers
["$logic_and"] = simplemap_logbin
;
478 mappers
["$logic_or"] = simplemap_logbin
;
479 mappers
["$eq"] = simplemap_eqne
;
480 mappers
["$eqx"] = simplemap_eqne
;
481 mappers
["$ne"] = simplemap_eqne
;
482 mappers
["$nex"] = simplemap_eqne
;
483 mappers
["$mux"] = simplemap_mux
;
484 mappers
["$lut"] = simplemap_lut
;
485 mappers
["$slice"] = simplemap_slice
;
486 mappers
["$concat"] = simplemap_concat
;
487 mappers
["$sr"] = simplemap_sr
;
488 mappers
["$dff"] = simplemap_dff
;
489 mappers
["$dffe"] = simplemap_dffe
;
490 mappers
["$dffsr"] = simplemap_dffsr
;
491 mappers
["$adff"] = simplemap_adff
;
492 mappers
["$dlatch"] = simplemap_dlatch
;
495 void simplemap(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
497 static std::map
<RTLIL::IdString
, void(*)(RTLIL::Module
*, RTLIL::Cell
*)> mappers
;
498 static bool initialized_mappers
= false;
500 if (!initialized_mappers
) {
501 simplemap_get_mappers(mappers
);
502 initialized_mappers
= true;
505 mappers
.at(cell
->type
)(module
, cell
);
509 PRIVATE_NAMESPACE_BEGIN
511 struct SimplemapPass
: public Pass
{
512 SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") { }
515 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
517 log(" simplemap [selection]\n");
519 log("This pass maps a small selection of simple coarse-grain cells to yosys gate\n");
520 log("primitives. The following internal cell types are mapped by this pass:\n");
522 log(" $not, $pos, $and, $or, $xor, $xnor\n");
523 log(" $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
524 log(" $logic_not, $logic_and, $logic_or, $mux\n");
525 log(" $sr, $dff, $dffsr, $adff, $dlatch\n");
528 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
530 log_header("Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
531 extra_args(args
, 1, design
);
533 std::map
<RTLIL::IdString
, void(*)(RTLIL::Module
*, RTLIL::Cell
*)> mappers
;
534 simplemap_get_mappers(mappers
);
536 for (auto mod
: design
->modules()) {
537 if (!design
->selected(mod
))
539 std::vector
<RTLIL::Cell
*> cells
= mod
->cells();
540 for (auto cell
: cells
) {
541 if (mappers
.count(cell
->type
) == 0)
543 if (!design
->selected(mod
, cell
))
545 log("Mapping %s.%s (%s).\n", log_id(mod
), log_id(cell
), log_id(cell
->type
));
546 mappers
.at(cell
->type
)(mod
, cell
);
553 PRIVATE_NAMESPACE_END