2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/sigtools.h"
22 #include "kernel/log.h"
27 extern void simplemap_get_mappers(std::map
<RTLIL::IdString
, void(*)(RTLIL::Module
*, RTLIL::Cell
*)> &mappers
);
29 static void simplemap_not(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
31 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
32 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
34 sig_a
.extend(SIZE(sig_y
), cell
->parameters
.at("\\A_SIGNED").as_bool());
36 for (int i
= 0; i
< SIZE(sig_y
); i
++) {
37 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, "$_NOT_");
38 gate
->setPort("\\A", sig_a
[i
]);
39 gate
->setPort("\\Y", sig_y
[i
]);
43 static void simplemap_pos(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
45 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
46 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
48 sig_a
.extend_u0(SIZE(sig_y
), cell
->parameters
.at("\\A_SIGNED").as_bool());
50 module
->connect(RTLIL::SigSig(sig_y
, sig_a
));
53 static void simplemap_bitop(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
55 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
56 RTLIL::SigSpec sig_b
= cell
->getPort("\\B");
57 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
59 sig_a
.extend_u0(SIZE(sig_y
), cell
->parameters
.at("\\A_SIGNED").as_bool());
60 sig_b
.extend_u0(SIZE(sig_y
), cell
->parameters
.at("\\B_SIGNED").as_bool());
62 if (cell
->type
== "$xnor")
64 RTLIL::SigSpec sig_t
= module
->addWire(NEW_ID
, SIZE(sig_y
));
66 for (int i
= 0; i
< SIZE(sig_y
); i
++) {
67 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, "$_NOT_");
68 gate
->setPort("\\A", sig_t
[i
]);
69 gate
->setPort("\\Y", sig_y
[i
]);
75 std::string gate_type
;
76 if (cell
->type
== "$and") gate_type
= "$_AND_";
77 if (cell
->type
== "$or") gate_type
= "$_OR_";
78 if (cell
->type
== "$xor") gate_type
= "$_XOR_";
79 if (cell
->type
== "$xnor") gate_type
= "$_XOR_";
80 log_assert(!gate_type
.empty());
82 for (int i
= 0; i
< SIZE(sig_y
); i
++) {
83 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, gate_type
);
84 gate
->setPort("\\A", sig_a
[i
]);
85 gate
->setPort("\\B", sig_b
[i
]);
86 gate
->setPort("\\Y", sig_y
[i
]);
90 static void simplemap_reduce(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
92 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
93 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
95 if (sig_y
.size() == 0)
98 if (sig_a
.size() == 0) {
99 if (cell
->type
== "$reduce_and") module
->connect(RTLIL::SigSig(sig_y
, RTLIL::SigSpec(1, sig_y
.size())));
100 if (cell
->type
== "$reduce_or") module
->connect(RTLIL::SigSig(sig_y
, RTLIL::SigSpec(0, sig_y
.size())));
101 if (cell
->type
== "$reduce_xor") module
->connect(RTLIL::SigSig(sig_y
, RTLIL::SigSpec(0, sig_y
.size())));
102 if (cell
->type
== "$reduce_xnor") module
->connect(RTLIL::SigSig(sig_y
, RTLIL::SigSpec(1, sig_y
.size())));
103 if (cell
->type
== "$reduce_bool") module
->connect(RTLIL::SigSig(sig_y
, RTLIL::SigSpec(0, sig_y
.size())));
107 if (sig_y
.size() > 1) {
108 module
->connect(RTLIL::SigSig(sig_y
.extract(1, sig_y
.size()-1), RTLIL::SigSpec(0, sig_y
.size()-1)));
109 sig_y
= sig_y
.extract(0, 1);
112 std::string gate_type
;
113 if (cell
->type
== "$reduce_and") gate_type
= "$_AND_";
114 if (cell
->type
== "$reduce_or") gate_type
= "$_OR_";
115 if (cell
->type
== "$reduce_xor") gate_type
= "$_XOR_";
116 if (cell
->type
== "$reduce_xnor") gate_type
= "$_XOR_";
117 if (cell
->type
== "$reduce_bool") gate_type
= "$_OR_";
118 log_assert(!gate_type
.empty());
120 RTLIL::Cell
*last_output_cell
= NULL
;
122 while (sig_a
.size() > 1)
124 RTLIL::SigSpec sig_t
= module
->addWire(NEW_ID
, sig_a
.size() / 2);
126 for (int i
= 0; i
< sig_a
.size(); i
+= 2)
128 if (i
+1 == sig_a
.size()) {
129 sig_t
.append(sig_a
[i
]);
133 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, gate_type
);
134 gate
->setPort("\\A", sig_a
[i
]);
135 gate
->setPort("\\B", sig_a
[i
+1]);
136 gate
->setPort("\\Y", sig_t
[i
/2]);
137 last_output_cell
= gate
;
143 if (cell
->type
== "$reduce_xnor") {
144 RTLIL::SigSpec sig_t
= module
->addWire(NEW_ID
);
145 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, "$_NOT_");
146 gate
->setPort("\\A", sig_a
);
147 gate
->setPort("\\Y", sig_t
);
148 last_output_cell
= gate
;
152 if (last_output_cell
== NULL
) {
153 module
->connect(RTLIL::SigSig(sig_y
, sig_a
));
155 last_output_cell
->setPort("\\Y", sig_y
);
159 static void logic_reduce(RTLIL::Module
*module
, RTLIL::SigSpec
&sig
)
161 while (sig
.size() > 1)
163 RTLIL::SigSpec sig_t
= module
->addWire(NEW_ID
, sig
.size() / 2);
165 for (int i
= 0; i
< sig
.size(); i
+= 2)
167 if (i
+1 == sig
.size()) {
168 sig_t
.append(sig
[i
]);
172 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, "$_OR_");
173 gate
->setPort("\\A", sig
[i
]);
174 gate
->setPort("\\B", sig
[i
+1]);
175 gate
->setPort("\\Y", sig_t
[i
/2]);
182 sig
= RTLIL::SigSpec(0, 1);
185 static void simplemap_lognot(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
187 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
188 logic_reduce(module
, sig_a
);
190 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
192 if (sig_y
.size() == 0)
195 if (sig_y
.size() > 1) {
196 module
->connect(RTLIL::SigSig(sig_y
.extract(1, sig_y
.size()-1), RTLIL::SigSpec(0, sig_y
.size()-1)));
197 sig_y
= sig_y
.extract(0, 1);
200 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, "$_NOT_");
201 gate
->setPort("\\A", sig_a
);
202 gate
->setPort("\\Y", sig_y
);
205 static void simplemap_logbin(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
207 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
208 logic_reduce(module
, sig_a
);
210 RTLIL::SigSpec sig_b
= cell
->getPort("\\B");
211 logic_reduce(module
, sig_b
);
213 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
215 if (sig_y
.size() == 0)
218 if (sig_y
.size() > 1) {
219 module
->connect(RTLIL::SigSig(sig_y
.extract(1, sig_y
.size()-1), RTLIL::SigSpec(0, sig_y
.size()-1)));
220 sig_y
= sig_y
.extract(0, 1);
223 std::string gate_type
;
224 if (cell
->type
== "$logic_and") gate_type
= "$_AND_";
225 if (cell
->type
== "$logic_or") gate_type
= "$_OR_";
226 log_assert(!gate_type
.empty());
228 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, gate_type
);
229 gate
->setPort("\\A", sig_a
);
230 gate
->setPort("\\B", sig_b
);
231 gate
->setPort("\\Y", sig_y
);
234 static void simplemap_mux(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
236 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
237 RTLIL::SigSpec sig_b
= cell
->getPort("\\B");
238 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
240 for (int i
= 0; i
< SIZE(sig_y
); i
++) {
241 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, "$_MUX_");
242 gate
->setPort("\\A", sig_a
[i
]);
243 gate
->setPort("\\B", sig_b
[i
]);
244 gate
->setPort("\\S", cell
->getPort("\\S"));
245 gate
->setPort("\\Y", sig_y
[i
]);
249 static void simplemap_slice(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
251 int offset
= cell
->parameters
.at("\\OFFSET").as_int();
252 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
253 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
254 module
->connect(RTLIL::SigSig(sig_y
, sig_a
.extract(offset
, sig_y
.size())));
257 static void simplemap_concat(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
259 RTLIL::SigSpec sig_ab
= cell
->getPort("\\A");
260 sig_ab
.append(cell
->getPort("\\B"));
261 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
262 module
->connect(RTLIL::SigSig(sig_y
, sig_ab
));
265 static void simplemap_sr(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
267 int width
= cell
->parameters
.at("\\WIDTH").as_int();
268 char set_pol
= cell
->parameters
.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
269 char clr_pol
= cell
->parameters
.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
271 RTLIL::SigSpec sig_s
= cell
->getPort("\\SET");
272 RTLIL::SigSpec sig_r
= cell
->getPort("\\CLR");
273 RTLIL::SigSpec sig_q
= cell
->getPort("\\Q");
275 std::string gate_type
= stringf("$_SR_%c%c_", set_pol
, clr_pol
);
277 for (int i
= 0; i
< width
; i
++) {
278 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, gate_type
);
279 gate
->setPort("\\S", sig_s
[i
]);
280 gate
->setPort("\\R", sig_r
[i
]);
281 gate
->setPort("\\Q", sig_q
[i
]);
285 static void simplemap_dff(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
287 int width
= cell
->parameters
.at("\\WIDTH").as_int();
288 char clk_pol
= cell
->parameters
.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
290 RTLIL::SigSpec sig_clk
= cell
->getPort("\\CLK");
291 RTLIL::SigSpec sig_d
= cell
->getPort("\\D");
292 RTLIL::SigSpec sig_q
= cell
->getPort("\\Q");
294 std::string gate_type
= stringf("$_DFF_%c_", clk_pol
);
296 for (int i
= 0; i
< width
; i
++) {
297 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, gate_type
);
298 gate
->setPort("\\C", sig_clk
);
299 gate
->setPort("\\D", sig_d
[i
]);
300 gate
->setPort("\\Q", sig_q
[i
]);
304 static void simplemap_dffsr(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
306 int width
= cell
->parameters
.at("\\WIDTH").as_int();
307 char clk_pol
= cell
->parameters
.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
308 char set_pol
= cell
->parameters
.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
309 char clr_pol
= cell
->parameters
.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
311 RTLIL::SigSpec sig_clk
= cell
->getPort("\\CLK");
312 RTLIL::SigSpec sig_s
= cell
->getPort("\\SET");
313 RTLIL::SigSpec sig_r
= cell
->getPort("\\CLR");
314 RTLIL::SigSpec sig_d
= cell
->getPort("\\D");
315 RTLIL::SigSpec sig_q
= cell
->getPort("\\Q");
317 std::string gate_type
= stringf("$_DFFSR_%c%c%c_", clk_pol
, set_pol
, clr_pol
);
319 for (int i
= 0; i
< width
; i
++) {
320 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, gate_type
);
321 gate
->setPort("\\C", sig_clk
);
322 gate
->setPort("\\S", sig_s
[i
]);
323 gate
->setPort("\\R", sig_r
[i
]);
324 gate
->setPort("\\D", sig_d
[i
]);
325 gate
->setPort("\\Q", sig_q
[i
]);
329 static void simplemap_adff(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
331 int width
= cell
->parameters
.at("\\WIDTH").as_int();
332 char clk_pol
= cell
->parameters
.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
333 char rst_pol
= cell
->parameters
.at("\\ARST_POLARITY").as_bool() ? 'P' : 'N';
335 std::vector
<RTLIL::State
> rst_val
= cell
->parameters
.at("\\ARST_VALUE").bits
;
336 while (int(rst_val
.size()) < width
)
337 rst_val
.push_back(RTLIL::State::S0
);
339 RTLIL::SigSpec sig_clk
= cell
->getPort("\\CLK");
340 RTLIL::SigSpec sig_rst
= cell
->getPort("\\ARST");
341 RTLIL::SigSpec sig_d
= cell
->getPort("\\D");
342 RTLIL::SigSpec sig_q
= cell
->getPort("\\Q");
344 std::string gate_type_0
= stringf("$_DFF_%c%c0_", clk_pol
, rst_pol
);
345 std::string gate_type_1
= stringf("$_DFF_%c%c1_", clk_pol
, rst_pol
);
347 for (int i
= 0; i
< width
; i
++) {
348 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, rst_val
.at(i
) == RTLIL::State::S1
? gate_type_1
: gate_type_0
);
349 gate
->setPort("\\C", sig_clk
);
350 gate
->setPort("\\R", sig_rst
);
351 gate
->setPort("\\D", sig_d
[i
]);
352 gate
->setPort("\\Q", sig_q
[i
]);
356 static void simplemap_dlatch(RTLIL::Module
*module
, RTLIL::Cell
*cell
)
358 int width
= cell
->parameters
.at("\\WIDTH").as_int();
359 char en_pol
= cell
->parameters
.at("\\EN_POLARITY").as_bool() ? 'P' : 'N';
361 RTLIL::SigSpec sig_en
= cell
->getPort("\\EN");
362 RTLIL::SigSpec sig_d
= cell
->getPort("\\D");
363 RTLIL::SigSpec sig_q
= cell
->getPort("\\Q");
365 std::string gate_type
= stringf("$_DLATCH_%c_", en_pol
);
367 for (int i
= 0; i
< width
; i
++) {
368 RTLIL::Cell
*gate
= module
->addCell(NEW_ID
, gate_type
);
369 gate
->setPort("\\E", sig_en
);
370 gate
->setPort("\\D", sig_d
[i
]);
371 gate
->setPort("\\Q", sig_q
[i
]);
375 void simplemap_get_mappers(std::map
<RTLIL::IdString
, void(*)(RTLIL::Module
*, RTLIL::Cell
*)> &mappers
)
377 mappers
["$not"] = simplemap_not
;
378 mappers
["$pos"] = simplemap_pos
;
379 mappers
["$and"] = simplemap_bitop
;
380 mappers
["$or"] = simplemap_bitop
;
381 mappers
["$xor"] = simplemap_bitop
;
382 mappers
["$xnor"] = simplemap_bitop
;
383 mappers
["$reduce_and"] = simplemap_reduce
;
384 mappers
["$reduce_or"] = simplemap_reduce
;
385 mappers
["$reduce_xor"] = simplemap_reduce
;
386 mappers
["$reduce_xnor"] = simplemap_reduce
;
387 mappers
["$reduce_bool"] = simplemap_reduce
;
388 mappers
["$logic_not"] = simplemap_lognot
;
389 mappers
["$logic_and"] = simplemap_logbin
;
390 mappers
["$logic_or"] = simplemap_logbin
;
391 mappers
["$mux"] = simplemap_mux
;
392 mappers
["$slice"] = simplemap_slice
;
393 mappers
["$concat"] = simplemap_concat
;
394 mappers
["$sr"] = simplemap_sr
;
395 mappers
["$dff"] = simplemap_dff
;
396 mappers
["$dffsr"] = simplemap_dffsr
;
397 mappers
["$adff"] = simplemap_adff
;
398 mappers
["$dlatch"] = simplemap_dlatch
;
401 struct SimplemapPass
: public Pass
{
402 SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") { }
405 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
407 log(" simplemap [selection]\n");
409 log("This pass maps a small selection of simple coarse-grain cells to yosys gate\n");
410 log("primitives. The following internal cell types are mapped by this pass:\n");
412 log(" $not, $pos, $and, $or, $xor, $xnor\n");
413 log(" $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
414 log(" $logic_not, $logic_and, $logic_or, $mux\n");
415 log(" $sr, $dff, $dffsr, $adff, $dlatch\n");
418 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
420 log_header("Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
421 extra_args(args
, 1, design
);
423 std::map
<RTLIL::IdString
, void(*)(RTLIL::Module
*, RTLIL::Cell
*)> mappers
;
424 simplemap_get_mappers(mappers
);
426 for (auto mod
: design
->modules()) {
427 if (!design
->selected(mod
))
429 std::vector
<RTLIL::Cell
*> cells
= mod
->cells();
430 for (auto cell
: cells
) {
431 if (mappers
.count(cell
->type
) == 0)
433 if (!design
->selected(mod
, cell
))
435 log("Mapping %s.%s (%s).\n", log_id(mod
), log_id(cell
), log_id(cell
->type
));
436 mappers
.at(cell
->type
)(mod
, cell
);