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abc9_ops: still emit delay table even box has no timing
[yosys.git] / passes / techmap / techmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/utils.h"
22 #include "kernel/sigtools.h"
23 #include "libs/sha1/sha1.h"
24
25 #include <stdlib.h>
26 #include <stdio.h>
27 #include <string.h>
28
29 #include "simplemap.h"
30 #include "passes/techmap/techmap.inc"
31
32 YOSYS_NAMESPACE_BEGIN
33
34 // see maccmap.cc
35 extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false);
36
37 YOSYS_NAMESPACE_END
38
39 USING_YOSYS_NAMESPACE
40 PRIVATE_NAMESPACE_BEGIN
41
42 void apply_prefix(IdString prefix, IdString &id)
43 {
44 if (id[0] == '\\')
45 id = stringf("%s.%s", prefix.c_str(), id.c_str()+1);
46 else
47 id = stringf("$techmap%s.%s", prefix.c_str(), id.c_str());
48 }
49
50 void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
51 {
52 vector<SigChunk> chunks = sig;
53 for (auto &chunk : chunks)
54 if (chunk.wire != NULL) {
55 IdString wire_name = chunk.wire->name;
56 apply_prefix(prefix, wire_name);
57 log_assert(module->wires_.count(wire_name) > 0);
58 chunk.wire = module->wires_[wire_name];
59 }
60 sig = chunks;
61 }
62
63 struct TechmapWorker
64 {
65 std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
66 std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
67 std::map<RTLIL::Module*, bool> techmap_do_cache;
68 std::set<RTLIL::Module*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Module>> module_queue;
69 dict<Module*, SigMap> sigmaps;
70
71 pool<IdString> flatten_do_list;
72 pool<IdString> flatten_done_list;
73 pool<Cell*> flatten_keep_list;
74
75 pool<string> log_msg_cache;
76
77 struct TechmapWireData {
78 RTLIL::Wire *wire;
79 RTLIL::SigSpec value;
80 };
81
82 typedef std::map<std::string, std::vector<TechmapWireData>> TechmapWires;
83
84 bool extern_mode;
85 bool assert_mode;
86 bool flatten_mode;
87 bool recursive_mode;
88 bool autoproc_mode;
89 bool ignore_wb;
90
91 TechmapWorker()
92 {
93 extern_mode = false;
94 assert_mode = false;
95 flatten_mode = false;
96 recursive_mode = false;
97 autoproc_mode = false;
98 ignore_wb = false;
99 }
100
101 std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose)
102 {
103 std::string constmap_info;
104 std::map<RTLIL::SigBit, std::pair<RTLIL::IdString, int>> connbits_map;
105
106 for (auto conn : cell->connections())
107 for (int i = 0; i < GetSize(conn.second); i++) {
108 RTLIL::SigBit bit = sigmap(conn.second[i]);
109 if (bit.wire == nullptr) {
110 if (verbose)
111 log(" Constant input on bit %d of port %s: %s\n", i, log_id(conn.first), log_signal(bit));
112 constmap_info += stringf("|%s %d %d", log_id(conn.first), i, bit.data);
113 } else if (connbits_map.count(bit)) {
114 if (verbose)
115 log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, log_id(conn.first),
116 connbits_map.at(bit).second, log_id(connbits_map.at(bit).first));
117 constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i,
118 log_id(connbits_map.at(bit).first), connbits_map.at(bit).second);
119 } else {
120 connbits_map[bit] = std::pair<RTLIL::IdString, int>(conn.first, i);
121 constmap_info += stringf("|%s %d", log_id(conn.first), i);
122 }
123 }
124
125 return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str());
126 }
127
128 TechmapWires techmap_find_special_wires(RTLIL::Module *module)
129 {
130 TechmapWires result;
131
132 if (module == NULL)
133 return result;
134
135 for (auto &it : module->wires_) {
136 const char *p = it.first.c_str();
137 if (*p == '$')
138 continue;
139
140 const char *q = strrchr(p+1, '.');
141 p = q ? q+1 : p+1;
142
143 if (!strncmp(p, "_TECHMAP_", 9)) {
144 TechmapWireData record;
145 record.wire = it.second;
146 record.value = it.second;
147 result[p].push_back(record);
148 it.second->attributes[ID::keep] = RTLIL::Const(1);
149 it.second->attributes[ID(_techmap_special_)] = RTLIL::Const(1);
150 }
151 }
152
153 if (!result.empty()) {
154 SigMap sigmap(module);
155 for (auto &it1 : result)
156 for (auto &it2 : it1.second)
157 sigmap.apply(it2.value);
158 }
159
160 return result;
161 }
162
163 void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl)
164 {
165 if (tpl->processes.size() != 0) {
166 log("Technology map yielded processes:");
167 for (auto &it : tpl->processes)
168 log(" %s",RTLIL::id2cstr(it.first));
169 log("\n");
170 if (autoproc_mode) {
171 Pass::call_on_module(tpl->design, tpl, "proc");
172 log_assert(GetSize(tpl->processes) == 0);
173 } else
174 log_error("Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).\n");
175 }
176
177 std::string orig_cell_name;
178 pool<string> extra_src_attrs = cell->get_strpool_attribute(ID(src));
179
180 if (!flatten_mode) {
181 for (auto &it : tpl->cells_)
182 if (it.first == ID(_TECHMAP_REPLACE_)) {
183 orig_cell_name = cell->name.str();
184 module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
185 break;
186 }
187 }
188
189 dict<IdString, IdString> memory_renames;
190
191 for (auto &it : tpl->memories) {
192 IdString m_name = it.first;
193 apply_prefix(cell->name, m_name);
194 RTLIL::Memory *m = new RTLIL::Memory;
195 m->name = m_name;
196 m->width = it.second->width;
197 m->start_offset = it.second->start_offset;
198 m->size = it.second->size;
199 m->attributes = it.second->attributes;
200 if (m->attributes.count(ID(src)))
201 m->add_strpool_attribute(ID(src), extra_src_attrs);
202 module->memories[m->name] = m;
203 memory_renames[it.first] = m->name;
204 design->select(module, m);
205 }
206
207 std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
208 dict<Wire*, IdString> temp_renamed_wires;
209 pool<SigBit> autopurge_tpl_bits;
210
211 for (auto &it : tpl->wires_)
212 {
213 if (it.second->port_id > 0)
214 {
215 IdString posportname = stringf("$%d", it.second->port_id);
216 positional_ports[posportname] = it.first;
217
218 if (!flatten_mode && it.second->get_bool_attribute(ID(techmap_autopurge)) &&
219 (!cell->hasPort(it.second->name) || !GetSize(cell->getPort(it.second->name))) &&
220 (!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname))))
221 {
222 if (sigmaps.count(tpl) == 0)
223 sigmaps[tpl].set(tpl);
224
225 for (auto bit : sigmaps.at(tpl)(it.second))
226 if (bit.wire != nullptr)
227 autopurge_tpl_bits.insert(bit);
228 }
229 }
230 IdString w_name = it.second->name;
231 apply_prefix(cell->name, w_name);
232 RTLIL::Wire *w = module->wire(w_name);
233 if (w != nullptr) {
234 if (!flatten_mode || !w->get_bool_attribute(ID(hierconn))) {
235 temp_renamed_wires[w] = w->name;
236 module->rename(w, NEW_ID);
237 w = nullptr;
238 } else {
239 w->attributes.erase(ID(hierconn));
240 if (GetSize(w) < GetSize(it.second)) {
241 log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w),
242 log_id(tpl), log_id(it.second), log_id(module), log_id(cell));
243 w->width = GetSize(it.second);
244 }
245 }
246 }
247 if (w == nullptr) {
248 w = module->addWire(w_name, it.second);
249 w->port_input = false;
250 w->port_output = false;
251 w->port_id = 0;
252 if (!flatten_mode)
253 w->attributes.erase(ID(techmap_autopurge));
254 if (it.second->get_bool_attribute(ID(_techmap_special_)))
255 w->attributes.clear();
256 if (w->attributes.count(ID(src)))
257 w->add_strpool_attribute(ID(src), extra_src_attrs);
258 }
259 design->select(module, w);
260
261 if (it.second->name.begins_with("\\_TECHMAP_REPLACE_.")) {
262 IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), it.second->name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
263 Wire *replace_w = module->addWire(replace_name, it.second);
264 module->connect(replace_w, w);
265 }
266 }
267
268 SigMap tpl_sigmap(tpl);
269 pool<SigBit> tpl_written_bits;
270
271 for (auto &it1 : tpl->cells_)
272 for (auto &it2 : it1.second->connections_)
273 if (it1.second->output(it2.first))
274 for (auto bit : tpl_sigmap(it2.second))
275 tpl_written_bits.insert(bit);
276 for (auto &it1 : tpl->connections_)
277 for (auto bit : tpl_sigmap(it1.first))
278 tpl_written_bits.insert(bit);
279
280 SigMap port_signal_map;
281 SigSig port_signal_assign;
282
283 for (auto &it : cell->connections())
284 {
285 RTLIL::IdString portname = it.first;
286 if (positional_ports.count(portname) > 0)
287 portname = positional_ports.at(portname);
288 if (tpl->wires_.count(portname) == 0 || tpl->wires_.at(portname)->port_id == 0) {
289 if (portname.begins_with("$"))
290 log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
291 continue;
292 }
293
294 if (GetSize(it.second) == 0)
295 continue;
296
297 RTLIL::Wire *w = tpl->wires_.at(portname);
298 RTLIL::SigSig c, extra_connect;
299
300 if (w->port_output && !w->port_input) {
301 c.first = it.second;
302 c.second = RTLIL::SigSpec(w);
303 apply_prefix(cell->name, c.second, module);
304 extra_connect.first = c.second;
305 extra_connect.second = c.first;
306 } else if (!w->port_output && w->port_input) {
307 c.first = RTLIL::SigSpec(w);
308 c.second = it.second;
309 apply_prefix(cell->name, c.first, module);
310 extra_connect.first = c.first;
311 extra_connect.second = c.second;
312 } else {
313 SigSpec sig_tpl = w, sig_tpl_pf = w, sig_mod = it.second;
314 apply_prefix(cell->name, sig_tpl_pf, module);
315 for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) {
316 if (tpl_written_bits.count(tpl_sigmap(sig_tpl[i]))) {
317 c.first.append(sig_mod[i]);
318 c.second.append(sig_tpl_pf[i]);
319 } else {
320 c.first.append(sig_tpl_pf[i]);
321 c.second.append(sig_mod[i]);
322 }
323 }
324 extra_connect.first = sig_tpl_pf;
325 extra_connect.second = sig_mod;
326 }
327
328 if (c.second.size() > c.first.size())
329 c.second.remove(c.first.size(), c.second.size() - c.first.size());
330
331 if (c.second.size() < c.first.size())
332 c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
333
334 log_assert(c.first.size() == c.second.size());
335
336 if (flatten_mode)
337 {
338 // more conservative approach:
339 // connect internal and external wires
340
341 if (sigmaps.count(module) == 0)
342 sigmaps[module].set(module);
343
344 if (sigmaps.at(module)(c.first).has_const())
345 log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
346 log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second));
347
348 module->connect(c);
349 }
350 else
351 {
352 // approach that yields nicer outputs:
353 // replace internal wires that are connected to external wires
354
355 if (w->port_output && !w->port_input) {
356 port_signal_map.add(c.second, c.first);
357 } else
358 if (!w->port_output && w->port_input) {
359 port_signal_map.add(c.first, c.second);
360 } else {
361 module->connect(c);
362 extra_connect = SigSig();
363 }
364
365 for (auto &attr : w->attributes) {
366 if (attr.first == ID(src))
367 continue;
368 auto lhs = GetSize(extra_connect.first);
369 auto rhs = GetSize(extra_connect.second);
370 if (lhs > rhs)
371 extra_connect.first.remove(rhs, lhs-rhs);
372 else if (rhs > lhs)
373 extra_connect.second.remove(lhs, rhs-lhs);
374 module->connect(extra_connect);
375 break;
376 }
377 }
378 }
379
380 for (auto &it : tpl->cells_)
381 {
382 IdString c_name = it.second->name.str();
383 bool techmap_replace_cell = (!flatten_mode) && (c_name == ID(_TECHMAP_REPLACE_));
384
385 if (techmap_replace_cell)
386 c_name = orig_cell_name;
387 else if (it.second->name.begins_with("\\_TECHMAP_REPLACE_."))
388 c_name = stringf("%s%s", orig_cell_name.c_str(), c_name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
389 else
390 apply_prefix(cell->name, c_name);
391
392 RTLIL::Cell *c = module->addCell(c_name, it.second);
393 design->select(module, c);
394
395 if (!flatten_mode && c->type.begins_with("\\$"))
396 c->type = c->type.substr(1);
397
398 vector<IdString> autopurge_ports;
399
400 for (auto &it2 : c->connections_)
401 {
402 bool autopurge = false;
403 if (!autopurge_tpl_bits.empty()) {
404 autopurge = GetSize(it2.second) != 0;
405 for (auto &bit : sigmaps.at(tpl)(it2.second))
406 if (!autopurge_tpl_bits.count(bit)) {
407 autopurge = false;
408 break;
409 }
410 }
411
412 if (autopurge) {
413 autopurge_ports.push_back(it2.first);
414 } else {
415 apply_prefix(cell->name, it2.second, module);
416 port_signal_map.apply(it2.second);
417 }
418 }
419
420 for (auto &it2 : autopurge_ports)
421 c->unsetPort(it2);
422
423 if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
424 IdString memid = c->getParam(ID(MEMID)).decode_string();
425 log_assert(memory_renames.count(memid) != 0);
426 c->setParam(ID(MEMID), Const(memory_renames[memid].str()));
427 }
428
429 if (c->type == ID($mem)) {
430 IdString memid = c->getParam(ID(MEMID)).decode_string();
431 apply_prefix(cell->name, memid);
432 c->setParam(ID(MEMID), Const(memid.c_str()));
433 }
434
435 if (c->attributes.count(ID(src)))
436 c->add_strpool_attribute(ID(src), extra_src_attrs);
437
438 if (techmap_replace_cell)
439 for (auto attr : cell->attributes)
440 if (!c->attributes.count(attr.first))
441 c->attributes[attr.first] = attr.second;
442 }
443
444 for (auto &it : tpl->connections()) {
445 RTLIL::SigSig c = it;
446 apply_prefix(cell->name.str(), c.first, module);
447 apply_prefix(cell->name.str(), c.second, module);
448 port_signal_map.apply(c.first);
449 port_signal_map.apply(c.second);
450 module->connect(c);
451 }
452
453 module->remove(cell);
454
455 for (auto &it : temp_renamed_wires)
456 {
457 Wire *w = it.first;
458 IdString name = it.second;
459 IdString altname = module->uniquify(name);
460 Wire *other_w = module->wire(name);
461 module->rename(other_w, altname);
462 module->rename(w, name);
463 }
464 }
465
466 bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
467 const std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> &celltypeMap, bool in_recursion)
468 {
469 std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";
470
471 if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb))
472 return false;
473
474 bool log_continue = false;
475 bool did_something = false;
476 LogMakeDebugHdl mkdebug;
477
478 SigMap sigmap(module);
479
480 dict<SigBit, State> init_bits;
481 pool<SigBit> remove_init_bits;
482
483 for (auto wire : module->wires()) {
484 if (wire->attributes.count("\\init")) {
485 Const value = wire->attributes.at("\\init");
486 for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
487 if (value[i] != State::Sx)
488 init_bits[sigmap(SigBit(wire, i))] = value[i];
489 }
490 }
491
492 TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
493 std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
494 std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
495
496 for (auto cell : module->cells())
497 {
498 if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
499 continue;
500
501 std::string cell_type = cell->type.str();
502 if (in_recursion && cell->type.begins_with("\\$"))
503 cell_type = cell_type.substr(1);
504
505 if (celltypeMap.count(cell_type) == 0) {
506 if (assert_mode && cell_type.back() != '_')
507 log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type));
508 continue;
509 }
510
511 if (flatten_mode) {
512 bool keepit = cell->get_bool_attribute(ID(keep_hierarchy));
513 for (auto &tpl_name : celltypeMap.at(cell_type))
514 if (map->modules_[tpl_name]->get_bool_attribute(ID(keep_hierarchy)))
515 keepit = true;
516 if (keepit) {
517 if (!flatten_keep_list[cell]) {
518 log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell));
519 flatten_keep_list.insert(cell);
520 }
521 if (!flatten_done_list[cell->type])
522 flatten_do_list.insert(cell->type);
523 continue;
524 }
525 }
526
527 for (auto &conn : cell->connections())
528 {
529 RTLIL::SigSpec sig = sigmap(conn.second);
530 sig.remove_const();
531
532 if (GetSize(sig) == 0)
533 continue;
534
535 for (auto &tpl_name : celltypeMap.at(cell_type)) {
536 RTLIL::Module *tpl = map->modules_[tpl_name];
537 RTLIL::Wire *port = tpl->wire(conn.first);
538 if (port && port->port_input)
539 cell_to_inbit[cell].insert(sig.begin(), sig.end());
540 if (port && port->port_output)
541 for (auto &bit : sig)
542 outbit_to_cell[bit].insert(cell);
543 }
544 }
545
546 cells.node(cell);
547 }
548
549 for (auto &it_right : cell_to_inbit)
550 for (auto &it_sigbit : it_right.second)
551 for (auto &it_left : outbit_to_cell[it_sigbit])
552 cells.edge(it_left, it_right.first);
553
554 cells.sort();
555
556 for (auto cell : cells.sorted)
557 {
558 log_assert(handled_cells.count(cell) == 0);
559 log_assert(cell == module->cell(cell->name));
560 bool mapped_cell = false;
561
562 std::string cell_type = cell->type.str();
563
564 if (in_recursion && cell->type.begins_with("\\$"))
565 cell_type = cell_type.substr(1);
566
567 for (auto &tpl_name : celltypeMap.at(cell_type))
568 {
569 RTLIL::IdString derived_name = tpl_name;
570 RTLIL::Module *tpl = map->modules_[tpl_name];
571 std::map<RTLIL::IdString, RTLIL::Const> parameters(cell->parameters.begin(), cell->parameters.end());
572
573 if (tpl->get_blackbox_attribute(ignore_wb))
574 continue;
575
576 if (!flatten_mode)
577 {
578 std::string extmapper_name;
579
580 if (tpl->get_bool_attribute(ID(techmap_simplemap)))
581 extmapper_name = "simplemap";
582
583 if (tpl->get_bool_attribute(ID(techmap_maccmap)))
584 extmapper_name = "maccmap";
585
586 if (tpl->attributes.count(ID(techmap_wrap)))
587 extmapper_name = "wrap";
588
589 if (!extmapper_name.empty())
590 {
591 cell->type = cell_type;
592
593 if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
594 {
595 std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
596
597 for (auto &c : cell->parameters)
598 m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
599
600 if (extmapper_name == "wrap")
601 m_name += ":" + sha1(tpl->attributes.at(ID(techmap_wrap)).decode_string());
602
603 RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
604 RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
605
606 if (extmapper_module == nullptr)
607 {
608 extmapper_module = extmapper_design->addModule(m_name);
609 RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
610
611 extmapper_cell->set_src_attribute(cell->get_src_attribute());
612
613 int port_counter = 1;
614 for (auto &c : extmapper_cell->connections_) {
615 RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
616 if (w->name.in(ID::Y, ID(Q)))
617 w->port_output = true;
618 else
619 w->port_input = true;
620 w->port_id = port_counter++;
621 c.second = w;
622 }
623
624 extmapper_module->fixup_ports();
625 extmapper_module->check();
626
627 if (extmapper_name == "simplemap") {
628 log("Creating %s with simplemap.\n", log_id(extmapper_module));
629 if (simplemap_mappers.count(extmapper_cell->type) == 0)
630 log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
631 simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
632 extmapper_module->remove(extmapper_cell);
633 }
634
635 if (extmapper_name == "maccmap") {
636 log("Creating %s with maccmap.\n", log_id(extmapper_module));
637 if (extmapper_cell->type != ID($macc))
638 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
639 maccmap(extmapper_module, extmapper_cell);
640 extmapper_module->remove(extmapper_cell);
641 }
642
643 if (extmapper_name == "wrap") {
644 std::string cmd_string = tpl->attributes.at(ID(techmap_wrap)).decode_string();
645 log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
646 mkdebug.on();
647 Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
648 log_continue = true;
649 }
650 }
651
652 cell->type = extmapper_module->name;
653 cell->parameters.clear();
654
655 if (!extern_mode || in_recursion) {
656 tpl = extmapper_module;
657 goto use_wrapper_tpl;
658 }
659
660 auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
661 if (!log_msg_cache.count(msg)) {
662 log_msg_cache.insert(msg);
663 log("%s\n", msg.c_str());
664 }
665 log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
666 }
667 else
668 {
669 auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type));
670 if (!log_msg_cache.count(msg)) {
671 log_msg_cache.insert(msg);
672 log("%s\n", msg.c_str());
673 }
674 log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
675
676 if (extmapper_name == "simplemap") {
677 if (simplemap_mappers.count(cell->type) == 0)
678 log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
679 simplemap_mappers.at(cell->type)(module, cell);
680 }
681
682 if (extmapper_name == "maccmap") {
683 if (cell->type != ID($macc))
684 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
685 maccmap(module, cell);
686 }
687
688 module->remove(cell);
689 cell = NULL;
690 }
691
692 did_something = true;
693 mapped_cell = true;
694 break;
695 }
696
697 for (auto conn : cell->connections()) {
698 if (conn.first.begins_with("$"))
699 continue;
700 if (tpl->wires_.count(conn.first) > 0 && tpl->wires_.at(conn.first)->port_id > 0)
701 continue;
702 if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
703 goto next_tpl;
704 parameters[conn.first] = conn.second.as_const();
705 }
706
707 if (0) {
708 next_tpl:
709 continue;
710 }
711
712 if (tpl->avail_parameters.count(ID(_TECHMAP_CELLTYPE_)) != 0)
713 parameters[ID(_TECHMAP_CELLTYPE_)] = RTLIL::unescape_id(cell->type);
714
715 for (auto conn : cell->connections()) {
716 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
717 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
718 for (auto &bit : v)
719 bit = RTLIL::SigBit(bit.wire == NULL ? RTLIL::State::S1 : RTLIL::State::S0);
720 parameters[stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
721 }
722 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))) != 0) {
723 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
724 for (auto &bit : v)
725 if (bit.wire != NULL)
726 bit = RTLIL::SigBit(RTLIL::State::Sx);
727 parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
728 }
729 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))) != 0) {
730 auto sig = sigmap(conn.second);
731 RTLIL::Const value(State::Sx, sig.size());
732 for (int i = 0; i < sig.size(); i++) {
733 auto it = init_bits.find(sig[i]);
734 if (it != init_bits.end()) {
735 value[i] = it->second;
736 }
737 }
738 parameters[stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))] = value;
739 }
740 }
741
742 int unique_bit_id_counter = 0;
743 std::map<RTLIL::SigBit, int> unique_bit_id;
744 unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++;
745 unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++;
746 unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++;
747 unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
748
749 for (auto conn : cell->connections())
750 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
751 for (auto &bit : sigmap(conn.second).to_sigbit_vector())
752 if (unique_bit_id.count(bit) == 0)
753 unique_bit_id[bit] = unique_bit_id_counter++;
754 }
755
756 // Find highest bit set
757 int bits = 0;
758 for (int i = 0; i < 32; i++)
759 if (((unique_bit_id_counter-1) & (1 << i)) != 0)
760 bits = i;
761 // Increment index by one to get number of bits
762 bits++;
763 if (tpl->avail_parameters.count(ID(_TECHMAP_BITS_CONNMAP_)))
764 parameters[ID(_TECHMAP_BITS_CONNMAP_)] = bits;
765
766 for (auto conn : cell->connections())
767 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
768 RTLIL::Const value;
769 for (auto &bit : sigmap(conn.second).to_sigbit_vector()) {
770 RTLIL::Const chunk(unique_bit_id.at(bit), bits);
771 value.bits.insert(value.bits.end(), chunk.bits.begin(), chunk.bits.end());
772 }
773 parameters[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))] = value;
774 }
775 }
776
777 if (0) {
778 use_wrapper_tpl:;
779 // do not register techmap_wrap modules with techmap_cache
780 } else {
781 std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
782 if (techmap_cache.count(key) > 0) {
783 tpl = techmap_cache[key];
784 } else {
785 if (parameters.size() != 0) {
786 mkdebug.on();
787 derived_name = tpl->derive(map, dict<RTLIL::IdString, RTLIL::Const>(parameters.begin(), parameters.end()));
788 tpl = map->module(derived_name);
789 log_continue = true;
790 }
791 techmap_cache[key] = tpl;
792 }
793 }
794
795 if (flatten_mode) {
796 techmap_do_cache[tpl] = true;
797 } else {
798 RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false));
799 if (constmapped_tpl != nullptr)
800 tpl = constmapped_tpl;
801 }
802
803 if (techmap_do_cache.count(tpl) == 0)
804 {
805 bool keep_running = true;
806 techmap_do_cache[tpl] = true;
807
808 std::set<std::string> techmap_wire_names;
809
810 while (keep_running)
811 {
812 TechmapWires twd = techmap_find_special_wires(tpl);
813 keep_running = false;
814
815 for (auto &it : twd)
816 techmap_wire_names.insert(it.first);
817
818 for (auto &it : twd["_TECHMAP_FAIL_"]) {
819 RTLIL::SigSpec value = it.value;
820 if (value.is_fully_const() && value.as_bool()) {
821 log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
822 derived_name.c_str(), RTLIL::id2cstr(it.wire->name), log_signal(value));
823 techmap_do_cache[tpl] = false;
824 }
825 }
826
827 if (!techmap_do_cache[tpl])
828 break;
829
830 for (auto &it : twd)
831 {
832 if (it.first.compare(0, 12, "_TECHMAP_DO_") != 0 || it.second.empty())
833 continue;
834
835 auto &data = it.second.front();
836
837 if (!data.value.is_fully_const())
838 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));
839
840 techmap_wire_names.erase(it.first);
841
842 const char *p = data.wire->name.c_str();
843 const char *q = strrchr(p+1, '.');
844 q = q ? q : p+1;
845
846 std::string cmd_string = data.value.as_const().decode_string();
847
848 restart_eval_cmd_string:
849 if (cmd_string.rfind("CONSTMAP; ", 0) == 0)
850 {
851 cmd_string = cmd_string.substr(strlen("CONSTMAP; "));
852
853 log("Analyzing pattern of constant bits for this cell:\n");
854 RTLIL::IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
855 log("Creating constmapped module `%s'.\n", log_id(new_tpl_name));
856 log_assert(map->module(new_tpl_name) == nullptr);
857
858 RTLIL::Module *new_tpl = map->addModule(new_tpl_name);
859 tpl->cloneInto(new_tpl);
860
861 techmap_do_cache.erase(tpl);
862 techmap_do_cache[new_tpl] = true;
863 tpl = new_tpl;
864
865 std::map<RTLIL::SigBit, RTLIL::SigBit> port_new2old_map;
866 std::map<RTLIL::SigBit, RTLIL::SigBit> port_connmap;
867 std::map<RTLIL::SigBit, RTLIL::SigBit> cellbits_to_tplbits;
868
869 for (auto wire : tpl->wires().to_vector())
870 {
871 if (!wire->port_input || wire->port_output)
872 continue;
873
874 RTLIL::IdString port_name = wire->name;
875 tpl->rename(wire, NEW_ID);
876
877 RTLIL::Wire *new_wire = tpl->addWire(port_name, wire);
878 wire->port_input = false;
879 wire->port_id = 0;
880
881 for (int i = 0; i < wire->width; i++) {
882 port_new2old_map[RTLIL::SigBit(new_wire, i)] = RTLIL::SigBit(wire, i);
883 port_connmap[RTLIL::SigBit(wire, i)] = RTLIL::SigBit(new_wire, i);
884 }
885 }
886
887 for (auto conn : cell->connections())
888 for (int i = 0; i < GetSize(conn.second); i++)
889 {
890 RTLIL::SigBit bit = sigmap(conn.second[i]);
891 RTLIL::SigBit tplbit(tpl->wire(conn.first), i);
892
893 if (bit.wire == nullptr)
894 {
895 RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
896 port_connmap.at(oldbit) = bit;
897 }
898 else if (cellbits_to_tplbits.count(bit))
899 {
900 RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
901 port_connmap.at(oldbit) = cellbits_to_tplbits[bit];
902 }
903 else
904 cellbits_to_tplbits[bit] = tplbit;
905 }
906
907 RTLIL::SigSig port_conn;
908 for (auto &it : port_connmap) {
909 port_conn.first.append_bit(it.first);
910 port_conn.second.append_bit(it.second);
911 }
912 tpl->connect(port_conn);
913
914 tpl->check();
915 goto restart_eval_cmd_string;
916 }
917
918 if (cmd_string.rfind("RECURSION; ", 0) == 0)
919 {
920 cmd_string = cmd_string.substr(strlen("RECURSION; "));
921 while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
922 goto restart_eval_cmd_string;
923 }
924
925 Pass::call_on_module(map, tpl, cmd_string);
926
927 log_assert(!strncmp(q, "_TECHMAP_DO_", 12));
928 std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
929 while (tpl->wires_.count(new_name))
930 new_name += "_";
931 tpl->rename(data.wire->name, new_name);
932
933 keep_running = true;
934 break;
935 }
936 }
937
938 TechmapWires twd = techmap_find_special_wires(tpl);
939 for (auto &it : twd) {
940 if (it.first != "_TECHMAP_FAIL_" && (it.first.substr(0, 20) != "_TECHMAP_REMOVEINIT_" || it.first[it.first.size()-1] != '_') && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
941 log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str());
942 if (techmap_do_cache[tpl])
943 for (auto &it2 : it.second)
944 if (!it2.value.is_fully_const())
945 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
946 techmap_wire_names.erase(it.first);
947 }
948
949 for (auto &it : techmap_wire_names)
950 log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it));
951
952 if (recursive_mode) {
953 if (log_continue) {
954 log_header(design, "Continuing TECHMAP pass.\n");
955 log_continue = false;
956 mkdebug.off();
957 }
958 while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
959 }
960 }
961
962 if (techmap_do_cache.at(tpl) == false)
963 continue;
964
965 if (log_continue) {
966 log_header(design, "Continuing TECHMAP pass.\n");
967 log_continue = false;
968 mkdebug.off();
969 }
970
971 TechmapWires twd = techmap_find_special_wires(tpl);
972 for (auto &it : twd) {
973 if (it.first.substr(0, 20) == "_TECHMAP_REMOVEINIT_") {
974 for (auto &it2 : it.second) {
975 auto val = it2.value.as_const();
976 auto wirename = RTLIL::escape_id(it.first.substr(20, it.first.size() - 20 - 1));
977 auto it = cell->connections().find(wirename);
978 if (it != cell->connections().end()) {
979 auto sig = sigmap(it->second);
980 for (int i = 0; i < sig.size(); i++)
981 if (val[i] == State::S1)
982 remove_init_bits.insert(sig[i]);
983 }
984 }
985 }
986 }
987
988 if (extern_mode && !in_recursion)
989 {
990 std::string m_name = stringf("$extern:%s", log_id(tpl));
991
992 if (!design->module(m_name))
993 {
994 RTLIL::Module *m = design->addModule(m_name);
995 tpl->cloneInto(m);
996
997 for (auto cell : m->cells()) {
998 if (cell->type.begins_with("\\$"))
999 cell->type = cell->type.substr(1);
1000 }
1001
1002 module_queue.insert(m);
1003 }
1004
1005 log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name));
1006 cell->type = m_name;
1007 cell->parameters.clear();
1008 }
1009 else
1010 {
1011 auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type));
1012 if (!log_msg_cache.count(msg)) {
1013 log_msg_cache.insert(msg);
1014 log("%s\n", msg.c_str());
1015 }
1016 log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl));
1017 techmap_module_worker(design, module, cell, tpl);
1018 cell = NULL;
1019 }
1020 did_something = true;
1021 mapped_cell = true;
1022 break;
1023 }
1024
1025 if (assert_mode && !mapped_cell)
1026 log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
1027
1028 handled_cells.insert(cell);
1029 }
1030
1031 if (!remove_init_bits.empty()) {
1032 for (auto wire : module->wires())
1033 if (wire->attributes.count("\\init")) {
1034 Const &value = wire->attributes.at("\\init");
1035 bool do_cleanup = true;
1036 for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
1037 SigBit bit = sigmap(SigBit(wire, i));
1038 if (remove_init_bits.count(bit))
1039 value[i] = State::Sx;
1040 else if (value[i] != State::Sx)
1041 do_cleanup = false;
1042 }
1043 if (do_cleanup) {
1044 log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
1045 wire->attributes.erase("\\init");
1046 }
1047 }
1048 }
1049
1050 if (log_continue) {
1051 log_header(design, "Continuing TECHMAP pass.\n");
1052 log_continue = false;
1053 mkdebug.off();
1054 }
1055
1056 return did_something;
1057 }
1058 };
1059
1060 struct TechmapPass : public Pass {
1061 TechmapPass() : Pass("techmap", "generic technology mapper") { }
1062 void help() YS_OVERRIDE
1063 {
1064 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1065 log("\n");
1066 log(" techmap [-map filename] [selection]\n");
1067 log("\n");
1068 log("This pass implements a very simple technology mapper that replaces cells in\n");
1069 log("the design with implementations given in form of a Verilog or ilang source\n");
1070 log("file.\n");
1071 log("\n");
1072 log(" -map filename\n");
1073 log(" the library of cell implementations to be used.\n");
1074 log(" without this parameter a builtin library is used that\n");
1075 log(" transforms the internal RTL cells to the internal gate\n");
1076 log(" library.\n");
1077 log("\n");
1078 log(" -map %%<design-name>\n");
1079 log(" like -map above, but with an in-memory design instead of a file.\n");
1080 log("\n");
1081 log(" -extern\n");
1082 log(" load the cell implementations as separate modules into the design\n");
1083 log(" instead of inlining them.\n");
1084 log("\n");
1085 log(" -max_iter <number>\n");
1086 log(" only run the specified number of iterations on each module.\n");
1087 log(" default: unlimited\n");
1088 log("\n");
1089 log(" -recursive\n");
1090 log(" instead of the iterative breadth-first algorithm use a recursive\n");
1091 log(" depth-first algorithm. both methods should yield equivalent results,\n");
1092 log(" but may differ in performance.\n");
1093 log("\n");
1094 log(" -autoproc\n");
1095 log(" Automatically call \"proc\" on implementations that contain processes.\n");
1096 log("\n");
1097 log(" -wb\n");
1098 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
1099 log("\n");
1100 log(" -assert\n");
1101 log(" this option will cause techmap to exit with an error if it can't map\n");
1102 log(" a selected cell. only cell types that end on an underscore are accepted\n");
1103 log(" as final cell types by this mode.\n");
1104 log("\n");
1105 log(" -D <define>, -I <incdir>\n");
1106 log(" this options are passed as-is to the Verilog frontend for loading the\n");
1107 log(" map file. Note that the Verilog frontend is also called with the\n");
1108 log(" '-nooverwrite' option set.\n");
1109 log("\n");
1110 log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
1111 log("match cells with a type that match the text value of this attribute. Otherwise\n");
1112 log("the module name will be used to match the cell.\n");
1113 log("\n");
1114 log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
1115 log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
1116 log("\n");
1117 log("When a module in the map file has the 'techmap_maccmap' attribute set, techmap\n");
1118 log("will use 'maccmap' (see 'help maccmap') to map cells matching the module.\n");
1119 log("\n");
1120 log("When a module in the map file has the 'techmap_wrap' attribute set, techmap\n");
1121 log("will create a wrapper for the cell and then run the command string that the\n");
1122 log("attribute is set to on the wrapper module.\n");
1123 log("\n");
1124 log("When a port on a module in the map file has the 'techmap_autopurge' attribute\n");
1125 log("set, and that port is not connected in the instantiation that is mapped, then\n");
1126 log("then a cell port connected only to such wires will be omitted in the mapped\n");
1127 log("version of the circuit.\n");
1128 log("\n");
1129 log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
1130 log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
1131 log("the mapping module to the techmap command. At the moment the following special\n");
1132 log("wires are supported:\n");
1133 log("\n");
1134 log(" _TECHMAP_FAIL_\n");
1135 log(" When this wire is set to a non-zero constant value, techmap will not\n");
1136 log(" use this module and instead try the next module with a matching\n");
1137 log(" 'techmap_celltype' attribute.\n");
1138 log("\n");
1139 log(" When such a wire exists but does not have a constant value after all\n");
1140 log(" _TECHMAP_DO_* commands have been executed, an error is generated.\n");
1141 log("\n");
1142 log(" _TECHMAP_DO_*\n");
1143 log(" This wires are evaluated in alphabetical order. The constant text value\n");
1144 log(" of this wire is a yosys command (or sequence of commands) that is run\n");
1145 log(" by techmap on the module. A common use case is to run 'proc' on modules\n");
1146 log(" that are written using always-statements.\n");
1147 log("\n");
1148 log(" When such a wire has a non-constant value at the time it is to be\n");
1149 log(" evaluated, an error is produced. That means it is possible for such a\n");
1150 log(" wire to start out as non-constant and evaluate to a constant value\n");
1151 log(" during processing of other _TECHMAP_DO_* commands.\n");
1152 log("\n");
1153 log(" A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.\n");
1154 log(" in this case techmap will create a copy for each distinct configuration\n");
1155 log(" of constant inputs and shorted inputs at this point and import the\n");
1156 log(" constant and connected bits into the map module. All further commands\n");
1157 log(" are executed in this copy. This is a very convenient way of creating\n");
1158 log(" optimized specializations of techmap modules without using the special\n");
1159 log(" parameters described below.\n");
1160 log("\n");
1161 log(" A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.\n");
1162 log(" then techmap will recursively replace the cells in the module with their\n");
1163 log(" implementation. This is not affected by the -max_iter option.\n");
1164 log("\n");
1165 log(" It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n");
1166 log("\n");
1167 log(" _TECHMAP_REMOVEINIT_<port-name>_\n");
1168 log(" When this wire is set to a constant value, the init attribute of the wire(s)\n");
1169 log(" connected to this port will be consumed. This wire must have the same\n");
1170 log(" width as the given port, and for every bit that is set to 1 in the value,\n");
1171 log(" the corresponding init attribute bit will be changed to 1'bx. If all\n");
1172 log(" bits of an init attribute are left as x, it will be removed.\n");
1173 log("\n");
1174 log("In addition to this special wires, techmap also supports special parameters in\n");
1175 log("modules in the map file:\n");
1176 log("\n");
1177 log(" _TECHMAP_CELLTYPE_\n");
1178 log(" When a parameter with this name exists, it will be set to the type name\n");
1179 log(" of the cell that matches the module.\n");
1180 log("\n");
1181 log(" _TECHMAP_CONSTMSK_<port-name>_\n");
1182 log(" _TECHMAP_CONSTVAL_<port-name>_\n");
1183 log(" When this pair of parameters is available in a module for a port, then\n");
1184 log(" former has a 1-bit for each constant input bit and the latter has the\n");
1185 log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
1186 log("\n");
1187 log(" _TECHMAP_WIREINIT_<port-name>_\n");
1188 log(" When a parameter with this name exists, it will be set to the initial\n");
1189 log(" value of the wire(s) connected to the given port, as specified by the init\n");
1190 log(" attribute. If the attribute doesn't exist, x will be filled for the\n");
1191 log(" missing bits. To remove the init attribute bits used, use the\n");
1192 log(" _TECHMAP_REMOVEINIT_*_ wires.\n");
1193 log("\n");
1194 log(" _TECHMAP_BITS_CONNMAP_\n");
1195 log(" _TECHMAP_CONNMAP_<port-name>_\n");
1196 log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
1197 log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n");
1198 log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n");
1199 log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n");
1200 log(" This can be used to detect shorted inputs.\n");
1201 log("\n");
1202 log("When a module in the map file has a parameter where the according cell in the\n");
1203 log("design has a port, the module from the map file is only used if the port in\n");
1204 log("the design is connected to a constant value. The parameter is then set to the\n");
1205 log("constant value.\n");
1206 log("\n");
1207 log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
1208 log("and attributes of the cell that is being replaced.\n");
1209 log("A cell with a name of the form `_TECHMAP_REPLACE_.<suffix>` in the map file will\n");
1210 log("be named thus but with the `_TECHMAP_REPLACE_' prefix substituted with the name\n");
1211 log("of the cell being replaced.\n");
1212 log("Similarly, a wire named in the form `_TECHMAP_REPLACE_.<suffix>` will cause a\n");
1213 log("new wire alias to be created and named as above but with the `_TECHMAP_REPLACE_'\n");
1214 log("prefix also substituted.\n");
1215 log("\n");
1216 log("See 'help extract' for a pass that does the opposite thing.\n");
1217 log("\n");
1218 log("See 'help flatten' for a pass that does flatten the design (which is\n");
1219 log("essentially techmap but using the design itself as map library).\n");
1220 log("\n");
1221 }
1222 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1223 {
1224 log_header(design, "Executing TECHMAP pass (map to technology primitives).\n");
1225 log_push();
1226
1227 TechmapWorker worker;
1228 simplemap_get_mappers(worker.simplemap_mappers);
1229
1230 std::vector<std::string> map_files;
1231 std::string verilog_frontend = "verilog -nooverwrite -noblackbox";
1232 int max_iter = -1;
1233
1234 size_t argidx;
1235 for (argidx = 1; argidx < args.size(); argidx++) {
1236 if (args[argidx] == "-map" && argidx+1 < args.size()) {
1237 map_files.push_back(args[++argidx]);
1238 continue;
1239 }
1240 if (args[argidx] == "-max_iter" && argidx+1 < args.size()) {
1241 max_iter = atoi(args[++argidx].c_str());
1242 continue;
1243 }
1244 if (args[argidx] == "-D" && argidx+1 < args.size()) {
1245 verilog_frontend += " -D " + args[++argidx];
1246 continue;
1247 }
1248 if (args[argidx] == "-I" && argidx+1 < args.size()) {
1249 verilog_frontend += " -I " + args[++argidx];
1250 continue;
1251 }
1252 if (args[argidx] == "-assert") {
1253 worker.assert_mode = true;
1254 continue;
1255 }
1256 if (args[argidx] == "-extern") {
1257 worker.extern_mode = true;
1258 continue;
1259 }
1260 if (args[argidx] == "-recursive") {
1261 worker.recursive_mode = true;
1262 continue;
1263 }
1264 if (args[argidx] == "-autoproc") {
1265 worker.autoproc_mode = true;
1266 continue;
1267 }
1268 if (args[argidx] == "-wb") {
1269 worker.ignore_wb = true;
1270 continue;
1271 }
1272 break;
1273 }
1274 extra_args(args, argidx, design);
1275
1276 RTLIL::Design *map = new RTLIL::Design;
1277 if (map_files.empty()) {
1278 std::istringstream f(stdcells_code);
1279 Frontend::frontend_call(map, &f, "<techmap.v>", verilog_frontend);
1280 } else {
1281 for (auto &fn : map_files)
1282 if (fn.compare(0, 1, "%") == 0) {
1283 if (!saved_designs.count(fn.substr(1))) {
1284 delete map;
1285 log_cmd_error("Can't saved design `%s'.\n", fn.c_str()+1);
1286 }
1287 for (auto mod : saved_designs.at(fn.substr(1))->modules())
1288 if (!map->has(mod->name))
1289 map->add(mod->clone());
1290 } else {
1291 std::ifstream f;
1292 rewrite_filename(fn);
1293 f.open(fn.c_str());
1294 yosys_input_files.insert(fn);
1295 if (f.fail())
1296 log_cmd_error("Can't open map file `%s'\n", fn.c_str());
1297 Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend));
1298 }
1299 }
1300
1301 log_header(design, "Continuing TECHMAP pass.\n");
1302
1303 std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
1304 for (auto &it : map->modules_) {
1305 if (it.second->attributes.count(ID(techmap_celltype)) && !it.second->attributes.at(ID(techmap_celltype)).bits.empty()) {
1306 char *p = strdup(it.second->attributes.at(ID(techmap_celltype)).decode_string().c_str());
1307 for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
1308 celltypeMap[RTLIL::escape_id(q)].insert(it.first);
1309 free(p);
1310 } else {
1311 string module_name = it.first.str();
1312 if (it.first.begins_with("\\$"))
1313 module_name = module_name.substr(1);
1314 celltypeMap[module_name].insert(it.first);
1315 }
1316 }
1317
1318 for (auto module : design->modules())
1319 worker.module_queue.insert(module);
1320
1321 while (!worker.module_queue.empty())
1322 {
1323 RTLIL::Module *module = *worker.module_queue.begin();
1324 worker.module_queue.erase(module);
1325
1326 int module_max_iter = max_iter;
1327 bool did_something = true;
1328 std::set<RTLIL::Cell*> handled_cells;
1329 while (did_something) {
1330 did_something = false;
1331 if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
1332 did_something = true;
1333 if (did_something)
1334 module->check();
1335 if (module_max_iter > 0 && --module_max_iter == 0)
1336 break;
1337 }
1338 }
1339
1340 log("No more expansions possible.\n");
1341 delete map;
1342
1343 log_pop();
1344 }
1345 } TechmapPass;
1346
1347 struct FlattenPass : public Pass {
1348 FlattenPass() : Pass("flatten", "flatten design") { }
1349 void help() YS_OVERRIDE
1350 {
1351 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1352 log("\n");
1353 log(" flatten [options] [selection]\n");
1354 log("\n");
1355 log("This pass flattens the design by replacing cells by their implementation. This\n");
1356 log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
1357 log("pass is using the current design as mapping library.\n");
1358 log("\n");
1359 log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
1360 log("flattened by this command.\n");
1361 log("\n");
1362 log(" -wb\n");
1363 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
1364 log("\n");
1365 }
1366 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1367 {
1368 log_header(design, "Executing FLATTEN pass (flatten design).\n");
1369 log_push();
1370
1371 TechmapWorker worker;
1372 worker.flatten_mode = true;
1373
1374 size_t argidx;
1375 for (argidx = 1; argidx < args.size(); argidx++) {
1376 if (args[argidx] == "-wb") {
1377 worker.ignore_wb = true;
1378 continue;
1379 }
1380 break;
1381 }
1382 extra_args(args, argidx, design);
1383
1384
1385 std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
1386 for (auto module : design->modules())
1387 celltypeMap[module->name].insert(module->name);
1388
1389 RTLIL::Module *top_mod = NULL;
1390 if (design->full_selection())
1391 for (auto mod : design->modules())
1392 if (mod->get_bool_attribute(ID(top)))
1393 top_mod = mod;
1394
1395 std::set<RTLIL::Cell*> handled_cells;
1396 if (top_mod != NULL) {
1397 worker.flatten_do_list.insert(top_mod->name);
1398 while (!worker.flatten_do_list.empty()) {
1399 auto mod = design->module(*worker.flatten_do_list.begin());
1400 while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
1401 worker.flatten_done_list.insert(mod->name);
1402 worker.flatten_do_list.erase(mod->name);
1403 }
1404 } else {
1405 for (auto mod : vector<Module*>(design->modules())) {
1406 while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
1407 }
1408 }
1409
1410 log_suppressed();
1411 log("No more expansions possible.\n");
1412
1413 if (top_mod != NULL)
1414 {
1415 pool<RTLIL::IdString> used_modules, new_used_modules;
1416 new_used_modules.insert(top_mod->name);
1417 while (!new_used_modules.empty()) {
1418 pool<RTLIL::IdString> queue;
1419 queue.swap(new_used_modules);
1420 for (auto modname : queue)
1421 used_modules.insert(modname);
1422 for (auto modname : queue)
1423 for (auto cell : design->module(modname)->cells())
1424 if (design->module(cell->type) && !used_modules[cell->type])
1425 new_used_modules.insert(cell->type);
1426 }
1427
1428 dict<RTLIL::IdString, RTLIL::Module*> new_modules;
1429 for (auto mod : vector<Module*>(design->modules()))
1430 if (used_modules[mod->name] || mod->get_blackbox_attribute(worker.ignore_wb)) {
1431 new_modules[mod->name] = mod;
1432 } else {
1433 log("Deleting now unused module %s.\n", log_id(mod));
1434 delete mod;
1435 }
1436 design->modules_.swap(new_modules);
1437 }
1438
1439 log_pop();
1440 }
1441 } FlattenPass;
1442
1443 PRIVATE_NAMESPACE_END