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0d7c10d0c86de67f8cefbb6521b8bb1573802d7b
[yosys.git] / passes / techmap / techmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/utils.h"
22 #include "kernel/sigtools.h"
23 #include "libs/sha1/sha1.h"
24
25 #include <stdlib.h>
26 #include <stdio.h>
27 #include <string.h>
28
29 #include "simplemap.h"
30
31 YOSYS_NAMESPACE_BEGIN
32
33 // see maccmap.cc
34 extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false);
35
36 YOSYS_NAMESPACE_END
37
38 USING_YOSYS_NAMESPACE
39 PRIVATE_NAMESPACE_BEGIN
40
41 void apply_prefix(IdString prefix, IdString &id)
42 {
43 if (id[0] == '\\')
44 id = stringf("%s.%s", prefix.c_str(), id.c_str()+1);
45 else
46 id = stringf("$techmap%s.%s", prefix.c_str(), id.c_str());
47 }
48
49 void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
50 {
51 vector<SigChunk> chunks = sig;
52 for (auto &chunk : chunks)
53 if (chunk.wire != nullptr) {
54 IdString wire_name = chunk.wire->name;
55 apply_prefix(prefix, wire_name);
56 log_assert(module->wire(wire_name) != nullptr);
57 chunk.wire = module->wire(wire_name);
58 }
59 sig = chunks;
60 }
61
62 struct TechmapWorker
63 {
64 dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
65 dict<std::pair<IdString, dict<IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
66 dict<RTLIL::Module*, bool> techmap_do_cache;
67 pool<RTLIL::Module*> module_queue;
68 dict<Module*, SigMap> sigmaps;
69
70 pool<IdString> flatten_do_list;
71 pool<IdString> flatten_done_list;
72 pool<Cell*> flatten_keep_list;
73
74 pool<string> log_msg_cache;
75
76 struct TechmapWireData {
77 RTLIL::Wire *wire;
78 RTLIL::SigSpec value;
79 };
80
81 typedef dict<IdString, std::vector<TechmapWireData>> TechmapWires;
82
83 bool extern_mode;
84 bool assert_mode;
85 bool flatten_mode;
86 bool recursive_mode;
87 bool autoproc_mode;
88 bool ignore_wb;
89
90 TechmapWorker()
91 {
92 extern_mode = false;
93 assert_mode = false;
94 flatten_mode = false;
95 recursive_mode = false;
96 autoproc_mode = false;
97 ignore_wb = false;
98 }
99
100 std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose)
101 {
102 std::string constmap_info;
103 dict<RTLIL::SigBit, std::pair<IdString, int>> connbits_map;
104
105 for (auto &conn : cell->connections())
106 for (int i = 0; i < GetSize(conn.second); i++) {
107 RTLIL::SigBit bit = sigmap(conn.second[i]);
108 if (bit.wire == nullptr) {
109 if (verbose)
110 log(" Constant input on bit %d of port %s: %s\n", i, log_id(conn.first), log_signal(bit));
111 constmap_info += stringf("|%s %d %d", log_id(conn.first), i, bit.data);
112 } else if (connbits_map.count(bit)) {
113 if (verbose)
114 log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, log_id(conn.first),
115 connbits_map.at(bit).second, log_id(connbits_map.at(bit).first));
116 constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i,
117 log_id(connbits_map.at(bit).first), connbits_map.at(bit).second);
118 } else {
119 connbits_map.emplace(bit, std::make_pair(conn.first, i));
120 constmap_info += stringf("|%s %d", log_id(conn.first), i);
121 }
122 }
123
124 return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str());
125 }
126
127 TechmapWires techmap_find_special_wires(RTLIL::Module *module)
128 {
129 TechmapWires result;
130
131 if (module == nullptr)
132 return result;
133
134 for (auto w : module->wires()) {
135 const char *p = w->name.c_str();
136 if (*p == '$')
137 continue;
138
139 const char *q = strrchr(p+1, '.');
140 if (q)
141 p = q;
142
143 if (!strncmp(p, "\\_TECHMAP_", 10)) {
144 TechmapWireData record;
145 record.wire = w;
146 record.value = w;
147 result[p].push_back(record);
148 w->set_bool_attribute(ID::keep);
149 w->set_bool_attribute(ID::_techmap_special_);
150 }
151 }
152
153 if (!result.empty()) {
154 SigMap sigmap(module);
155 for (auto &it1 : result)
156 for (auto &it2 : it1.second)
157 sigmap.apply(it2.value);
158 }
159
160 return result;
161 }
162
163 void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl)
164 {
165 if (tpl->processes.size() != 0) {
166 log("Technology map yielded processes:");
167 for (auto &it : tpl->processes)
168 log(" %s",log_id(it.first));
169 log("\n");
170 if (autoproc_mode) {
171 Pass::call_on_module(tpl->design, tpl, "proc");
172 log_assert(GetSize(tpl->processes) == 0);
173 } else
174 log_error("Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).\n");
175 }
176
177 std::string orig_cell_name;
178 pool<string> extra_src_attrs = cell->get_strpool_attribute(ID::src);
179
180 orig_cell_name = cell->name.str();
181 if (!flatten_mode) {
182 for (auto tpl_cell : tpl->cells())
183 if (tpl_cell->name == ID::_TECHMAP_REPLACE_) {
184 module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
185 break;
186 }
187 }
188
189 dict<IdString, IdString> memory_renames;
190
191 for (auto &it : tpl->memories) {
192 IdString m_name = it.first;
193 apply_prefix(cell->name, m_name);
194 RTLIL::Memory *m = new RTLIL::Memory;
195 m->name = m_name;
196 m->width = it.second->width;
197 m->start_offset = it.second->start_offset;
198 m->size = it.second->size;
199 m->attributes = it.second->attributes;
200 if (m->attributes.count(ID::src))
201 m->add_strpool_attribute(ID::src, extra_src_attrs);
202 module->memories[m->name] = m;
203 memory_renames[it.first] = m->name;
204 design->select(module, m);
205 }
206
207 dict<IdString, IdString> positional_ports;
208 dict<Wire*, IdString> temp_renamed_wires;
209 pool<SigBit> autopurge_tpl_bits;
210
211 for (auto tpl_w : tpl->wires())
212 {
213 if (tpl_w->port_id > 0)
214 {
215 IdString posportname = stringf("$%d", tpl_w->port_id);
216 positional_ports.emplace(posportname, tpl_w->name);
217
218 if (!flatten_mode && tpl_w->get_bool_attribute(ID::techmap_autopurge) &&
219 (!cell->hasPort(tpl_w->name) || !GetSize(cell->getPort(tpl_w->name))) &&
220 (!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname))))
221 {
222 if (sigmaps.count(tpl) == 0)
223 sigmaps[tpl].set(tpl);
224
225 for (auto bit : sigmaps.at(tpl)(tpl_w))
226 if (bit.wire != nullptr)
227 autopurge_tpl_bits.insert(bit);
228 }
229 }
230 IdString w_name = tpl_w->name;
231 apply_prefix(cell->name, w_name);
232 RTLIL::Wire *w = module->wire(w_name);
233 if (w != nullptr) {
234 if (!flatten_mode || !w->get_bool_attribute(ID::hierconn)) {
235 temp_renamed_wires[w] = w->name;
236 module->rename(w, NEW_ID);
237 w = nullptr;
238 } else {
239 w->attributes.erase(ID::hierconn);
240 if (GetSize(w) < GetSize(tpl_w)) {
241 log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w),
242 log_id(tpl), log_id(tpl_w), log_id(module), log_id(cell));
243 w->width = GetSize(tpl_w);
244 }
245 }
246 }
247 if (w == nullptr) {
248 w = module->addWire(w_name, tpl_w);
249 w->port_input = false;
250 w->port_output = false;
251 w->port_id = 0;
252 if (!flatten_mode)
253 w->attributes.erase(ID::techmap_autopurge);
254 if (tpl_w->get_bool_attribute(ID::_techmap_special_))
255 w->attributes.clear();
256 if (w->attributes.count(ID::src))
257 w->add_strpool_attribute(ID::src, extra_src_attrs);
258 }
259 design->select(module, w);
260
261 if (tpl_w->name.begins_with("\\_TECHMAP_REPLACE_.")) {
262 IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), tpl_w->name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
263 Wire *replace_w = module->addWire(replace_name, tpl_w);
264 module->connect(replace_w, w);
265 }
266 }
267
268 SigMap tpl_sigmap(tpl);
269 pool<SigBit> tpl_written_bits;
270
271 for (auto tpl_cell : tpl->cells())
272 for (auto &conn : tpl_cell->connections())
273 if (tpl_cell->output(conn.first))
274 for (auto bit : tpl_sigmap(conn.second))
275 tpl_written_bits.insert(bit);
276 for (auto &conn : tpl->connections())
277 for (auto bit : tpl_sigmap(conn.first))
278 tpl_written_bits.insert(bit);
279
280 SigMap port_signal_map;
281 SigSig port_signal_assign;
282
283 for (auto &it : cell->connections())
284 {
285 IdString portname = it.first;
286 if (positional_ports.count(portname) > 0)
287 portname = positional_ports.at(portname);
288 if (tpl->wire(portname) == nullptr || tpl->wire(portname)->port_id == 0) {
289 if (portname.begins_with("$"))
290 log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
291 continue;
292 }
293
294 if (GetSize(it.second) == 0)
295 continue;
296
297 RTLIL::Wire *w = tpl->wire(portname);
298 RTLIL::SigSig c, extra_connect;
299
300 if (w->port_output && !w->port_input) {
301 c.first = it.second;
302 c.second = RTLIL::SigSpec(w);
303 apply_prefix(cell->name, c.second, module);
304 extra_connect.first = c.second;
305 extra_connect.second = c.first;
306 } else if (!w->port_output && w->port_input) {
307 c.first = RTLIL::SigSpec(w);
308 c.second = it.second;
309 apply_prefix(cell->name, c.first, module);
310 extra_connect.first = c.first;
311 extra_connect.second = c.second;
312 } else {
313 SigSpec sig_tpl = w, sig_tpl_pf = w, sig_mod = it.second;
314 apply_prefix(cell->name, sig_tpl_pf, module);
315 for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) {
316 if (tpl_written_bits.count(tpl_sigmap(sig_tpl[i]))) {
317 c.first.append(sig_mod[i]);
318 c.second.append(sig_tpl_pf[i]);
319 } else {
320 c.first.append(sig_tpl_pf[i]);
321 c.second.append(sig_mod[i]);
322 }
323 }
324 extra_connect.first = sig_tpl_pf;
325 extra_connect.second = sig_mod;
326 }
327
328 if (c.second.size() > c.first.size())
329 c.second.remove(c.first.size(), c.second.size() - c.first.size());
330
331 if (c.second.size() < c.first.size())
332 c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
333
334 log_assert(c.first.size() == c.second.size());
335
336 if (flatten_mode)
337 {
338 // more conservative approach:
339 // connect internal and external wires
340
341 if (sigmaps.count(module) == 0)
342 sigmaps[module].set(module);
343
344 if (sigmaps.at(module)(c.first).has_const())
345 log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
346 log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second));
347
348 module->connect(c);
349 }
350 else
351 {
352 // approach that yields nicer outputs:
353 // replace internal wires that are connected to external wires
354
355 if (w->port_output && !w->port_input) {
356 port_signal_map.add(c.second, c.first);
357 } else
358 if (!w->port_output && w->port_input) {
359 port_signal_map.add(c.first, c.second);
360 } else {
361 module->connect(c);
362 extra_connect = SigSig();
363 }
364
365 for (auto &attr : w->attributes) {
366 if (attr.first == ID::src)
367 continue;
368 auto lhs = GetSize(extra_connect.first);
369 auto rhs = GetSize(extra_connect.second);
370 if (lhs > rhs)
371 extra_connect.first.remove(rhs, lhs-rhs);
372 else if (rhs > lhs)
373 extra_connect.second.remove(lhs, rhs-lhs);
374 module->connect(extra_connect);
375 break;
376 }
377 }
378 }
379
380 for (auto tpl_cell : tpl->cells())
381 {
382 IdString c_name = tpl_cell->name;
383 bool techmap_replace_cell = (!flatten_mode) && (c_name == ID::_TECHMAP_REPLACE_);
384
385 if (techmap_replace_cell)
386 c_name = orig_cell_name;
387 else if (tpl_cell->name.begins_with("\\_TECHMAP_REPLACE_."))
388 c_name = stringf("%s%s", orig_cell_name.c_str(), c_name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
389 else
390 apply_prefix(cell->name, c_name);
391
392 RTLIL::Cell *c = module->addCell(c_name, tpl_cell);
393 design->select(module, c);
394
395 if (!flatten_mode && c->type.begins_with("\\$"))
396 c->type = c->type.substr(1);
397
398 vector<IdString> autopurge_ports;
399
400 for (auto &conn : c->connections())
401 {
402 bool autopurge = false;
403 if (!autopurge_tpl_bits.empty()) {
404 autopurge = GetSize(conn.second) != 0;
405 for (auto &bit : sigmaps.at(tpl)(conn.second))
406 if (!autopurge_tpl_bits.count(bit)) {
407 autopurge = false;
408 break;
409 }
410 }
411
412 if (autopurge) {
413 autopurge_ports.push_back(conn.first);
414 } else {
415 RTLIL::SigSpec new_conn = conn.second;
416 apply_prefix(cell->name, new_conn, module);
417 port_signal_map.apply(new_conn);
418 c->setPort(conn.first, std::move(new_conn));
419 }
420 }
421
422 for (auto &it2 : autopurge_ports)
423 c->unsetPort(it2);
424
425 if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
426 IdString memid = c->getParam(ID::MEMID).decode_string();
427 log_assert(memory_renames.count(memid) != 0);
428 c->setParam(ID::MEMID, Const(memory_renames[memid].str()));
429 }
430
431 if (c->type == ID($mem)) {
432 IdString memid = c->getParam(ID::MEMID).decode_string();
433 apply_prefix(cell->name, memid);
434 c->setParam(ID::MEMID, Const(memid.c_str()));
435 }
436
437 if (c->attributes.count(ID::src))
438 c->add_strpool_attribute(ID::src, extra_src_attrs);
439
440 if (techmap_replace_cell)
441 for (auto attr : cell->attributes)
442 if (!c->attributes.count(attr.first))
443 c->attributes[attr.first] = attr.second;
444 }
445
446 for (auto &it : tpl->connections()) {
447 RTLIL::SigSig c = it;
448 apply_prefix(cell->name.str(), c.first, module);
449 apply_prefix(cell->name.str(), c.second, module);
450 port_signal_map.apply(c.first);
451 port_signal_map.apply(c.second);
452 module->connect(c);
453 }
454
455 module->remove(cell);
456
457 for (auto &it : temp_renamed_wires)
458 {
459 Wire *w = it.first;
460 IdString name = it.second;
461 IdString altname = module->uniquify(name);
462 Wire *other_w = module->wire(name);
463 module->rename(other_w, altname);
464 module->rename(w, name);
465 }
466 }
467
468 bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool<RTLIL::Cell*> &handled_cells,
469 const dict<IdString, pool<IdString>> &celltypeMap, bool in_recursion)
470 {
471 std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";
472
473 if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb))
474 return false;
475
476 bool log_continue = false;
477 bool did_something = false;
478 LogMakeDebugHdl mkdebug;
479
480 SigMap sigmap(module);
481
482 dict<SigBit, State> init_bits;
483 pool<SigBit> remove_init_bits;
484
485 for (auto wire : module->wires()) {
486 if (wire->attributes.count(ID::init)) {
487 Const value = wire->attributes.at(ID::init);
488 for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
489 if (value[i] != State::Sx)
490 init_bits[sigmap(SigBit(wire, i))] = value[i];
491 }
492 }
493
494 TopoSort<RTLIL::Cell*, IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
495 dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_to_inbit;
496 dict<RTLIL::SigBit, pool<RTLIL::Cell*>> outbit_to_cell;
497
498 for (auto cell : module->selected_cells())
499 {
500 if (handled_cells.count(cell) > 0)
501 continue;
502
503 std::string cell_type = cell->type.str();
504 if (in_recursion && cell->type.begins_with("\\$"))
505 cell_type = cell_type.substr(1);
506
507 if (celltypeMap.count(cell_type) == 0) {
508 if (assert_mode && cell_type.back() != '_')
509 log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type));
510 continue;
511 }
512
513 if (flatten_mode) {
514 bool keepit = cell->get_bool_attribute(ID::keep_hierarchy);
515 for (auto &tpl_name : celltypeMap.at(cell_type))
516 if (map->module(tpl_name)->get_bool_attribute(ID::keep_hierarchy))
517 keepit = true;
518 if (keepit) {
519 if (!flatten_keep_list[cell]) {
520 log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell));
521 flatten_keep_list.insert(cell);
522 }
523 if (!flatten_done_list[cell->type])
524 flatten_do_list.insert(cell->type);
525 continue;
526 }
527 }
528
529 for (auto &conn : cell->connections())
530 {
531 RTLIL::SigSpec sig = sigmap(conn.second);
532 sig.remove_const();
533
534 if (GetSize(sig) == 0)
535 continue;
536
537 for (auto &tpl_name : celltypeMap.at(cell_type)) {
538 RTLIL::Module *tpl = map->module(tpl_name);
539 RTLIL::Wire *port = tpl->wire(conn.first);
540 if (port && port->port_input)
541 cell_to_inbit[cell].insert(sig.begin(), sig.end());
542 if (port && port->port_output)
543 for (auto &bit : sig)
544 outbit_to_cell[bit].insert(cell);
545 }
546 }
547
548 cells.node(cell);
549 }
550
551 for (auto &it_right : cell_to_inbit)
552 for (auto &it_sigbit : it_right.second)
553 for (auto &it_left : outbit_to_cell[it_sigbit])
554 cells.edge(it_left, it_right.first);
555
556 cells.sort();
557
558 for (auto cell : cells.sorted)
559 {
560 log_assert(handled_cells.count(cell) == 0);
561 log_assert(cell == module->cell(cell->name));
562 bool mapped_cell = false;
563
564 std::string cell_type = cell->type.str();
565
566 if (in_recursion && cell->type.begins_with("\\$"))
567 cell_type = cell_type.substr(1);
568
569 for (auto &tpl_name : celltypeMap.at(cell_type))
570 {
571 IdString derived_name = tpl_name;
572 RTLIL::Module *tpl = map->module(tpl_name);
573 dict<IdString, RTLIL::Const> parameters(cell->parameters);
574
575 if (tpl->get_blackbox_attribute(ignore_wb))
576 continue;
577
578 if (!flatten_mode)
579 {
580 std::string extmapper_name;
581
582 if (tpl->get_bool_attribute(ID::techmap_simplemap))
583 extmapper_name = "simplemap";
584
585 if (tpl->get_bool_attribute(ID::techmap_maccmap))
586 extmapper_name = "maccmap";
587
588 if (tpl->attributes.count(ID::techmap_wrap))
589 extmapper_name = "wrap";
590
591 if (!extmapper_name.empty())
592 {
593 cell->type = cell_type;
594
595 if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
596 {
597 std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
598
599 for (auto &c : cell->parameters)
600 m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
601
602 if (extmapper_name == "wrap")
603 m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string());
604
605 RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
606 RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
607
608 if (extmapper_module == nullptr)
609 {
610 extmapper_module = extmapper_design->addModule(m_name);
611 RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
612
613 extmapper_cell->set_src_attribute(cell->get_src_attribute());
614
615 int port_counter = 1;
616 for (auto &c : extmapper_cell->connections_) {
617 RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
618 if (w->name.in(ID::Y, ID::Q))
619 w->port_output = true;
620 else
621 w->port_input = true;
622 w->port_id = port_counter++;
623 c.second = w;
624 }
625
626 extmapper_module->fixup_ports();
627 extmapper_module->check();
628
629 if (extmapper_name == "simplemap") {
630 log("Creating %s with simplemap.\n", log_id(extmapper_module));
631 if (simplemap_mappers.count(extmapper_cell->type) == 0)
632 log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
633 simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
634 extmapper_module->remove(extmapper_cell);
635 }
636
637 if (extmapper_name == "maccmap") {
638 log("Creating %s with maccmap.\n", log_id(extmapper_module));
639 if (extmapper_cell->type != ID($macc))
640 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
641 maccmap(extmapper_module, extmapper_cell);
642 extmapper_module->remove(extmapper_cell);
643 }
644
645 if (extmapper_name == "wrap") {
646 std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string();
647 log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
648 mkdebug.on();
649 Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
650 log_continue = true;
651 }
652 }
653
654 cell->type = extmapper_module->name;
655 cell->parameters.clear();
656
657 if (!extern_mode || in_recursion) {
658 tpl = extmapper_module;
659 goto use_wrapper_tpl;
660 }
661
662 auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
663 if (!log_msg_cache.count(msg)) {
664 log_msg_cache.insert(msg);
665 log("%s\n", msg.c_str());
666 }
667 log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
668 }
669 else
670 {
671 auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type));
672 if (!log_msg_cache.count(msg)) {
673 log_msg_cache.insert(msg);
674 log("%s\n", msg.c_str());
675 }
676 log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
677
678 if (extmapper_name == "simplemap") {
679 if (simplemap_mappers.count(cell->type) == 0)
680 log_error("No simplemap mapper for cell type %s found!\n", log_id(cell->type));
681 simplemap_mappers.at(cell->type)(module, cell);
682 }
683
684 if (extmapper_name == "maccmap") {
685 if (cell->type != ID($macc))
686 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
687 maccmap(module, cell);
688 }
689
690 module->remove(cell);
691 cell = nullptr;
692 }
693
694 did_something = true;
695 mapped_cell = true;
696 break;
697 }
698
699 for (auto &conn : cell->connections()) {
700 if (conn.first.begins_with("$"))
701 continue;
702 if (tpl->wire(conn.first) != nullptr && tpl->wire(conn.first)->port_id > 0)
703 continue;
704 if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
705 goto next_tpl;
706 parameters[conn.first] = conn.second.as_const();
707 }
708
709 if (0) {
710 next_tpl:
711 continue;
712 }
713
714 if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0)
715 parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type));
716
717 for (auto &conn : cell->connections()) {
718 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) {
719 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
720 for (auto &bit : v)
721 bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0);
722 parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
723 }
724 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) {
725 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
726 for (auto &bit : v)
727 if (bit.wire != nullptr)
728 bit = RTLIL::SigBit(RTLIL::State::Sx);
729 parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
730 }
731 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) {
732 auto sig = sigmap(conn.second);
733 RTLIL::Const value(State::Sx, sig.size());
734 for (int i = 0; i < sig.size(); i++) {
735 auto it = init_bits.find(sig[i]);
736 if (it != init_bits.end()) {
737 value[i] = it->second;
738 }
739 }
740 parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), value);
741 }
742 }
743
744 int unique_bit_id_counter = 0;
745 dict<RTLIL::SigBit, int> unique_bit_id;
746 unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++;
747 unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++;
748 unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++;
749 unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
750
751 for (auto &conn : cell->connections())
752 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) {
753 for (auto &bit : sigmap(conn.second))
754 if (unique_bit_id.count(bit) == 0)
755 unique_bit_id[bit] = unique_bit_id_counter++;
756 }
757
758 // Find highest bit set
759 int bits = 0;
760 for (int i = 0; i < 32; i++)
761 if (((unique_bit_id_counter-1) & (1 << i)) != 0)
762 bits = i;
763 // Increment index by one to get number of bits
764 bits++;
765 if (tpl->avail_parameters.count(ID::_TECHMAP_BITS_CONNMAP_))
766 parameters[ID::_TECHMAP_BITS_CONNMAP_] = bits;
767
768 for (auto &conn : cell->connections())
769 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) {
770 RTLIL::Const value;
771 for (auto &bit : sigmap(conn.second)) {
772 int val = unique_bit_id.at(bit);
773 for (int i = 0; i < bits; i++) {
774 value.bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
775 val = val >> 1;
776 }
777 }
778 parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first)), value);
779 }
780 }
781
782 if (0) {
783 use_wrapper_tpl:;
784 // do not register techmap_wrap modules with techmap_cache
785 } else {
786 std::pair<IdString, dict<IdString, RTLIL::Const>> key(tpl_name, parameters);
787 auto it = techmap_cache.find(key);
788 if (it != techmap_cache.end()) {
789 tpl = it->second;
790 } else {
791 if (parameters.size() != 0) {
792 mkdebug.on();
793 derived_name = tpl->derive(map, parameters);
794 tpl = map->module(derived_name);
795 log_continue = true;
796 }
797 techmap_cache.emplace(std::move(key), tpl);
798 }
799 }
800
801 if (flatten_mode) {
802 techmap_do_cache[tpl] = true;
803 } else {
804 RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false));
805 if (constmapped_tpl != nullptr)
806 tpl = constmapped_tpl;
807 }
808
809 if (techmap_do_cache.count(tpl) == 0)
810 {
811 bool keep_running = true;
812 techmap_do_cache[tpl] = true;
813
814 pool<IdString> techmap_wire_names;
815
816 while (keep_running)
817 {
818 TechmapWires twd = techmap_find_special_wires(tpl);
819 keep_running = false;
820
821 for (auto &it : twd)
822 techmap_wire_names.insert(it.first);
823
824 for (auto &it : twd[ID::_TECHMAP_FAIL_]) {
825 RTLIL::SigSpec value = it.value;
826 if (value.is_fully_const() && value.as_bool()) {
827 log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
828 derived_name.c_str(), log_id(it.wire->name), log_signal(value));
829 techmap_do_cache[tpl] = false;
830 }
831 }
832
833 if (!techmap_do_cache[tpl])
834 break;
835
836 for (auto &it : twd)
837 {
838 if (!it.first.begins_with("\\_TECHMAP_DO_") || it.second.empty())
839 continue;
840
841 auto &data = it.second.front();
842
843 if (!data.value.is_fully_const())
844 log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(data.wire->name), log_signal(data.value));
845
846 techmap_wire_names.erase(it.first);
847
848 const char *p = data.wire->name.c_str();
849 const char *q = strrchr(p+1, '.');
850 q = q ? q : p+1;
851
852 std::string cmd_string = data.value.as_const().decode_string();
853
854 restart_eval_cmd_string:
855 if (cmd_string.rfind("CONSTMAP; ", 0) == 0)
856 {
857 cmd_string = cmd_string.substr(strlen("CONSTMAP; "));
858
859 log("Analyzing pattern of constant bits for this cell:\n");
860 IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
861 log("Creating constmapped module `%s'.\n", log_id(new_tpl_name));
862 log_assert(map->module(new_tpl_name) == nullptr);
863
864 RTLIL::Module *new_tpl = map->addModule(new_tpl_name);
865 tpl->cloneInto(new_tpl);
866
867 techmap_do_cache.erase(tpl);
868 techmap_do_cache[new_tpl] = true;
869 tpl = new_tpl;
870
871 dict<RTLIL::SigBit, RTLIL::SigBit> port_new2old_map;
872 dict<RTLIL::SigBit, RTLIL::SigBit> port_connmap;
873 dict<RTLIL::SigBit, RTLIL::SigBit> cellbits_to_tplbits;
874
875 for (auto wire : tpl->wires().to_vector())
876 {
877 if (!wire->port_input || wire->port_output)
878 continue;
879
880 IdString port_name = wire->name;
881 tpl->rename(wire, NEW_ID);
882
883 RTLIL::Wire *new_wire = tpl->addWire(port_name, wire);
884 wire->port_input = false;
885 wire->port_id = 0;
886
887 for (int i = 0; i < wire->width; i++) {
888 port_new2old_map.emplace(RTLIL::SigBit(new_wire, i), RTLIL::SigBit(wire, i));
889 port_connmap.emplace(RTLIL::SigBit(wire, i), RTLIL::SigBit(new_wire, i));
890 }
891 }
892
893 for (auto &conn : cell->connections())
894 for (int i = 0; i < GetSize(conn.second); i++)
895 {
896 RTLIL::SigBit bit = sigmap(conn.second[i]);
897 RTLIL::SigBit tplbit(tpl->wire(conn.first), i);
898
899 if (bit.wire == nullptr)
900 {
901 RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
902 port_connmap.at(oldbit) = bit;
903 }
904 else if (cellbits_to_tplbits.count(bit))
905 {
906 RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
907 port_connmap.at(oldbit) = cellbits_to_tplbits[bit];
908 }
909 else
910 cellbits_to_tplbits[bit] = tplbit;
911 }
912
913 RTLIL::SigSig port_conn;
914 for (auto &it : port_connmap) {
915 port_conn.first.append(it.first);
916 port_conn.second.append(it.second);
917 }
918 tpl->connect(port_conn);
919
920 tpl->check();
921 goto restart_eval_cmd_string;
922 }
923
924 if (cmd_string.rfind("RECURSION; ", 0) == 0)
925 {
926 cmd_string = cmd_string.substr(strlen("RECURSION; "));
927 while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
928 goto restart_eval_cmd_string;
929 }
930
931 Pass::call_on_module(map, tpl, cmd_string);
932
933 log_assert(!strncmp(q, "_TECHMAP_DO_", 12));
934 std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
935 while (tpl->wire(new_name) != nullptr)
936 new_name += "_";
937 tpl->rename(data.wire->name, new_name);
938
939 keep_running = true;
940 break;
941 }
942 }
943
944 TechmapWires twd = techmap_find_special_wires(tpl);
945 for (auto &it : twd) {
946 if (it.first != ID::_TECHMAP_FAIL_ && (!it.first.begins_with("\\_TECHMAP_REMOVEINIT_") || !it.first.ends_with("_")) && !it.first.begins_with("\\_TECHMAP_DO_") && !it.first.begins_with("\\_TECHMAP_DONE_"))
947 log_error("Techmap yielded unknown config wire %s.\n", log_id(it.first));
948 if (techmap_do_cache[tpl])
949 for (auto &it2 : it.second)
950 if (!it2.value.is_fully_const())
951 log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(it2.wire->name), log_signal(it2.value));
952 techmap_wire_names.erase(it.first);
953 }
954
955 for (auto &it : techmap_wire_names)
956 log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", log_id(it));
957
958 if (recursive_mode) {
959 if (log_continue) {
960 log_header(design, "Continuing TECHMAP pass.\n");
961 log_continue = false;
962 mkdebug.off();
963 }
964 while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
965 }
966 }
967
968 if (techmap_do_cache.at(tpl) == false)
969 continue;
970
971 if (log_continue) {
972 log_header(design, "Continuing TECHMAP pass.\n");
973 log_continue = false;
974 mkdebug.off();
975 }
976
977 TechmapWires twd = techmap_find_special_wires(tpl);
978 for (auto &it : twd) {
979 if (it.first.begins_with("\\_TECHMAP_REMOVEINIT_")) {
980 for (auto &it2 : it.second) {
981 auto val = it2.value.as_const();
982 auto wirename = RTLIL::escape_id(it.first.substr(21, it.first.size() - 21 - 1));
983 auto it = cell->connections().find(wirename);
984 if (it != cell->connections().end()) {
985 auto sig = sigmap(it->second);
986 for (int i = 0; i < sig.size(); i++)
987 if (val[i] == State::S1)
988 remove_init_bits.insert(sig[i]);
989 }
990 }
991 }
992 }
993
994 if (extern_mode && !in_recursion)
995 {
996 std::string m_name = stringf("$extern:%s", log_id(tpl));
997
998 if (!design->module(m_name))
999 {
1000 RTLIL::Module *m = design->addModule(m_name);
1001 tpl->cloneInto(m);
1002
1003 for (auto cell : m->cells()) {
1004 if (cell->type.begins_with("\\$"))
1005 cell->type = cell->type.substr(1);
1006 }
1007
1008 module_queue.insert(m);
1009 }
1010
1011 log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name));
1012 cell->type = m_name;
1013 cell->parameters.clear();
1014 }
1015 else
1016 {
1017 auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type));
1018 if (!log_msg_cache.count(msg)) {
1019 log_msg_cache.insert(msg);
1020 log("%s\n", msg.c_str());
1021 }
1022 log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl));
1023 techmap_module_worker(design, module, cell, tpl);
1024 cell = nullptr;
1025 }
1026 did_something = true;
1027 mapped_cell = true;
1028 break;
1029 }
1030
1031 if (assert_mode && !mapped_cell)
1032 log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
1033
1034 handled_cells.insert(cell);
1035 }
1036
1037 if (!remove_init_bits.empty()) {
1038 for (auto wire : module->wires())
1039 if (wire->attributes.count(ID::init)) {
1040 Const &value = wire->attributes.at(ID::init);
1041 bool do_cleanup = true;
1042 for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
1043 SigBit bit = sigmap(SigBit(wire, i));
1044 if (remove_init_bits.count(bit))
1045 value[i] = State::Sx;
1046 else if (value[i] != State::Sx)
1047 do_cleanup = false;
1048 }
1049 if (do_cleanup) {
1050 log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
1051 wire->attributes.erase(ID::init);
1052 }
1053 }
1054 }
1055
1056 if (log_continue) {
1057 log_header(design, "Continuing TECHMAP pass.\n");
1058 log_continue = false;
1059 mkdebug.off();
1060 }
1061
1062 return did_something;
1063 }
1064 };
1065
1066 struct TechmapPass : public Pass {
1067 TechmapPass() : Pass("techmap", "generic technology mapper") { }
1068 void help() YS_OVERRIDE
1069 {
1070 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1071 log("\n");
1072 log(" techmap [-map filename] [selection]\n");
1073 log("\n");
1074 log("This pass implements a very simple technology mapper that replaces cells in\n");
1075 log("the design with implementations given in form of a Verilog or ilang source\n");
1076 log("file.\n");
1077 log("\n");
1078 log(" -map filename\n");
1079 log(" the library of cell implementations to be used.\n");
1080 log(" without this parameter a builtin library is used that\n");
1081 log(" transforms the internal RTL cells to the internal gate\n");
1082 log(" library.\n");
1083 log("\n");
1084 log(" -map %%<design-name>\n");
1085 log(" like -map above, but with an in-memory design instead of a file.\n");
1086 log("\n");
1087 log(" -extern\n");
1088 log(" load the cell implementations as separate modules into the design\n");
1089 log(" instead of inlining them.\n");
1090 log("\n");
1091 log(" -max_iter <number>\n");
1092 log(" only run the specified number of iterations on each module.\n");
1093 log(" default: unlimited\n");
1094 log("\n");
1095 log(" -recursive\n");
1096 log(" instead of the iterative breadth-first algorithm use a recursive\n");
1097 log(" depth-first algorithm. both methods should yield equivalent results,\n");
1098 log(" but may differ in performance.\n");
1099 log("\n");
1100 log(" -autoproc\n");
1101 log(" Automatically call \"proc\" on implementations that contain processes.\n");
1102 log("\n");
1103 log(" -wb\n");
1104 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
1105 log("\n");
1106 log(" -assert\n");
1107 log(" this option will cause techmap to exit with an error if it can't map\n");
1108 log(" a selected cell. only cell types that end on an underscore are accepted\n");
1109 log(" as final cell types by this mode.\n");
1110 log("\n");
1111 log(" -D <define>, -I <incdir>\n");
1112 log(" this options are passed as-is to the Verilog frontend for loading the\n");
1113 log(" map file. Note that the Verilog frontend is also called with the\n");
1114 log(" '-nooverwrite' option set.\n");
1115 log("\n");
1116 log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
1117 log("match cells with a type that match the text value of this attribute. Otherwise\n");
1118 log("the module name will be used to match the cell.\n");
1119 log("\n");
1120 log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
1121 log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
1122 log("\n");
1123 log("When a module in the map file has the 'techmap_maccmap' attribute set, techmap\n");
1124 log("will use 'maccmap' (see 'help maccmap') to map cells matching the module.\n");
1125 log("\n");
1126 log("When a module in the map file has the 'techmap_wrap' attribute set, techmap\n");
1127 log("will create a wrapper for the cell and then run the command string that the\n");
1128 log("attribute is set to on the wrapper module.\n");
1129 log("\n");
1130 log("When a port on a module in the map file has the 'techmap_autopurge' attribute\n");
1131 log("set, and that port is not connected in the instantiation that is mapped, then\n");
1132 log("then a cell port connected only to such wires will be omitted in the mapped\n");
1133 log("version of the circuit.\n");
1134 log("\n");
1135 log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
1136 log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
1137 log("the mapping module to the techmap command. At the moment the following special\n");
1138 log("wires are supported:\n");
1139 log("\n");
1140 log(" _TECHMAP_FAIL_\n");
1141 log(" When this wire is set to a non-zero constant value, techmap will not\n");
1142 log(" use this module and instead try the next module with a matching\n");
1143 log(" 'techmap_celltype' attribute.\n");
1144 log("\n");
1145 log(" When such a wire exists but does not have a constant value after all\n");
1146 log(" _TECHMAP_DO_* commands have been executed, an error is generated.\n");
1147 log("\n");
1148 log(" _TECHMAP_DO_*\n");
1149 log(" This wires are evaluated in alphabetical order. The constant text value\n");
1150 log(" of this wire is a yosys command (or sequence of commands) that is run\n");
1151 log(" by techmap on the module. A common use case is to run 'proc' on modules\n");
1152 log(" that are written using always-statements.\n");
1153 log("\n");
1154 log(" When such a wire has a non-constant value at the time it is to be\n");
1155 log(" evaluated, an error is produced. That means it is possible for such a\n");
1156 log(" wire to start out as non-constant and evaluate to a constant value\n");
1157 log(" during processing of other _TECHMAP_DO_* commands.\n");
1158 log("\n");
1159 log(" A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.\n");
1160 log(" in this case techmap will create a copy for each distinct configuration\n");
1161 log(" of constant inputs and shorted inputs at this point and import the\n");
1162 log(" constant and connected bits into the map module. All further commands\n");
1163 log(" are executed in this copy. This is a very convenient way of creating\n");
1164 log(" optimized specializations of techmap modules without using the special\n");
1165 log(" parameters described below.\n");
1166 log("\n");
1167 log(" A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.\n");
1168 log(" then techmap will recursively replace the cells in the module with their\n");
1169 log(" implementation. This is not affected by the -max_iter option.\n");
1170 log("\n");
1171 log(" It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n");
1172 log("\n");
1173 log(" _TECHMAP_REMOVEINIT_<port-name>_\n");
1174 log(" When this wire is set to a constant value, the init attribute of the wire(s)\n");
1175 log(" connected to this port will be consumed. This wire must have the same\n");
1176 log(" width as the given port, and for every bit that is set to 1 in the value,\n");
1177 log(" the corresponding init attribute bit will be changed to 1'bx. If all\n");
1178 log(" bits of an init attribute are left as x, it will be removed.\n");
1179 log("\n");
1180 log("In addition to this special wires, techmap also supports special parameters in\n");
1181 log("modules in the map file:\n");
1182 log("\n");
1183 log(" _TECHMAP_CELLTYPE_\n");
1184 log(" When a parameter with this name exists, it will be set to the type name\n");
1185 log(" of the cell that matches the module.\n");
1186 log("\n");
1187 log(" _TECHMAP_CONSTMSK_<port-name>_\n");
1188 log(" _TECHMAP_CONSTVAL_<port-name>_\n");
1189 log(" When this pair of parameters is available in a module for a port, then\n");
1190 log(" former has a 1-bit for each constant input bit and the latter has the\n");
1191 log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
1192 log("\n");
1193 log(" _TECHMAP_WIREINIT_<port-name>_\n");
1194 log(" When a parameter with this name exists, it will be set to the initial\n");
1195 log(" value of the wire(s) connected to the given port, as specified by the init\n");
1196 log(" attribute. If the attribute doesn't exist, x will be filled for the\n");
1197 log(" missing bits. To remove the init attribute bits used, use the\n");
1198 log(" _TECHMAP_REMOVEINIT_*_ wires.\n");
1199 log("\n");
1200 log(" _TECHMAP_BITS_CONNMAP_\n");
1201 log(" _TECHMAP_CONNMAP_<port-name>_\n");
1202 log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
1203 log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n");
1204 log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n");
1205 log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n");
1206 log(" This can be used to detect shorted inputs.\n");
1207 log("\n");
1208 log("When a module in the map file has a parameter where the according cell in the\n");
1209 log("design has a port, the module from the map file is only used if the port in\n");
1210 log("the design is connected to a constant value. The parameter is then set to the\n");
1211 log("constant value.\n");
1212 log("\n");
1213 log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
1214 log("and attributes of the cell that is being replaced.\n");
1215 log("A cell with a name of the form `_TECHMAP_REPLACE_.<suffix>` in the map file will\n");
1216 log("be named thus but with the `_TECHMAP_REPLACE_' prefix substituted with the name\n");
1217 log("of the cell being replaced.\n");
1218 log("Similarly, a wire named in the form `_TECHMAP_REPLACE_.<suffix>` will cause a\n");
1219 log("new wire alias to be created and named as above but with the `_TECHMAP_REPLACE_'\n");
1220 log("prefix also substituted.\n");
1221 log("\n");
1222 log("See 'help extract' for a pass that does the opposite thing.\n");
1223 log("\n");
1224 log("See 'help flatten' for a pass that does flatten the design (which is\n");
1225 log("essentially techmap but using the design itself as map library).\n");
1226 log("\n");
1227 }
1228 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1229 {
1230 log_header(design, "Executing TECHMAP pass (map to technology primitives).\n");
1231 log_push();
1232
1233 TechmapWorker worker;
1234 simplemap_get_mappers(worker.simplemap_mappers);
1235
1236 std::vector<std::string> map_files;
1237 std::string verilog_frontend = "verilog -nooverwrite -noblackbox";
1238 int max_iter = -1;
1239
1240 size_t argidx;
1241 for (argidx = 1; argidx < args.size(); argidx++) {
1242 if (args[argidx] == "-map" && argidx+1 < args.size()) {
1243 map_files.push_back(args[++argidx]);
1244 continue;
1245 }
1246 if (args[argidx] == "-max_iter" && argidx+1 < args.size()) {
1247 max_iter = atoi(args[++argidx].c_str());
1248 continue;
1249 }
1250 if (args[argidx] == "-D" && argidx+1 < args.size()) {
1251 verilog_frontend += " -D " + args[++argidx];
1252 continue;
1253 }
1254 if (args[argidx] == "-I" && argidx+1 < args.size()) {
1255 verilog_frontend += " -I " + args[++argidx];
1256 continue;
1257 }
1258 if (args[argidx] == "-assert") {
1259 worker.assert_mode = true;
1260 continue;
1261 }
1262 if (args[argidx] == "-extern") {
1263 worker.extern_mode = true;
1264 continue;
1265 }
1266 if (args[argidx] == "-recursive") {
1267 worker.recursive_mode = true;
1268 continue;
1269 }
1270 if (args[argidx] == "-autoproc") {
1271 worker.autoproc_mode = true;
1272 continue;
1273 }
1274 if (args[argidx] == "-wb") {
1275 worker.ignore_wb = true;
1276 continue;
1277 }
1278 break;
1279 }
1280 extra_args(args, argidx, design);
1281
1282 RTLIL::Design *map = new RTLIL::Design;
1283 if (map_files.empty()) {
1284 Frontend::frontend_call(map, nullptr, "+/techmap.v", verilog_frontend);
1285 } else {
1286 for (auto &fn : map_files)
1287 if (fn.compare(0, 1, "%") == 0) {
1288 if (!saved_designs.count(fn.substr(1))) {
1289 delete map;
1290 log_cmd_error("Can't open saved design `%s'.\n", fn.c_str()+1);
1291 }
1292 for (auto mod : saved_designs.at(fn.substr(1))->modules())
1293 if (!map->module(mod->name))
1294 map->add(mod->clone());
1295 } else {
1296 Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend));
1297 }
1298 }
1299
1300 log_header(design, "Continuing TECHMAP pass.\n");
1301
1302 dict<IdString, pool<IdString>> celltypeMap;
1303 for (auto module : map->modules()) {
1304 if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).bits.empty()) {
1305 char *p = strdup(module->attributes.at(ID::techmap_celltype).decode_string().c_str());
1306 for (char *q = strtok(p, " \t\r\n"); q; q = strtok(nullptr, " \t\r\n"))
1307 celltypeMap[RTLIL::escape_id(q)].insert(module->name);
1308 free(p);
1309 } else {
1310 IdString module_name = module->name.begins_with("\\$") ?
1311 module->name.substr(1) : module->name.str();
1312 celltypeMap[module_name].insert(module->name);
1313 }
1314 }
1315 for (auto &i : celltypeMap)
1316 i.second.sort(RTLIL::sort_by_id_str());
1317
1318 for (auto module : design->modules())
1319 worker.module_queue.insert(module);
1320
1321 while (!worker.module_queue.empty())
1322 {
1323 RTLIL::Module *module = *worker.module_queue.begin();
1324 worker.module_queue.erase(module);
1325
1326 int module_max_iter = max_iter;
1327 bool did_something = true;
1328 pool<RTLIL::Cell*> handled_cells;
1329 while (did_something) {
1330 did_something = false;
1331 if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
1332 did_something = true;
1333 if (did_something)
1334 module->check();
1335 if (module_max_iter > 0 && --module_max_iter == 0)
1336 break;
1337 }
1338 }
1339
1340 log("No more expansions possible.\n");
1341 delete map;
1342
1343 log_pop();
1344 }
1345 } TechmapPass;
1346
1347 struct FlattenPass : public Pass {
1348 FlattenPass() : Pass("flatten", "flatten design") { }
1349 void help() YS_OVERRIDE
1350 {
1351 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1352 log("\n");
1353 log(" flatten [options] [selection]\n");
1354 log("\n");
1355 log("This pass flattens the design by replacing cells by their implementation. This\n");
1356 log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
1357 log("pass is using the current design as mapping library.\n");
1358 log("\n");
1359 log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
1360 log("flattened by this command.\n");
1361 log("\n");
1362 log(" -wb\n");
1363 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
1364 log("\n");
1365 }
1366 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1367 {
1368 log_header(design, "Executing FLATTEN pass (flatten design).\n");
1369 log_push();
1370
1371 TechmapWorker worker;
1372 worker.flatten_mode = true;
1373
1374 size_t argidx;
1375 for (argidx = 1; argidx < args.size(); argidx++) {
1376 if (args[argidx] == "-wb") {
1377 worker.ignore_wb = true;
1378 continue;
1379 }
1380 break;
1381 }
1382 extra_args(args, argidx, design);
1383
1384
1385 dict<IdString, pool<IdString>> celltypeMap;
1386 for (auto module : design->modules())
1387 celltypeMap[module->name].insert(module->name);
1388 for (auto &i : celltypeMap)
1389 i.second.sort(RTLIL::sort_by_id_str());
1390
1391 RTLIL::Module *top_mod = nullptr;
1392 if (design->full_selection())
1393 for (auto mod : design->modules())
1394 if (mod->get_bool_attribute(ID::top))
1395 top_mod = mod;
1396
1397 pool<RTLIL::Cell*> handled_cells;
1398 if (top_mod != nullptr) {
1399 worker.flatten_do_list.insert(top_mod->name);
1400 while (!worker.flatten_do_list.empty()) {
1401 auto mod = design->module(*worker.flatten_do_list.begin());
1402 while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
1403 worker.flatten_done_list.insert(mod->name);
1404 worker.flatten_do_list.erase(mod->name);
1405 }
1406 } else {
1407 for (auto mod : design->modules().to_vector())
1408 while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
1409 }
1410
1411 log_suppressed();
1412 log("No more expansions possible.\n");
1413
1414 if (top_mod != nullptr)
1415 {
1416 pool<IdString> used_modules, new_used_modules;
1417 new_used_modules.insert(top_mod->name);
1418 while (!new_used_modules.empty()) {
1419 pool<IdString> queue;
1420 queue.swap(new_used_modules);
1421 for (auto modname : queue)
1422 used_modules.insert(modname);
1423 for (auto modname : queue)
1424 for (auto cell : design->module(modname)->cells())
1425 if (design->module(cell->type) && !used_modules[cell->type])
1426 new_used_modules.insert(cell->type);
1427 }
1428
1429 for (auto mod : design->modules().to_vector())
1430 if (!used_modules[mod->name] && !mod->get_blackbox_attribute(worker.ignore_wb)) {
1431 log("Deleting now unused module %s.\n", log_id(mod));
1432 design->remove(mod);
1433 }
1434 }
1435
1436 log_pop();
1437 }
1438 } FlattenPass;
1439
1440 PRIVATE_NAMESPACE_END