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be more verbose when techmap yielded processes
[yosys.git] / passes / techmap / techmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/compatibility.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/log.h"
24 #include <stdlib.h>
25 #include <assert.h>
26 #include <stdio.h>
27 #include <string.h>
28
29 #include "passes/techmap/stdcells.inc"
30
31 // see simplemap.cc
32 extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
33
34 static void apply_prefix(std::string prefix, std::string &id)
35 {
36 if (id[0] == '\\')
37 id = prefix + "." + id.substr(1);
38 else
39 id = "$techmap" + prefix + "." + id;
40 }
41
42 static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
43 {
44 for (size_t i = 0; i < sig.chunks.size(); i++) {
45 if (sig.chunks[i].wire == NULL)
46 continue;
47 std::string wire_name = sig.chunks[i].wire->name;
48 apply_prefix(prefix, wire_name);
49 assert(module->wires.count(wire_name) > 0);
50 sig.chunks[i].wire = module->wires[wire_name];
51 }
52 }
53
54 struct TechmapWorker
55 {
56 std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
57 std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
58 std::map<RTLIL::Module*, bool> techmap_do_cache;
59
60 struct TechmapWireData {
61 RTLIL::Wire *wire;
62 RTLIL::SigSpec value;
63 };
64
65 typedef std::map<std::string, std::vector<TechmapWireData>> TechmapWires;
66
67 TechmapWires techmap_find_special_wires(RTLIL::Module *module)
68 {
69 TechmapWires result;
70
71 if (module == NULL)
72 return result;
73
74 for (auto &it : module->wires) {
75 const char *p = it.first.c_str();
76 if (*p == '$')
77 continue;
78
79 const char *q = strrchr(p+1, '.');
80 p = q ? q : p+1;
81
82 if (!strncmp(p, "_TECHMAP_", 9)) {
83 TechmapWireData record;
84 record.wire = it.second;
85 record.value = it.second;
86 result[p].push_back(record);
87 it.second->attributes["\\keep"] = RTLIL::Const(1);
88 it.second->attributes["\\_techmap_special_"] = RTLIL::Const(1);
89 }
90 }
91
92 if (!result.empty()) {
93 SigMap sigmap(module);
94 for (auto &it1 : result)
95 for (auto &it2 : it1.second)
96 sigmap.apply(it2.value);
97 }
98
99 return result;
100 }
101
102 void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, bool flatten_mode)
103 {
104 log("Mapping `%s.%s' using `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(tpl->name));
105
106 if (tpl->memories.size() != 0)
107 log_error("Technology map yielded memories -> this is not supported.\n");
108
109 if (tpl->processes.size() != 0) {
110 log("Technology map yielded processes:\n");
111 for (auto &it : tpl->processes)
112 log(" %s",RTLIL::id2cstr(it.first));
113 log_error("Technology map yielded processes -> this is not supported.\n");
114 }
115
116 // erase from namespace first for _TECHMAP_REPLACE_ to work
117 module->cells.erase(cell->name);
118 std::string orig_cell_name;
119
120 if (!flatten_mode)
121 for (auto &it : tpl->cells)
122 if (it.first == "\\_TECHMAP_REPLACE_") {
123 orig_cell_name = cell->name;
124 cell->name = stringf("$techmap%d", RTLIL::autoidx++) + cell->name;
125 break;
126 }
127
128 std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
129
130 for (auto &it : tpl->wires) {
131 if (it.second->port_id > 0)
132 positional_ports[stringf("$%d", it.second->port_id)] = it.first;
133 RTLIL::Wire *w = new RTLIL::Wire(*it.second);
134 apply_prefix(cell->name, w->name);
135 w->port_input = false;
136 w->port_output = false;
137 w->port_id = 0;
138 if (it.second->get_bool_attribute("\\_techmap_special_"))
139 w->attributes.clear();
140 module->add(w);
141 design->select(module, w);
142 }
143
144 SigMap port_signal_map;
145
146 for (auto &it : cell->connections) {
147 RTLIL::IdString portname = it.first;
148 if (positional_ports.count(portname) > 0)
149 portname = positional_ports.at(portname);
150 if (tpl->wires.count(portname) == 0 || tpl->wires.at(portname)->port_id == 0) {
151 if (portname.substr(0, 1) == "$")
152 log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
153 continue;
154 }
155 RTLIL::Wire *w = tpl->wires.at(portname);
156 RTLIL::SigSig c;
157 if (w->port_output) {
158 c.first = it.second;
159 c.second = RTLIL::SigSpec(w);
160 apply_prefix(cell->name, c.second, module);
161 } else {
162 c.first = RTLIL::SigSpec(w);
163 c.second = it.second;
164 apply_prefix(cell->name, c.first, module);
165 }
166 if (c.second.width > c.first.width)
167 c.second.remove(c.first.width, c.second.width - c.first.width);
168 if (c.second.width < c.first.width)
169 c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.width - c.second.width));
170 assert(c.first.width == c.second.width);
171 if (flatten_mode) {
172 // more conservative approach:
173 // connect internal and external wires
174 module->connections.push_back(c);
175 } else {
176 // approach that yields nicer outputs:
177 // replace internal wires that are connected to external wires
178 if (w->port_output)
179 port_signal_map.add(c.second, c.first);
180 else
181 port_signal_map.add(c.first, c.second);
182 }
183 }
184
185 for (auto &it : tpl->cells) {
186 RTLIL::Cell *c = new RTLIL::Cell(*it.second);
187 if (!flatten_mode && c->type.substr(0, 2) == "\\$")
188 c->type = c->type.substr(1);
189 if (!flatten_mode && c->name == "\\_TECHMAP_REPLACE_")
190 c->name = orig_cell_name;
191 else
192 apply_prefix(cell->name, c->name);
193 for (auto &it2 : c->connections) {
194 apply_prefix(cell->name, it2.second, module);
195 port_signal_map.apply(it2.second);
196 }
197 module->add(c);
198 design->select(module, c);
199 }
200
201 for (auto &it : tpl->connections) {
202 RTLIL::SigSig c = it;
203 apply_prefix(cell->name, c.first, module);
204 apply_prefix(cell->name, c.second, module);
205 port_signal_map.apply(c.first);
206 port_signal_map.apply(c.second);
207 module->connections.push_back(c);
208 }
209
210 delete cell;
211 }
212
213 bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
214 const std::map<RTLIL::IdString, std::set<RTLIL::IdString>> &celltypeMap, bool flatten_mode)
215 {
216 if (!design->selected(module))
217 return false;
218
219 bool log_continue = false;
220 bool did_something = false;
221 std::vector<std::string> cell_names;
222
223 SigMap sigmap(module);
224 for (auto &cell_it : module->cells)
225 cell_names.push_back(cell_it.first);
226
227 for (auto &cell_name : cell_names)
228 {
229 if (module->cells.count(cell_name) == 0)
230 continue;
231
232 RTLIL::Cell *cell = module->cells[cell_name];
233
234 if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
235 continue;
236
237 if (celltypeMap.count(cell->type) == 0)
238 continue;
239
240 for (auto &tpl_name : celltypeMap.at(cell->type))
241 {
242 std::string derived_name = tpl_name;
243 RTLIL::Module *tpl = map->modules[tpl_name];
244 std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters;
245
246 if (!flatten_mode)
247 {
248 if (tpl->get_bool_attribute("\\techmap_simplemap")) {
249 log("Mapping %s.%s (%s) with simplemap.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
250 if (simplemap_mappers.count(cell->type) == 0)
251 log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
252 simplemap_mappers.at(cell->type)(module, cell);
253 module->cells.erase(cell->name);
254 delete cell;
255 cell = NULL;
256 did_something = true;
257 break;
258 }
259
260 for (auto conn : cell->connections) {
261 if (conn.first.substr(0, 1) == "$")
262 continue;
263 if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0)
264 continue;
265 if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
266 goto next_tpl;
267 parameters[conn.first] = conn.second.as_const();
268 }
269
270 if (0) {
271 next_tpl:
272 continue;
273 }
274
275 if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0)
276 parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type);
277
278 for (auto conn : cell->connections) {
279 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
280 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
281 for (auto &bit : v)
282 bit = RTLIL::SigBit(bit.wire == NULL ? RTLIL::State::S1 : RTLIL::State::S0);
283 parameters[stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
284 }
285 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))) != 0) {
286 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
287 for (auto &bit : v)
288 if (bit.wire != NULL)
289 bit = RTLIL::SigBit(RTLIL::State::Sx);
290 parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
291 }
292 }
293
294 int unique_bit_id_counter = 0;
295 std::map<RTLIL::SigBit, int> unique_bit_id;
296 unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++;
297 unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++;
298 unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++;
299 unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
300
301 for (auto conn : cell->connections)
302 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
303 for (auto &bit : sigmap(conn.second).to_sigbit_vector())
304 if (unique_bit_id.count(bit) == 0)
305 unique_bit_id[bit] = unique_bit_id_counter++;
306 }
307
308 int bits = 0;
309 for (int i = 0; i < 32; i++)
310 if (((unique_bit_id_counter-1) & (1 << i)) != 0)
311 bits = i;
312 if (tpl->avail_parameters.count("\\_TECHMAP_BITS_CONNMAP_"))
313 parameters["\\_TECHMAP_BITS_CONNMAP_"] = bits;
314
315 for (auto conn : cell->connections)
316 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
317 RTLIL::Const value;
318 for (auto &bit : sigmap(conn.second).to_sigbit_vector()) {
319 RTLIL::Const chunk(unique_bit_id.at(bit), bits);
320 value.bits.insert(value.bits.end(), chunk.bits.begin(), chunk.bits.end());
321 }
322 parameters[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))] = value;
323 }
324 }
325
326 std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
327 if (techmap_cache.count(key) > 0) {
328 tpl = techmap_cache[key];
329 } else {
330 if (cell->parameters.size() != 0) {
331 derived_name = tpl->derive(map, parameters);
332 tpl = map->modules[derived_name];
333 log_continue = true;
334 }
335 techmap_cache[key] = tpl;
336 }
337
338 if (flatten_mode)
339 techmap_do_cache[tpl] = true;
340
341 if (techmap_do_cache.count(tpl) == 0)
342 {
343 bool keep_running = true;
344 techmap_do_cache[tpl] = true;
345
346 std::set<std::string> techmap_wire_names;
347
348 while (keep_running)
349 {
350 TechmapWires twd = techmap_find_special_wires(tpl);
351 keep_running = false;
352
353 for (auto &it : twd)
354 techmap_wire_names.insert(it.first);
355
356 for (auto &it : twd["_TECHMAP_FAIL_"]) {
357 RTLIL::SigSpec value = it.value;
358 if (value.is_fully_const() && value.as_bool()) {
359 log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
360 derived_name.c_str(), RTLIL::id2cstr(it.wire->name), log_signal(value));
361 techmap_do_cache[tpl] = false;
362 }
363 }
364
365 if (!techmap_do_cache[tpl])
366 break;
367
368 for (auto &it : twd)
369 {
370 if (it.first.substr(0, 12) != "_TECHMAP_DO_" || it.second.empty())
371 continue;
372
373 auto &data = it.second.front();
374
375 if (!data.value.is_fully_const())
376 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));
377
378 techmap_wire_names.erase(it.first);
379 tpl->wires.erase(data.wire->name);
380
381 const char *p = data.wire->name.c_str();
382 const char *q = strrchr(p+1, '.');
383 q = q ? q : p+1;
384
385 assert(!strncmp(q, "_TECHMAP_DO_", 12));
386 std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
387 while (tpl->wires.count(new_name))
388 new_name += "_";
389 data.wire->name = new_name;
390 tpl->add(data.wire);
391
392 std::string cmd_string = data.value.as_const().decode_string();
393
394 RTLIL::Selection tpl_mod_sel(false);
395 std::string backup_active_module = map->selected_active_module;
396 map->selected_active_module = tpl->name;
397 tpl_mod_sel.select(tpl);
398 map->selection_stack.push_back(tpl_mod_sel);
399 Pass::call(map, cmd_string);
400 map->selection_stack.pop_back();
401 map->selected_active_module = backup_active_module;
402
403 keep_running = true;
404 break;
405 }
406 }
407
408 TechmapWires twd = techmap_find_special_wires(tpl);
409 for (auto &it : twd) {
410 if (it.first != "_TECHMAP_FAIL_" && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
411 log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str());
412 if (techmap_do_cache[tpl])
413 for (auto &it2 : it.second)
414 if (!it2.value.is_fully_const())
415 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
416 techmap_wire_names.erase(it.first);
417 }
418
419 for (auto &it : techmap_wire_names)
420 log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it));
421 }
422
423 if (techmap_do_cache.at(tpl) == false)
424 continue;
425
426 if (log_continue) {
427 log_header("Continuing TECHMAP pass.\n");
428 log_continue = false;
429 }
430
431 techmap_module_worker(design, module, cell, tpl, flatten_mode);
432 did_something = true;
433 cell = NULL;
434 break;
435 }
436
437 handled_cells.insert(cell);
438 }
439
440 if (log_continue) {
441 log_header("Continuing TECHMAP pass.\n");
442 log_continue = false;
443 }
444
445 return did_something;
446 }
447 };
448
449 struct TechmapPass : public Pass {
450 TechmapPass() : Pass("techmap", "generic technology mapper") { }
451 virtual void help()
452 {
453 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
454 log("\n");
455 log(" techmap [-map filename] [selection]\n");
456 log("\n");
457 log("This pass implements a very simple technology mapper that replaces cells in\n");
458 log("the design with implementations given in form of a verilog or ilang source\n");
459 log("file.\n");
460 log("\n");
461 log(" -map filename\n");
462 log(" the library of cell implementations to be used.\n");
463 log(" without this parameter a builtin library is used that\n");
464 log(" transforms the internal RTL cells to the internal gate\n");
465 log(" library.\n");
466 log("\n");
467 log(" -share_map filename\n");
468 log(" like -map, but look for the file in the share directory (where the\n");
469 log(" yosys data files are). this is mainly used internally when techmap\n");
470 log(" is called from other commands.\n");
471 log("\n");
472 log(" -max_iter <number>\n");
473 log(" only run the specified number of iterations.\n");
474 log("\n");
475 log(" -D <define>, -I <incdir>\n");
476 log(" this options are passed as-is to the verilog frontend for loading the\n");
477 log(" map file. Note that the verilog frontend is also called with the\n");
478 log(" '-ignore_redef' option set.\n");
479 log("\n");
480 log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
481 log("match cells with a type that match the text value of this attribute. Otherwise\n");
482 log("the module name will be used to match the cell.\n");
483 log("\n");
484 log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
485 log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
486 log("\n");
487 log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
488 log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
489 log("the mapping module to the techmap command. At the moment the following special\n");
490 log("wires are supported:\n");
491 log("\n");
492 log(" _TECHMAP_FAIL_\n");
493 log(" When this wire is set to a non-zero constant value, techmap will not\n");
494 log(" use this module and instead try the next module with a matching\n");
495 log(" 'techmap_celltype' attribute.\n");
496 log("\n");
497 log(" When such a wire exists but does not have a constant value after all\n");
498 log(" _TECHMAP_DO_* commands have been executed, an error is generated.\n");
499 log("\n");
500 log(" _TECHMAP_DO_*\n");
501 log(" This wires are evaluated in alphabetical order. The constant text value\n");
502 log(" of this wire is a yosys command (or sequence of commands) that is run\n");
503 log(" by techmap on the module. A common use case is to run 'proc' on modules\n");
504 log(" that are written using always-statements.\n");
505 log("\n");
506 log(" When such a wire has a non-constant value at the time it is to be\n");
507 log(" evaluated, an error is produced. That means it is possible for such a\n");
508 log(" wire to start out as non-constant and evaluate to a constant value\n");
509 log(" during processing of other _TECHMAP_DO_* commands.\n");
510 log("\n");
511 log("In addition to this special wires, techmap also supports special parameters in\n");
512 log("modules in the map file:\n");
513 log("\n");
514 log(" _TECHMAP_CELLTYPE_\n");
515 log(" When a parameter with this name exists, it will be set to the type name\n");
516 log(" of the cell that matches the module.\n");
517 log("\n");
518 log(" _TECHMAP_CONSTMSK_<port-name>_\n");
519 log(" _TECHMAP_CONSTVAL_<port-name>_\n");
520 log(" When this pair of parameters is available in a module for a port, then\n");
521 log(" former has a 1-bit for each constant input bit and the latter has the\n");
522 log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
523 log("\n");
524 log(" _TECHMAP_BITS_CONNMAP_\n");
525 log(" _TECHMAP_CONNMAP_<port-name>_\n");
526 log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
527 log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n");
528 log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n");
529 log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n");
530 log(" This can be used to detect shorted inputs.\n");
531 log("\n");
532 log("When a module in the map file has a parameter where the according cell in the\n");
533 log("design has a port, the module from the map file is only used if the port in\n");
534 log("the design is connected to a constant value. The parameter is then set to the\n");
535 log("constant value.\n");
536 log("\n");
537 log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
538 log("of the cell that is beeing replaced.\n");
539 log("\n");
540 log("See 'help extract' for a pass that does the opposite thing.\n");
541 log("\n");
542 log("See 'help flatten' for a pass that does flatten the design (which is\n");
543 log("esentially techmap but using the design itself as map library).\n");
544 log("\n");
545 }
546 virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
547 {
548 log_header("Executing TECHMAP pass (map to technology primitives).\n");
549 log_push();
550
551 std::vector<std::string> map_files;
552 std::string verilog_frontend = "verilog -ignore_redef";
553 int max_iter = -1;
554
555 size_t argidx;
556 std::string proc_share_path = proc_share_dirname();
557 for (argidx = 1; argidx < args.size(); argidx++) {
558 if (args[argidx] == "-map" && argidx+1 < args.size()) {
559 map_files.push_back(args[++argidx]);
560 continue;
561 }
562 if (args[argidx] == "-share_map" && argidx+1 < args.size()) {
563 map_files.push_back(proc_share_path + args[++argidx]);
564 continue;
565 }
566 if (args[argidx] == "-max_iter" && argidx+1 < args.size()) {
567 max_iter = atoi(args[++argidx].c_str());
568 continue;
569 }
570 if (args[argidx] == "-D" && argidx+1 < args.size()) {
571 verilog_frontend += " -D " + args[++argidx];
572 continue;
573 }
574 if (args[argidx] == "-I" && argidx+1 < args.size()) {
575 verilog_frontend += " -I " + args[++argidx];
576 continue;
577 }
578 break;
579 }
580 extra_args(args, argidx, design);
581
582 TechmapWorker worker;
583 simplemap_get_mappers(worker.simplemap_mappers);
584
585 RTLIL::Design *map = new RTLIL::Design;
586 if (map_files.empty()) {
587 FILE *f = fmemopen(stdcells_code, strlen(stdcells_code), "rt");
588 Frontend::frontend_call(map, f, "<stdcells.v>", verilog_frontend);
589 fclose(f);
590 } else
591 for (auto &fn : map_files) {
592 FILE *f = fopen(fn.c_str(), "rt");
593 if (f == NULL)
594 log_cmd_error("Can't open map file `%s'\n", fn.c_str());
595 Frontend::frontend_call(map, f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend);
596 fclose(f);
597 }
598
599 std::map<RTLIL::IdString, RTLIL::Module*> modules_new;
600 for (auto &it : map->modules) {
601 if (it.first.substr(0, 2) == "\\$")
602 it.second->name = it.first.substr(1);
603 modules_new[it.second->name] = it.second;
604 }
605 map->modules.swap(modules_new);
606
607 std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
608 for (auto &it : map->modules) {
609 if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) {
610 char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str());
611 for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
612 celltypeMap[RTLIL::escape_id(q)].insert(it.first);
613 free(p);
614 } else
615 celltypeMap[it.first].insert(it.first);
616 }
617
618 bool did_something = true;
619 std::set<RTLIL::Cell*> handled_cells;
620 while (did_something) {
621 did_something = false;
622 for (auto &mod_it : design->modules)
623 if (worker.techmap_module(design, mod_it.second, map, handled_cells, celltypeMap, false))
624 did_something = true;
625 if (did_something)
626 design->check();
627 if (max_iter > 0 && --max_iter == 0)
628 break;
629 }
630
631 log("No more expansions possible.\n");
632 delete map;
633
634 log_pop();
635 }
636 } TechmapPass;
637
638 struct FlattenPass : public Pass {
639 FlattenPass() : Pass("flatten", "flatten design") { }
640 virtual void help()
641 {
642 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
643 log("\n");
644 log(" flatten [selection]\n");
645 log("\n");
646 log("This pass flattens the design by replacing cells by their implementation. This\n");
647 log("pass is very simmilar to the 'techmap' pass. The only difference is that this\n");
648 log("pass is using the current design as mapping library.\n");
649 log("\n");
650 }
651 virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
652 {
653 log_header("Executing FLATTEN pass (flatten design).\n");
654 log_push();
655
656 extra_args(args, 1, design);
657
658 TechmapWorker worker;
659
660 std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
661 for (auto &it : design->modules)
662 celltypeMap[it.first].insert(it.first);
663
664 RTLIL::Module *top_mod = NULL;
665 if (design->full_selection())
666 for (auto &mod_it : design->modules)
667 if (mod_it.second->get_bool_attribute("\\top"))
668 top_mod = mod_it.second;
669
670 bool did_something = true;
671 std::set<RTLIL::Cell*> handled_cells;
672 while (did_something) {
673 did_something = false;
674 if (top_mod != NULL) {
675 if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true))
676 did_something = true;
677 } else {
678 for (auto &mod_it : design->modules)
679 if (worker.techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true))
680 did_something = true;
681 }
682 }
683
684 log("No more expansions possible.\n");
685
686 if (top_mod != NULL) {
687 std::map<RTLIL::IdString, RTLIL::Module*> new_modules;
688 for (auto &mod_it : design->modules)
689 if (mod_it.second == top_mod) {
690 new_modules[mod_it.first] = mod_it.second;
691 } else {
692 log("Deleting now unused module %s.\n", RTLIL::id2cstr(mod_it.first));
693 delete mod_it.second;
694 }
695 design->modules.swap(new_modules);
696 }
697
698 log_pop();
699 }
700 } FlattenPass;
701