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9227385b37a18f87bce20d3a3c7d70b6f87fa4a5
[yosys.git] / passes / techmap / techmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/utils.h"
22 #include "kernel/sigtools.h"
23 #include "libs/sha1/sha1.h"
24
25 #include <stdlib.h>
26 #include <stdio.h>
27 #include <string.h>
28
29 #include "simplemap.h"
30
31 YOSYS_NAMESPACE_BEGIN
32
33 // see maccmap.cc
34 extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false);
35
36 YOSYS_NAMESPACE_END
37
38 USING_YOSYS_NAMESPACE
39 PRIVATE_NAMESPACE_BEGIN
40
41 void apply_prefix(IdString prefix, IdString &id)
42 {
43 if (id[0] == '\\')
44 id = stringf("%s.%s", prefix.c_str(), id.c_str()+1);
45 else
46 id = stringf("$techmap%s.%s", prefix.c_str(), id.c_str());
47 }
48
49 void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
50 {
51 vector<SigChunk> chunks = sig;
52 for (auto &chunk : chunks)
53 if (chunk.wire != nullptr) {
54 IdString wire_name = chunk.wire->name;
55 apply_prefix(prefix, wire_name);
56 log_assert(module->wire(wire_name) != nullptr);
57 chunk.wire = module->wire(wire_name);
58 }
59 sig = chunks;
60 }
61
62 struct TechmapWorker
63 {
64 dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
65 dict<std::pair<IdString, dict<IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
66 dict<RTLIL::Module*, bool> techmap_do_cache;
67 pool<RTLIL::Module*> module_queue;
68 dict<Module*, SigMap> sigmaps;
69
70 pool<IdString> flatten_do_list;
71 pool<IdString> flatten_done_list;
72 pool<Cell*> flatten_keep_list;
73
74 pool<string> log_msg_cache;
75
76 struct TechmapWireData {
77 RTLIL::Wire *wire;
78 RTLIL::SigSpec value;
79 };
80
81 typedef dict<IdString, std::vector<TechmapWireData>> TechmapWires;
82
83 bool extern_mode = false;
84 bool assert_mode = false;
85 bool flatten_mode = false;
86 bool recursive_mode = false;
87 bool autoproc_mode = false;
88 bool ignore_wb = false;
89
90 std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose)
91 {
92 std::string constmap_info;
93 dict<RTLIL::SigBit, std::pair<IdString, int>> connbits_map;
94
95 for (auto &conn : cell->connections())
96 for (int i = 0; i < GetSize(conn.second); i++) {
97 RTLIL::SigBit bit = sigmap(conn.second[i]);
98 if (bit.wire == nullptr) {
99 if (verbose)
100 log(" Constant input on bit %d of port %s: %s\n", i, log_id(conn.first), log_signal(bit));
101 constmap_info += stringf("|%s %d %d", log_id(conn.first), i, bit.data);
102 } else if (connbits_map.count(bit)) {
103 if (verbose)
104 log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, log_id(conn.first),
105 connbits_map.at(bit).second, log_id(connbits_map.at(bit).first));
106 constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i,
107 log_id(connbits_map.at(bit).first), connbits_map.at(bit).second);
108 } else {
109 connbits_map.emplace(bit, std::make_pair(conn.first, i));
110 constmap_info += stringf("|%s %d", log_id(conn.first), i);
111 }
112 }
113
114 return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str());
115 }
116
117 TechmapWires techmap_find_special_wires(RTLIL::Module *module)
118 {
119 TechmapWires result;
120
121 if (module == nullptr)
122 return result;
123
124 for (auto w : module->wires()) {
125 const char *p = w->name.c_str();
126 if (*p == '$')
127 continue;
128
129 const char *q = strrchr(p+1, '.');
130 if (q)
131 p = q;
132
133 if (!strncmp(p, "\\_TECHMAP_", 10)) {
134 TechmapWireData record;
135 record.wire = w;
136 record.value = w;
137 result[p].push_back(record);
138 w->set_bool_attribute(ID::keep);
139 w->set_bool_attribute(ID::_techmap_special_);
140 }
141 }
142
143 if (!result.empty()) {
144 SigMap sigmap(module);
145 for (auto &it1 : result)
146 for (auto &it2 : it1.second)
147 sigmap.apply(it2.value);
148 }
149
150 return result;
151 }
152
153 void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl)
154 {
155 if (tpl->processes.size() != 0) {
156 log("Technology map yielded processes:");
157 for (auto &it : tpl->processes)
158 log(" %s",log_id(it.first));
159 log("\n");
160 if (autoproc_mode) {
161 Pass::call_on_module(tpl->design, tpl, "proc");
162 log_assert(GetSize(tpl->processes) == 0);
163 } else
164 log_error("Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).\n");
165 }
166
167 std::string orig_cell_name;
168 pool<string> extra_src_attrs = cell->get_strpool_attribute(ID::src);
169
170 orig_cell_name = cell->name.str();
171 if (!flatten_mode) {
172 for (auto tpl_cell : tpl->cells())
173 if (tpl_cell->name == ID::_TECHMAP_REPLACE_) {
174 module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
175 break;
176 }
177 }
178
179 dict<IdString, IdString> memory_renames;
180
181 for (auto &it : tpl->memories) {
182 IdString m_name = it.first;
183 apply_prefix(cell->name, m_name);
184 RTLIL::Memory *m = new RTLIL::Memory;
185 m->name = m_name;
186 m->width = it.second->width;
187 m->start_offset = it.second->start_offset;
188 m->size = it.second->size;
189 m->attributes = it.second->attributes;
190 if (m->attributes.count(ID::src))
191 m->add_strpool_attribute(ID::src, extra_src_attrs);
192 module->memories[m->name] = m;
193 memory_renames[it.first] = m->name;
194 design->select(module, m);
195 }
196
197 dict<IdString, IdString> positional_ports;
198 dict<Wire*, IdString> temp_renamed_wires;
199 pool<SigBit> autopurge_tpl_bits;
200
201 for (auto tpl_w : tpl->wires())
202 {
203 if (tpl_w->port_id > 0)
204 {
205 IdString posportname = stringf("$%d", tpl_w->port_id);
206 positional_ports.emplace(posportname, tpl_w->name);
207
208 if (!flatten_mode && tpl_w->get_bool_attribute(ID::techmap_autopurge) &&
209 (!cell->hasPort(tpl_w->name) || !GetSize(cell->getPort(tpl_w->name))) &&
210 (!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname))))
211 {
212 if (sigmaps.count(tpl) == 0)
213 sigmaps[tpl].set(tpl);
214
215 for (auto bit : sigmaps.at(tpl)(tpl_w))
216 if (bit.wire != nullptr)
217 autopurge_tpl_bits.insert(bit);
218 }
219 }
220 IdString w_name = tpl_w->name;
221 apply_prefix(cell->name, w_name);
222 RTLIL::Wire *w = module->wire(w_name);
223 if (w != nullptr) {
224 if (!flatten_mode || !w->get_bool_attribute(ID::hierconn)) {
225 temp_renamed_wires[w] = w->name;
226 module->rename(w, NEW_ID);
227 w = nullptr;
228 } else {
229 w->attributes.erase(ID::hierconn);
230 if (GetSize(w) < GetSize(tpl_w)) {
231 log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w),
232 log_id(tpl), log_id(tpl_w), log_id(module), log_id(cell));
233 w->width = GetSize(tpl_w);
234 }
235 }
236 }
237 if (w == nullptr) {
238 w = module->addWire(w_name, tpl_w);
239 w->port_input = false;
240 w->port_output = false;
241 w->port_id = 0;
242 if (!flatten_mode)
243 w->attributes.erase(ID::techmap_autopurge);
244 if (tpl_w->get_bool_attribute(ID::_techmap_special_))
245 w->attributes.clear();
246 if (w->attributes.count(ID::src))
247 w->add_strpool_attribute(ID::src, extra_src_attrs);
248 }
249 design->select(module, w);
250
251 if (tpl_w->name.begins_with("\\_TECHMAP_REPLACE_.")) {
252 IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), tpl_w->name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
253 Wire *replace_w = module->addWire(replace_name, tpl_w);
254 module->connect(replace_w, w);
255 }
256 }
257
258 SigMap tpl_sigmap(tpl);
259 pool<SigBit> tpl_written_bits;
260
261 for (auto tpl_cell : tpl->cells())
262 for (auto &conn : tpl_cell->connections())
263 if (tpl_cell->output(conn.first))
264 for (auto bit : tpl_sigmap(conn.second))
265 tpl_written_bits.insert(bit);
266 for (auto &conn : tpl->connections())
267 for (auto bit : tpl_sigmap(conn.first))
268 tpl_written_bits.insert(bit);
269
270 SigMap port_signal_map;
271 SigSig port_signal_assign;
272
273 for (auto &it : cell->connections())
274 {
275 IdString portname = it.first;
276 if (positional_ports.count(portname) > 0)
277 portname = positional_ports.at(portname);
278 if (tpl->wire(portname) == nullptr || tpl->wire(portname)->port_id == 0) {
279 if (portname.begins_with("$"))
280 log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
281 continue;
282 }
283
284 if (GetSize(it.second) == 0)
285 continue;
286
287 RTLIL::Wire *w = tpl->wire(portname);
288 RTLIL::SigSig c, extra_connect;
289
290 if (w->port_output && !w->port_input) {
291 c.first = it.second;
292 c.second = RTLIL::SigSpec(w);
293 apply_prefix(cell->name, c.second, module);
294 extra_connect.first = c.second;
295 extra_connect.second = c.first;
296 } else if (!w->port_output && w->port_input) {
297 c.first = RTLIL::SigSpec(w);
298 c.second = it.second;
299 apply_prefix(cell->name, c.first, module);
300 extra_connect.first = c.first;
301 extra_connect.second = c.second;
302 } else {
303 SigSpec sig_tpl = w, sig_tpl_pf = w, sig_mod = it.second;
304 apply_prefix(cell->name, sig_tpl_pf, module);
305 for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) {
306 if (tpl_written_bits.count(tpl_sigmap(sig_tpl[i]))) {
307 c.first.append(sig_mod[i]);
308 c.second.append(sig_tpl_pf[i]);
309 } else {
310 c.first.append(sig_tpl_pf[i]);
311 c.second.append(sig_mod[i]);
312 }
313 }
314 extra_connect.first = sig_tpl_pf;
315 extra_connect.second = sig_mod;
316 }
317
318 if (c.second.size() > c.first.size())
319 c.second.remove(c.first.size(), c.second.size() - c.first.size());
320
321 if (c.second.size() < c.first.size())
322 c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
323
324 log_assert(c.first.size() == c.second.size());
325
326 if (flatten_mode)
327 {
328 // more conservative approach:
329 // connect internal and external wires
330
331 if (sigmaps.count(module) == 0)
332 sigmaps[module].set(module);
333
334 if (sigmaps.at(module)(c.first).has_const())
335 log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
336 log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second));
337
338 module->connect(c);
339 }
340 else
341 {
342 // approach that yields nicer outputs:
343 // replace internal wires that are connected to external wires
344
345 if (w->port_output && !w->port_input) {
346 port_signal_map.add(c.second, c.first);
347 } else
348 if (!w->port_output && w->port_input) {
349 port_signal_map.add(c.first, c.second);
350 } else {
351 module->connect(c);
352 extra_connect = SigSig();
353 }
354
355 for (auto &attr : w->attributes) {
356 if (attr.first == ID::src)
357 continue;
358 auto lhs = GetSize(extra_connect.first);
359 auto rhs = GetSize(extra_connect.second);
360 if (lhs > rhs)
361 extra_connect.first.remove(rhs, lhs-rhs);
362 else if (rhs > lhs)
363 extra_connect.second.remove(lhs, rhs-lhs);
364 module->connect(extra_connect);
365 break;
366 }
367 }
368 }
369
370 for (auto tpl_cell : tpl->cells())
371 {
372 IdString c_name = tpl_cell->name;
373 bool techmap_replace_cell = (!flatten_mode) && (c_name == ID::_TECHMAP_REPLACE_);
374
375 if (techmap_replace_cell)
376 c_name = orig_cell_name;
377 else if (tpl_cell->name.begins_with("\\_TECHMAP_REPLACE_."))
378 c_name = stringf("%s%s", orig_cell_name.c_str(), c_name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
379 else
380 apply_prefix(cell->name, c_name);
381
382 RTLIL::Cell *c = module->addCell(c_name, tpl_cell);
383 design->select(module, c);
384
385 if (!flatten_mode && c->type.begins_with("\\$"))
386 c->type = c->type.substr(1);
387
388 vector<IdString> autopurge_ports;
389
390 for (auto &conn : c->connections())
391 {
392 bool autopurge = false;
393 if (!autopurge_tpl_bits.empty()) {
394 autopurge = GetSize(conn.second) != 0;
395 for (auto &bit : sigmaps.at(tpl)(conn.second))
396 if (!autopurge_tpl_bits.count(bit)) {
397 autopurge = false;
398 break;
399 }
400 }
401
402 if (autopurge) {
403 autopurge_ports.push_back(conn.first);
404 } else {
405 RTLIL::SigSpec new_conn = conn.second;
406 apply_prefix(cell->name, new_conn, module);
407 port_signal_map.apply(new_conn);
408 c->setPort(conn.first, std::move(new_conn));
409 }
410 }
411
412 for (auto &it2 : autopurge_ports)
413 c->unsetPort(it2);
414
415 if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
416 IdString memid = c->getParam(ID::MEMID).decode_string();
417 log_assert(memory_renames.count(memid) != 0);
418 c->setParam(ID::MEMID, Const(memory_renames[memid].str()));
419 }
420
421 if (c->type == ID($mem)) {
422 IdString memid = c->getParam(ID::MEMID).decode_string();
423 apply_prefix(cell->name, memid);
424 c->setParam(ID::MEMID, Const(memid.c_str()));
425 }
426
427 if (c->attributes.count(ID::src))
428 c->add_strpool_attribute(ID::src, extra_src_attrs);
429
430 if (techmap_replace_cell)
431 for (auto attr : cell->attributes)
432 if (!c->attributes.count(attr.first))
433 c->attributes[attr.first] = attr.second;
434 }
435
436 for (auto &it : tpl->connections()) {
437 RTLIL::SigSig c = it;
438 apply_prefix(cell->name.str(), c.first, module);
439 apply_prefix(cell->name.str(), c.second, module);
440 port_signal_map.apply(c.first);
441 port_signal_map.apply(c.second);
442 module->connect(c);
443 }
444
445 module->remove(cell);
446
447 for (auto &it : temp_renamed_wires)
448 {
449 Wire *w = it.first;
450 IdString name = it.second;
451 IdString altname = module->uniquify(name);
452 Wire *other_w = module->wire(name);
453 module->rename(other_w, altname);
454 module->rename(w, name);
455 }
456 }
457
458 bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool<RTLIL::Cell*> &handled_cells,
459 const dict<IdString, pool<IdString>> &celltypeMap, bool in_recursion)
460 {
461 std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";
462
463 if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb))
464 return false;
465
466 bool log_continue = false;
467 bool did_something = false;
468 LogMakeDebugHdl mkdebug;
469
470 SigMap sigmap(module);
471
472 dict<SigBit, State> init_bits;
473 pool<SigBit> remove_init_bits;
474
475 for (auto wire : module->wires()) {
476 if (wire->attributes.count(ID::init)) {
477 Const value = wire->attributes.at(ID::init);
478 for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
479 if (value[i] != State::Sx)
480 init_bits[sigmap(SigBit(wire, i))] = value[i];
481 }
482 }
483
484 TopoSort<RTLIL::Cell*, IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
485 dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_to_inbit;
486 dict<RTLIL::SigBit, pool<RTLIL::Cell*>> outbit_to_cell;
487
488 for (auto cell : module->selected_cells())
489 {
490 if (handled_cells.count(cell) > 0)
491 continue;
492
493 std::string cell_type = cell->type.str();
494 if (in_recursion && cell->type.begins_with("\\$"))
495 cell_type = cell_type.substr(1);
496
497 if (celltypeMap.count(cell_type) == 0) {
498 if (assert_mode && cell_type.back() != '_')
499 log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type));
500 continue;
501 }
502
503 if (flatten_mode) {
504 bool keepit = cell->get_bool_attribute(ID::keep_hierarchy);
505 for (auto &tpl_name : celltypeMap.at(cell_type))
506 if (map->module(tpl_name)->get_bool_attribute(ID::keep_hierarchy))
507 keepit = true;
508 if (keepit) {
509 if (!flatten_keep_list[cell]) {
510 log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell));
511 flatten_keep_list.insert(cell);
512 }
513 if (!flatten_done_list[cell->type])
514 flatten_do_list.insert(cell->type);
515 continue;
516 }
517 }
518
519 for (auto &conn : cell->connections())
520 {
521 RTLIL::SigSpec sig = sigmap(conn.second);
522 sig.remove_const();
523
524 if (GetSize(sig) == 0)
525 continue;
526
527 for (auto &tpl_name : celltypeMap.at(cell_type)) {
528 RTLIL::Module *tpl = map->module(tpl_name);
529 RTLIL::Wire *port = tpl->wire(conn.first);
530 if (port && port->port_input)
531 cell_to_inbit[cell].insert(sig.begin(), sig.end());
532 if (port && port->port_output)
533 for (auto &bit : sig)
534 outbit_to_cell[bit].insert(cell);
535 }
536 }
537
538 cells.node(cell);
539 }
540
541 for (auto &it_right : cell_to_inbit)
542 for (auto &it_sigbit : it_right.second)
543 for (auto &it_left : outbit_to_cell[it_sigbit])
544 cells.edge(it_left, it_right.first);
545
546 cells.sort();
547
548 for (auto cell : cells.sorted)
549 {
550 log_assert(handled_cells.count(cell) == 0);
551 log_assert(cell == module->cell(cell->name));
552 bool mapped_cell = false;
553
554 std::string cell_type = cell->type.str();
555
556 if (in_recursion && cell->type.begins_with("\\$"))
557 cell_type = cell_type.substr(1);
558
559 for (auto &tpl_name : celltypeMap.at(cell_type))
560 {
561 IdString derived_name = tpl_name;
562 RTLIL::Module *tpl = map->module(tpl_name);
563 dict<IdString, RTLIL::Const> parameters(cell->parameters);
564
565 if (tpl->get_blackbox_attribute(ignore_wb))
566 continue;
567
568 if (!flatten_mode)
569 {
570 std::string extmapper_name;
571
572 if (tpl->get_bool_attribute(ID::techmap_simplemap))
573 extmapper_name = "simplemap";
574
575 if (tpl->get_bool_attribute(ID::techmap_maccmap))
576 extmapper_name = "maccmap";
577
578 if (tpl->attributes.count(ID::techmap_wrap))
579 extmapper_name = "wrap";
580
581 if (!extmapper_name.empty())
582 {
583 cell->type = cell_type;
584
585 if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
586 {
587 std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
588
589 for (auto &c : cell->parameters)
590 m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
591
592 if (extmapper_name == "wrap")
593 m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string());
594
595 RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
596 RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
597
598 if (extmapper_module == nullptr)
599 {
600 extmapper_module = extmapper_design->addModule(m_name);
601 RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
602
603 extmapper_cell->set_src_attribute(cell->get_src_attribute());
604
605 int port_counter = 1;
606 for (auto &c : extmapper_cell->connections_) {
607 RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
608 if (w->name.in(ID::Y, ID::Q))
609 w->port_output = true;
610 else
611 w->port_input = true;
612 w->port_id = port_counter++;
613 c.second = w;
614 }
615
616 extmapper_module->fixup_ports();
617 extmapper_module->check();
618
619 if (extmapper_name == "simplemap") {
620 log("Creating %s with simplemap.\n", log_id(extmapper_module));
621 if (simplemap_mappers.count(extmapper_cell->type) == 0)
622 log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
623 simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
624 extmapper_module->remove(extmapper_cell);
625 }
626
627 if (extmapper_name == "maccmap") {
628 log("Creating %s with maccmap.\n", log_id(extmapper_module));
629 if (extmapper_cell->type != ID($macc))
630 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
631 maccmap(extmapper_module, extmapper_cell);
632 extmapper_module->remove(extmapper_cell);
633 }
634
635 if (extmapper_name == "wrap") {
636 std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string();
637 log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
638 mkdebug.on();
639 Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
640 log_continue = true;
641 }
642 }
643
644 cell->type = extmapper_module->name;
645 cell->parameters.clear();
646
647 if (!extern_mode || in_recursion) {
648 tpl = extmapper_module;
649 goto use_wrapper_tpl;
650 }
651
652 auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
653 if (!log_msg_cache.count(msg)) {
654 log_msg_cache.insert(msg);
655 log("%s\n", msg.c_str());
656 }
657 log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
658 }
659 else
660 {
661 auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type));
662 if (!log_msg_cache.count(msg)) {
663 log_msg_cache.insert(msg);
664 log("%s\n", msg.c_str());
665 }
666 log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
667
668 if (extmapper_name == "simplemap") {
669 if (simplemap_mappers.count(cell->type) == 0)
670 log_error("No simplemap mapper for cell type %s found!\n", log_id(cell->type));
671 simplemap_mappers.at(cell->type)(module, cell);
672 }
673
674 if (extmapper_name == "maccmap") {
675 if (cell->type != ID($macc))
676 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
677 maccmap(module, cell);
678 }
679
680 module->remove(cell);
681 cell = nullptr;
682 }
683
684 did_something = true;
685 mapped_cell = true;
686 break;
687 }
688
689 for (auto &conn : cell->connections()) {
690 if (conn.first.begins_with("$"))
691 continue;
692 if (tpl->wire(conn.first) != nullptr && tpl->wire(conn.first)->port_id > 0)
693 continue;
694 if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
695 goto next_tpl;
696 parameters[conn.first] = conn.second.as_const();
697 }
698
699 if (0) {
700 next_tpl:
701 continue;
702 }
703
704 if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0)
705 parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type));
706
707 for (auto &conn : cell->connections()) {
708 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) {
709 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
710 for (auto &bit : v)
711 bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0);
712 parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
713 }
714 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) {
715 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
716 for (auto &bit : v)
717 if (bit.wire != nullptr)
718 bit = RTLIL::SigBit(RTLIL::State::Sx);
719 parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
720 }
721 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) {
722 auto sig = sigmap(conn.second);
723 RTLIL::Const value(State::Sx, sig.size());
724 for (int i = 0; i < sig.size(); i++) {
725 auto it = init_bits.find(sig[i]);
726 if (it != init_bits.end()) {
727 value[i] = it->second;
728 }
729 }
730 parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), value);
731 }
732 }
733
734 int unique_bit_id_counter = 0;
735 dict<RTLIL::SigBit, int> unique_bit_id;
736 unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++;
737 unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++;
738 unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++;
739 unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
740
741 for (auto &conn : cell->connections())
742 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) {
743 for (auto &bit : sigmap(conn.second))
744 if (unique_bit_id.count(bit) == 0)
745 unique_bit_id[bit] = unique_bit_id_counter++;
746 }
747
748 // Find highest bit set
749 int bits = 0;
750 for (int i = 0; i < 32; i++)
751 if (((unique_bit_id_counter-1) & (1 << i)) != 0)
752 bits = i;
753 // Increment index by one to get number of bits
754 bits++;
755 if (tpl->avail_parameters.count(ID::_TECHMAP_BITS_CONNMAP_))
756 parameters[ID::_TECHMAP_BITS_CONNMAP_] = bits;
757
758 for (auto &conn : cell->connections())
759 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) {
760 RTLIL::Const value;
761 for (auto &bit : sigmap(conn.second)) {
762 int val = unique_bit_id.at(bit);
763 for (int i = 0; i < bits; i++) {
764 value.bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
765 val = val >> 1;
766 }
767 }
768 parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first)), value);
769 }
770 }
771
772 if (0) {
773 use_wrapper_tpl:;
774 // do not register techmap_wrap modules with techmap_cache
775 } else {
776 std::pair<IdString, dict<IdString, RTLIL::Const>> key(tpl_name, parameters);
777 auto it = techmap_cache.find(key);
778 if (it != techmap_cache.end()) {
779 tpl = it->second;
780 } else {
781 if (parameters.size() != 0) {
782 mkdebug.on();
783 derived_name = tpl->derive(map, parameters);
784 tpl = map->module(derived_name);
785 log_continue = true;
786 }
787 techmap_cache.emplace(std::move(key), tpl);
788 }
789 }
790
791 if (flatten_mode) {
792 techmap_do_cache[tpl] = true;
793 } else {
794 RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false));
795 if (constmapped_tpl != nullptr)
796 tpl = constmapped_tpl;
797 }
798
799 if (techmap_do_cache.count(tpl) == 0)
800 {
801 bool keep_running = true;
802 techmap_do_cache[tpl] = true;
803
804 pool<IdString> techmap_wire_names;
805
806 while (keep_running)
807 {
808 TechmapWires twd = techmap_find_special_wires(tpl);
809 keep_running = false;
810
811 for (auto &it : twd)
812 techmap_wire_names.insert(it.first);
813
814 for (auto &it : twd[ID::_TECHMAP_FAIL_]) {
815 RTLIL::SigSpec value = it.value;
816 if (value.is_fully_const() && value.as_bool()) {
817 log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
818 derived_name.c_str(), log_id(it.wire->name), log_signal(value));
819 techmap_do_cache[tpl] = false;
820 }
821 }
822
823 if (!techmap_do_cache[tpl])
824 break;
825
826 for (auto &it : twd)
827 {
828 if (!it.first.begins_with("\\_TECHMAP_DO_") || it.second.empty())
829 continue;
830
831 auto &data = it.second.front();
832
833 if (!data.value.is_fully_const())
834 log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(data.wire->name), log_signal(data.value));
835
836 techmap_wire_names.erase(it.first);
837
838 const char *p = data.wire->name.c_str();
839 const char *q = strrchr(p+1, '.');
840 q = q ? q : p+1;
841
842 std::string cmd_string = data.value.as_const().decode_string();
843
844 restart_eval_cmd_string:
845 if (cmd_string.rfind("CONSTMAP; ", 0) == 0)
846 {
847 cmd_string = cmd_string.substr(strlen("CONSTMAP; "));
848
849 log("Analyzing pattern of constant bits for this cell:\n");
850 IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
851 log("Creating constmapped module `%s'.\n", log_id(new_tpl_name));
852 log_assert(map->module(new_tpl_name) == nullptr);
853
854 RTLIL::Module *new_tpl = map->addModule(new_tpl_name);
855 tpl->cloneInto(new_tpl);
856
857 techmap_do_cache.erase(tpl);
858 techmap_do_cache[new_tpl] = true;
859 tpl = new_tpl;
860
861 dict<RTLIL::SigBit, RTLIL::SigBit> port_new2old_map;
862 dict<RTLIL::SigBit, RTLIL::SigBit> port_connmap;
863 dict<RTLIL::SigBit, RTLIL::SigBit> cellbits_to_tplbits;
864
865 for (auto wire : tpl->wires().to_vector())
866 {
867 if (!wire->port_input || wire->port_output)
868 continue;
869
870 IdString port_name = wire->name;
871 tpl->rename(wire, NEW_ID);
872
873 RTLIL::Wire *new_wire = tpl->addWire(port_name, wire);
874 wire->port_input = false;
875 wire->port_id = 0;
876
877 for (int i = 0; i < wire->width; i++) {
878 port_new2old_map.emplace(RTLIL::SigBit(new_wire, i), RTLIL::SigBit(wire, i));
879 port_connmap.emplace(RTLIL::SigBit(wire, i), RTLIL::SigBit(new_wire, i));
880 }
881 }
882
883 for (auto &conn : cell->connections())
884 for (int i = 0; i < GetSize(conn.second); i++)
885 {
886 RTLIL::SigBit bit = sigmap(conn.second[i]);
887 RTLIL::SigBit tplbit(tpl->wire(conn.first), i);
888
889 if (bit.wire == nullptr)
890 {
891 RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
892 port_connmap.at(oldbit) = bit;
893 }
894 else if (cellbits_to_tplbits.count(bit))
895 {
896 RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
897 port_connmap.at(oldbit) = cellbits_to_tplbits[bit];
898 }
899 else
900 cellbits_to_tplbits[bit] = tplbit;
901 }
902
903 RTLIL::SigSig port_conn;
904 for (auto &it : port_connmap) {
905 port_conn.first.append(it.first);
906 port_conn.second.append(it.second);
907 }
908 tpl->connect(port_conn);
909
910 tpl->check();
911 goto restart_eval_cmd_string;
912 }
913
914 if (cmd_string.rfind("RECURSION; ", 0) == 0)
915 {
916 cmd_string = cmd_string.substr(strlen("RECURSION; "));
917 while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
918 goto restart_eval_cmd_string;
919 }
920
921 Pass::call_on_module(map, tpl, cmd_string);
922
923 log_assert(!strncmp(q, "_TECHMAP_DO_", 12));
924 std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
925 while (tpl->wire(new_name) != nullptr)
926 new_name += "_";
927 tpl->rename(data.wire->name, new_name);
928
929 keep_running = true;
930 break;
931 }
932 }
933
934 TechmapWires twd = techmap_find_special_wires(tpl);
935 for (auto &it : twd) {
936 if (it.first != ID::_TECHMAP_FAIL_ && (!it.first.begins_with("\\_TECHMAP_REMOVEINIT_") || !it.first.ends_with("_")) && !it.first.begins_with("\\_TECHMAP_DO_") && !it.first.begins_with("\\_TECHMAP_DONE_"))
937 log_error("Techmap yielded unknown config wire %s.\n", log_id(it.first));
938 if (techmap_do_cache[tpl])
939 for (auto &it2 : it.second)
940 if (!it2.value.is_fully_const())
941 log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(it2.wire->name), log_signal(it2.value));
942 techmap_wire_names.erase(it.first);
943 }
944
945 for (auto &it : techmap_wire_names)
946 log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", log_id(it));
947
948 if (recursive_mode) {
949 if (log_continue) {
950 log_header(design, "Continuing TECHMAP pass.\n");
951 log_continue = false;
952 mkdebug.off();
953 }
954 while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
955 }
956 }
957
958 if (techmap_do_cache.at(tpl) == false)
959 continue;
960
961 if (log_continue) {
962 log_header(design, "Continuing TECHMAP pass.\n");
963 log_continue = false;
964 mkdebug.off();
965 }
966
967 TechmapWires twd = techmap_find_special_wires(tpl);
968 for (auto &it : twd) {
969 if (it.first.begins_with("\\_TECHMAP_REMOVEINIT_")) {
970 for (auto &it2 : it.second) {
971 auto val = it2.value.as_const();
972 auto wirename = RTLIL::escape_id(it.first.substr(21, it.first.size() - 21 - 1));
973 auto it = cell->connections().find(wirename);
974 if (it != cell->connections().end()) {
975 auto sig = sigmap(it->second);
976 for (int i = 0; i < sig.size(); i++)
977 if (val[i] == State::S1)
978 remove_init_bits.insert(sig[i]);
979 }
980 }
981 }
982 }
983
984 if (extern_mode && !in_recursion)
985 {
986 std::string m_name = stringf("$extern:%s", log_id(tpl));
987
988 if (!design->module(m_name))
989 {
990 RTLIL::Module *m = design->addModule(m_name);
991 tpl->cloneInto(m);
992
993 for (auto cell : m->cells()) {
994 if (cell->type.begins_with("\\$"))
995 cell->type = cell->type.substr(1);
996 }
997
998 module_queue.insert(m);
999 }
1000
1001 log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name));
1002 cell->type = m_name;
1003 cell->parameters.clear();
1004 }
1005 else
1006 {
1007 auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type));
1008 if (!log_msg_cache.count(msg)) {
1009 log_msg_cache.insert(msg);
1010 log("%s\n", msg.c_str());
1011 }
1012 log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl));
1013 techmap_module_worker(design, module, cell, tpl);
1014 cell = nullptr;
1015 }
1016 did_something = true;
1017 mapped_cell = true;
1018 break;
1019 }
1020
1021 if (assert_mode && !mapped_cell)
1022 log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
1023
1024 handled_cells.insert(cell);
1025 }
1026
1027 if (!remove_init_bits.empty()) {
1028 for (auto wire : module->wires())
1029 if (wire->attributes.count(ID::init)) {
1030 Const &value = wire->attributes.at(ID::init);
1031 bool do_cleanup = true;
1032 for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
1033 SigBit bit = sigmap(SigBit(wire, i));
1034 if (remove_init_bits.count(bit))
1035 value[i] = State::Sx;
1036 else if (value[i] != State::Sx)
1037 do_cleanup = false;
1038 }
1039 if (do_cleanup) {
1040 log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
1041 wire->attributes.erase(ID::init);
1042 }
1043 }
1044 }
1045
1046 if (log_continue) {
1047 log_header(design, "Continuing TECHMAP pass.\n");
1048 log_continue = false;
1049 mkdebug.off();
1050 }
1051
1052 return did_something;
1053 }
1054 };
1055
1056 struct TechmapPass : public Pass {
1057 TechmapPass() : Pass("techmap", "generic technology mapper") { }
1058 void help() YS_OVERRIDE
1059 {
1060 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1061 log("\n");
1062 log(" techmap [-map filename] [selection]\n");
1063 log("\n");
1064 log("This pass implements a very simple technology mapper that replaces cells in\n");
1065 log("the design with implementations given in form of a Verilog or ilang source\n");
1066 log("file.\n");
1067 log("\n");
1068 log(" -map filename\n");
1069 log(" the library of cell implementations to be used.\n");
1070 log(" without this parameter a builtin library is used that\n");
1071 log(" transforms the internal RTL cells to the internal gate\n");
1072 log(" library.\n");
1073 log("\n");
1074 log(" -map %%<design-name>\n");
1075 log(" like -map above, but with an in-memory design instead of a file.\n");
1076 log("\n");
1077 log(" -extern\n");
1078 log(" load the cell implementations as separate modules into the design\n");
1079 log(" instead of inlining them.\n");
1080 log("\n");
1081 log(" -max_iter <number>\n");
1082 log(" only run the specified number of iterations on each module.\n");
1083 log(" default: unlimited\n");
1084 log("\n");
1085 log(" -recursive\n");
1086 log(" instead of the iterative breadth-first algorithm use a recursive\n");
1087 log(" depth-first algorithm. both methods should yield equivalent results,\n");
1088 log(" but may differ in performance.\n");
1089 log("\n");
1090 log(" -autoproc\n");
1091 log(" Automatically call \"proc\" on implementations that contain processes.\n");
1092 log("\n");
1093 log(" -wb\n");
1094 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
1095 log("\n");
1096 log(" -assert\n");
1097 log(" this option will cause techmap to exit with an error if it can't map\n");
1098 log(" a selected cell. only cell types that end on an underscore are accepted\n");
1099 log(" as final cell types by this mode.\n");
1100 log("\n");
1101 log(" -D <define>, -I <incdir>\n");
1102 log(" this options are passed as-is to the Verilog frontend for loading the\n");
1103 log(" map file. Note that the Verilog frontend is also called with the\n");
1104 log(" '-nooverwrite' option set.\n");
1105 log("\n");
1106 log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
1107 log("match cells with a type that match the text value of this attribute. Otherwise\n");
1108 log("the module name will be used to match the cell.\n");
1109 log("\n");
1110 log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
1111 log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
1112 log("\n");
1113 log("When a module in the map file has the 'techmap_maccmap' attribute set, techmap\n");
1114 log("will use 'maccmap' (see 'help maccmap') to map cells matching the module.\n");
1115 log("\n");
1116 log("When a module in the map file has the 'techmap_wrap' attribute set, techmap\n");
1117 log("will create a wrapper for the cell and then run the command string that the\n");
1118 log("attribute is set to on the wrapper module.\n");
1119 log("\n");
1120 log("When a port on a module in the map file has the 'techmap_autopurge' attribute\n");
1121 log("set, and that port is not connected in the instantiation that is mapped, then\n");
1122 log("then a cell port connected only to such wires will be omitted in the mapped\n");
1123 log("version of the circuit.\n");
1124 log("\n");
1125 log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
1126 log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
1127 log("the mapping module to the techmap command. At the moment the following special\n");
1128 log("wires are supported:\n");
1129 log("\n");
1130 log(" _TECHMAP_FAIL_\n");
1131 log(" When this wire is set to a non-zero constant value, techmap will not\n");
1132 log(" use this module and instead try the next module with a matching\n");
1133 log(" 'techmap_celltype' attribute.\n");
1134 log("\n");
1135 log(" When such a wire exists but does not have a constant value after all\n");
1136 log(" _TECHMAP_DO_* commands have been executed, an error is generated.\n");
1137 log("\n");
1138 log(" _TECHMAP_DO_*\n");
1139 log(" This wires are evaluated in alphabetical order. The constant text value\n");
1140 log(" of this wire is a yosys command (or sequence of commands) that is run\n");
1141 log(" by techmap on the module. A common use case is to run 'proc' on modules\n");
1142 log(" that are written using always-statements.\n");
1143 log("\n");
1144 log(" When such a wire has a non-constant value at the time it is to be\n");
1145 log(" evaluated, an error is produced. That means it is possible for such a\n");
1146 log(" wire to start out as non-constant and evaluate to a constant value\n");
1147 log(" during processing of other _TECHMAP_DO_* commands.\n");
1148 log("\n");
1149 log(" A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.\n");
1150 log(" in this case techmap will create a copy for each distinct configuration\n");
1151 log(" of constant inputs and shorted inputs at this point and import the\n");
1152 log(" constant and connected bits into the map module. All further commands\n");
1153 log(" are executed in this copy. This is a very convenient way of creating\n");
1154 log(" optimized specializations of techmap modules without using the special\n");
1155 log(" parameters described below.\n");
1156 log("\n");
1157 log(" A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.\n");
1158 log(" then techmap will recursively replace the cells in the module with their\n");
1159 log(" implementation. This is not affected by the -max_iter option.\n");
1160 log("\n");
1161 log(" It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n");
1162 log("\n");
1163 log(" _TECHMAP_REMOVEINIT_<port-name>_\n");
1164 log(" When this wire is set to a constant value, the init attribute of the wire(s)\n");
1165 log(" connected to this port will be consumed. This wire must have the same\n");
1166 log(" width as the given port, and for every bit that is set to 1 in the value,\n");
1167 log(" the corresponding init attribute bit will be changed to 1'bx. If all\n");
1168 log(" bits of an init attribute are left as x, it will be removed.\n");
1169 log("\n");
1170 log("In addition to this special wires, techmap also supports special parameters in\n");
1171 log("modules in the map file:\n");
1172 log("\n");
1173 log(" _TECHMAP_CELLTYPE_\n");
1174 log(" When a parameter with this name exists, it will be set to the type name\n");
1175 log(" of the cell that matches the module.\n");
1176 log("\n");
1177 log(" _TECHMAP_CONSTMSK_<port-name>_\n");
1178 log(" _TECHMAP_CONSTVAL_<port-name>_\n");
1179 log(" When this pair of parameters is available in a module for a port, then\n");
1180 log(" former has a 1-bit for each constant input bit and the latter has the\n");
1181 log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
1182 log("\n");
1183 log(" _TECHMAP_WIREINIT_<port-name>_\n");
1184 log(" When a parameter with this name exists, it will be set to the initial\n");
1185 log(" value of the wire(s) connected to the given port, as specified by the init\n");
1186 log(" attribute. If the attribute doesn't exist, x will be filled for the\n");
1187 log(" missing bits. To remove the init attribute bits used, use the\n");
1188 log(" _TECHMAP_REMOVEINIT_*_ wires.\n");
1189 log("\n");
1190 log(" _TECHMAP_BITS_CONNMAP_\n");
1191 log(" _TECHMAP_CONNMAP_<port-name>_\n");
1192 log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
1193 log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n");
1194 log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n");
1195 log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n");
1196 log(" This can be used to detect shorted inputs.\n");
1197 log("\n");
1198 log("When a module in the map file has a parameter where the according cell in the\n");
1199 log("design has a port, the module from the map file is only used if the port in\n");
1200 log("the design is connected to a constant value. The parameter is then set to the\n");
1201 log("constant value.\n");
1202 log("\n");
1203 log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
1204 log("and attributes of the cell that is being replaced.\n");
1205 log("A cell with a name of the form `_TECHMAP_REPLACE_.<suffix>` in the map file will\n");
1206 log("be named thus but with the `_TECHMAP_REPLACE_' prefix substituted with the name\n");
1207 log("of the cell being replaced.\n");
1208 log("Similarly, a wire named in the form `_TECHMAP_REPLACE_.<suffix>` will cause a\n");
1209 log("new wire alias to be created and named as above but with the `_TECHMAP_REPLACE_'\n");
1210 log("prefix also substituted.\n");
1211 log("\n");
1212 log("See 'help extract' for a pass that does the opposite thing.\n");
1213 log("\n");
1214 log("See 'help flatten' for a pass that does flatten the design (which is\n");
1215 log("essentially techmap but using the design itself as map library).\n");
1216 log("\n");
1217 }
1218 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1219 {
1220 log_header(design, "Executing TECHMAP pass (map to technology primitives).\n");
1221 log_push();
1222
1223 TechmapWorker worker;
1224 simplemap_get_mappers(worker.simplemap_mappers);
1225
1226 std::vector<std::string> map_files;
1227 std::string verilog_frontend = "verilog -nooverwrite -noblackbox";
1228 int max_iter = -1;
1229
1230 size_t argidx;
1231 for (argidx = 1; argidx < args.size(); argidx++) {
1232 if (args[argidx] == "-map" && argidx+1 < args.size()) {
1233 map_files.push_back(args[++argidx]);
1234 continue;
1235 }
1236 if (args[argidx] == "-max_iter" && argidx+1 < args.size()) {
1237 max_iter = atoi(args[++argidx].c_str());
1238 continue;
1239 }
1240 if (args[argidx] == "-D" && argidx+1 < args.size()) {
1241 verilog_frontend += " -D " + args[++argidx];
1242 continue;
1243 }
1244 if (args[argidx] == "-I" && argidx+1 < args.size()) {
1245 verilog_frontend += " -I " + args[++argidx];
1246 continue;
1247 }
1248 if (args[argidx] == "-assert") {
1249 worker.assert_mode = true;
1250 continue;
1251 }
1252 if (args[argidx] == "-extern") {
1253 worker.extern_mode = true;
1254 continue;
1255 }
1256 if (args[argidx] == "-recursive") {
1257 worker.recursive_mode = true;
1258 continue;
1259 }
1260 if (args[argidx] == "-autoproc") {
1261 worker.autoproc_mode = true;
1262 continue;
1263 }
1264 if (args[argidx] == "-wb") {
1265 worker.ignore_wb = true;
1266 continue;
1267 }
1268 break;
1269 }
1270 extra_args(args, argidx, design);
1271
1272 RTLIL::Design *map = new RTLIL::Design;
1273 if (map_files.empty()) {
1274 Frontend::frontend_call(map, nullptr, "+/techmap.v", verilog_frontend);
1275 } else {
1276 for (auto &fn : map_files)
1277 if (fn.compare(0, 1, "%") == 0) {
1278 if (!saved_designs.count(fn.substr(1))) {
1279 delete map;
1280 log_cmd_error("Can't open saved design `%s'.\n", fn.c_str()+1);
1281 }
1282 for (auto mod : saved_designs.at(fn.substr(1))->modules())
1283 if (!map->module(mod->name))
1284 map->add(mod->clone());
1285 } else {
1286 Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend));
1287 }
1288 }
1289
1290 log_header(design, "Continuing TECHMAP pass.\n");
1291
1292 dict<IdString, pool<IdString>> celltypeMap;
1293 for (auto module : map->modules()) {
1294 if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).bits.empty()) {
1295 char *p = strdup(module->attributes.at(ID::techmap_celltype).decode_string().c_str());
1296 for (char *q = strtok(p, " \t\r\n"); q; q = strtok(nullptr, " \t\r\n"))
1297 celltypeMap[RTLIL::escape_id(q)].insert(module->name);
1298 free(p);
1299 } else {
1300 IdString module_name = module->name.begins_with("\\$") ?
1301 module->name.substr(1) : module->name.str();
1302 celltypeMap[module_name].insert(module->name);
1303 }
1304 }
1305 for (auto &i : celltypeMap)
1306 i.second.sort(RTLIL::sort_by_id_str());
1307
1308 for (auto module : design->modules())
1309 worker.module_queue.insert(module);
1310
1311 while (!worker.module_queue.empty())
1312 {
1313 RTLIL::Module *module = *worker.module_queue.begin();
1314 worker.module_queue.erase(module);
1315
1316 int module_max_iter = max_iter;
1317 bool did_something = true;
1318 pool<RTLIL::Cell*> handled_cells;
1319 while (did_something) {
1320 did_something = false;
1321 if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
1322 did_something = true;
1323 if (did_something)
1324 module->check();
1325 if (module_max_iter > 0 && --module_max_iter == 0)
1326 break;
1327 }
1328 }
1329
1330 log("No more expansions possible.\n");
1331 delete map;
1332
1333 log_pop();
1334 }
1335 } TechmapPass;
1336
1337 struct FlattenPass : public Pass {
1338 FlattenPass() : Pass("flatten", "flatten design") { }
1339 void help() YS_OVERRIDE
1340 {
1341 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1342 log("\n");
1343 log(" flatten [options] [selection]\n");
1344 log("\n");
1345 log("This pass flattens the design by replacing cells by their implementation. This\n");
1346 log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
1347 log("pass is using the current design as mapping library.\n");
1348 log("\n");
1349 log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
1350 log("flattened by this command.\n");
1351 log("\n");
1352 log(" -wb\n");
1353 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
1354 log("\n");
1355 }
1356 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1357 {
1358 log_header(design, "Executing FLATTEN pass (flatten design).\n");
1359 log_push();
1360
1361 TechmapWorker worker;
1362 worker.flatten_mode = true;
1363
1364 size_t argidx;
1365 for (argidx = 1; argidx < args.size(); argidx++) {
1366 if (args[argidx] == "-wb") {
1367 worker.ignore_wb = true;
1368 continue;
1369 }
1370 break;
1371 }
1372 extra_args(args, argidx, design);
1373
1374
1375 dict<IdString, pool<IdString>> celltypeMap;
1376 for (auto module : design->modules())
1377 celltypeMap[module->name].insert(module->name);
1378 for (auto &i : celltypeMap)
1379 i.second.sort(RTLIL::sort_by_id_str());
1380
1381 RTLIL::Module *top_mod = nullptr;
1382 if (design->full_selection())
1383 for (auto mod : design->modules())
1384 if (mod->get_bool_attribute(ID::top))
1385 top_mod = mod;
1386
1387 pool<RTLIL::Cell*> handled_cells;
1388 if (top_mod != nullptr) {
1389 worker.flatten_do_list.insert(top_mod->name);
1390 while (!worker.flatten_do_list.empty()) {
1391 auto mod = design->module(*worker.flatten_do_list.begin());
1392 while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
1393 worker.flatten_done_list.insert(mod->name);
1394 worker.flatten_do_list.erase(mod->name);
1395 }
1396 } else {
1397 for (auto mod : design->modules().to_vector())
1398 while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
1399 }
1400
1401 log_suppressed();
1402 log("No more expansions possible.\n");
1403
1404 if (top_mod != nullptr)
1405 {
1406 pool<IdString> used_modules, new_used_modules;
1407 new_used_modules.insert(top_mod->name);
1408 while (!new_used_modules.empty()) {
1409 pool<IdString> queue;
1410 queue.swap(new_used_modules);
1411 for (auto modname : queue)
1412 used_modules.insert(modname);
1413 for (auto modname : queue)
1414 for (auto cell : design->module(modname)->cells())
1415 if (design->module(cell->type) && !used_modules[cell->type])
1416 new_used_modules.insert(cell->type);
1417 }
1418
1419 for (auto mod : design->modules().to_vector())
1420 if (!used_modules[mod->name] && !mod->get_blackbox_attribute(worker.ignore_wb)) {
1421 log("Deleting now unused module %s.\n", log_id(mod));
1422 design->remove(mod);
1423 }
1424 }
1425
1426 log_pop();
1427 }
1428 } FlattenPass;
1429
1430 PRIVATE_NAMESPACE_END