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Transform "$.*" to ID("$.*") in passes/techmap
[yosys.git] / passes / techmap / techmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/utils.h"
22 #include "kernel/sigtools.h"
23 #include "libs/sha1/sha1.h"
24
25 #include <stdlib.h>
26 #include <stdio.h>
27 #include <string.h>
28
29 #include "simplemap.h"
30 #include "passes/techmap/techmap.inc"
31
32 YOSYS_NAMESPACE_BEGIN
33
34 // see maccmap.cc
35 extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false);
36
37 YOSYS_NAMESPACE_END
38
39 USING_YOSYS_NAMESPACE
40 PRIVATE_NAMESPACE_BEGIN
41
42 void apply_prefix(std::string prefix, std::string &id)
43 {
44 if (id[0] == '\\')
45 id = prefix + "." + id.substr(1);
46 else
47 id = "$techmap" + prefix + "." + id;
48 }
49
50 void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
51 {
52 vector<SigChunk> chunks = sig;
53 for (auto &chunk : chunks)
54 if (chunk.wire != NULL) {
55 std::string wire_name = chunk.wire->name.str();
56 apply_prefix(prefix, wire_name);
57 log_assert(module->wires_.count(wire_name) > 0);
58 chunk.wire = module->wires_[wire_name];
59 }
60 sig = chunks;
61 }
62
63 struct TechmapWorker
64 {
65 std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
66 std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
67 std::map<RTLIL::Module*, bool> techmap_do_cache;
68 std::set<RTLIL::Module*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Module>> module_queue;
69 dict<Module*, SigMap> sigmaps;
70
71 pool<IdString> flatten_do_list;
72 pool<IdString> flatten_done_list;
73 pool<Cell*> flatten_keep_list;
74
75 pool<string> log_msg_cache;
76
77 struct TechmapWireData {
78 RTLIL::Wire *wire;
79 RTLIL::SigSpec value;
80 };
81
82 typedef std::map<std::string, std::vector<TechmapWireData>> TechmapWires;
83
84 bool extern_mode;
85 bool assert_mode;
86 bool flatten_mode;
87 bool recursive_mode;
88 bool autoproc_mode;
89 bool ignore_wb;
90
91 TechmapWorker()
92 {
93 extern_mode = false;
94 assert_mode = false;
95 flatten_mode = false;
96 recursive_mode = false;
97 autoproc_mode = false;
98 ignore_wb = false;
99 }
100
101 std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose)
102 {
103 std::string constmap_info;
104 std::map<RTLIL::SigBit, std::pair<RTLIL::IdString, int>> connbits_map;
105
106 for (auto conn : cell->connections())
107 for (int i = 0; i < GetSize(conn.second); i++) {
108 RTLIL::SigBit bit = sigmap(conn.second[i]);
109 if (bit.wire == nullptr) {
110 if (verbose)
111 log(" Constant input on bit %d of port %s: %s\n", i, log_id(conn.first), log_signal(bit));
112 constmap_info += stringf("|%s %d %d", log_id(conn.first), i, bit.data);
113 } else if (connbits_map.count(bit)) {
114 if (verbose)
115 log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, log_id(conn.first),
116 connbits_map.at(bit).second, log_id(connbits_map.at(bit).first));
117 constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i,
118 log_id(connbits_map.at(bit).first), connbits_map.at(bit).second);
119 } else {
120 connbits_map[bit] = std::pair<RTLIL::IdString, int>(conn.first, i);
121 constmap_info += stringf("|%s %d", log_id(conn.first), i);
122 }
123 }
124
125 return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str());
126 }
127
128 TechmapWires techmap_find_special_wires(RTLIL::Module *module)
129 {
130 TechmapWires result;
131
132 if (module == NULL)
133 return result;
134
135 for (auto &it : module->wires_) {
136 const char *p = it.first.c_str();
137 if (*p == '$')
138 continue;
139
140 const char *q = strrchr(p+1, '.');
141 p = q ? q+1 : p+1;
142
143 if (!strncmp(p, "_TECHMAP_", 9)) {
144 TechmapWireData record;
145 record.wire = it.second;
146 record.value = it.second;
147 result[p].push_back(record);
148 it.second->attributes["\\keep"] = RTLIL::Const(1);
149 it.second->attributes["\\_techmap_special_"] = RTLIL::Const(1);
150 }
151 }
152
153 if (!result.empty()) {
154 SigMap sigmap(module);
155 for (auto &it1 : result)
156 for (auto &it2 : it1.second)
157 sigmap.apply(it2.value);
158 }
159
160 return result;
161 }
162
163 void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl)
164 {
165 if (tpl->processes.size() != 0) {
166 log("Technology map yielded processes:");
167 for (auto &it : tpl->processes)
168 log(" %s",RTLIL::id2cstr(it.first));
169 log("\n");
170 if (autoproc_mode) {
171 Pass::call_on_module(tpl->design, tpl, "proc");
172 log_assert(GetSize(tpl->processes) == 0);
173 } else
174 log_error("Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).\n");
175 }
176
177 std::string orig_cell_name;
178 pool<string> extra_src_attrs = cell->get_strpool_attribute("\\src");
179
180 if (!flatten_mode) {
181 for (auto &it : tpl->cells_)
182 if (it.first == "\\_TECHMAP_REPLACE_") {
183 orig_cell_name = cell->name.str();
184 module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
185 break;
186 }
187 }
188
189 dict<IdString, IdString> memory_renames;
190
191 for (auto &it : tpl->memories) {
192 std::string m_name = it.first.str();
193 apply_prefix(cell->name.str(), m_name);
194 RTLIL::Memory *m = new RTLIL::Memory;
195 m->name = m_name;
196 m->width = it.second->width;
197 m->start_offset = it.second->start_offset;
198 m->size = it.second->size;
199 m->attributes = it.second->attributes;
200 if (m->attributes.count("\\src"))
201 m->add_strpool_attribute("\\src", extra_src_attrs);
202 module->memories[m->name] = m;
203 memory_renames[it.first] = m->name;
204 design->select(module, m);
205 }
206
207 std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
208
209 for (auto &it : tpl->wires_) {
210 if (it.second->port_id > 0)
211 positional_ports[stringf("$%d", it.second->port_id)] = it.first;
212 std::string w_name = it.second->name.str();
213 apply_prefix(cell->name.str(), w_name);
214 RTLIL::Wire *w = module->addWire(w_name, it.second);
215 w->port_input = false;
216 w->port_output = false;
217 w->port_id = 0;
218 if (it.second->get_bool_attribute("\\_techmap_special_"))
219 w->attributes.clear();
220 if (w->attributes.count("\\src"))
221 w->add_strpool_attribute("\\src", extra_src_attrs);
222 design->select(module, w);
223 }
224
225 SigMap tpl_sigmap(tpl);
226 pool<SigBit> tpl_written_bits;
227
228 for (auto &it1 : tpl->cells_)
229 for (auto &it2 : it1.second->connections_)
230 if (it1.second->output(it2.first))
231 for (auto bit : tpl_sigmap(it2.second))
232 tpl_written_bits.insert(bit);
233 for (auto &it1 : tpl->connections_)
234 for (auto bit : tpl_sigmap(it1.first))
235 tpl_written_bits.insert(bit);
236
237 SigMap port_signal_map;
238 SigSig port_signal_assign;
239
240 for (auto &it : cell->connections())
241 {
242 RTLIL::IdString portname = it.first;
243 if (positional_ports.count(portname) > 0)
244 portname = positional_ports.at(portname);
245 if (tpl->wires_.count(portname) == 0 || tpl->wires_.at(portname)->port_id == 0) {
246 if (portname.begins_with("$"))
247 log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
248 continue;
249 }
250
251 if (GetSize(it.second) == 0)
252 continue;
253
254 RTLIL::Wire *w = tpl->wires_.at(portname);
255 RTLIL::SigSig c, extra_connect;
256
257 if (w->port_output && !w->port_input) {
258 c.first = it.second;
259 c.second = RTLIL::SigSpec(w);
260 apply_prefix(cell->name.str(), c.second, module);
261 extra_connect.first = c.second;
262 extra_connect.second = c.first;
263 } else if (!w->port_output && w->port_input) {
264 c.first = RTLIL::SigSpec(w);
265 c.second = it.second;
266 apply_prefix(cell->name.str(), c.first, module);
267 extra_connect.first = c.first;
268 extra_connect.second = c.second;
269 } else {
270 SigSpec sig_tpl = w, sig_tpl_pf = w, sig_mod = it.second;
271 apply_prefix(cell->name.str(), sig_tpl_pf, module);
272 for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) {
273 if (tpl_written_bits.count(tpl_sigmap(sig_tpl[i]))) {
274 c.first.append(sig_mod[i]);
275 c.second.append(sig_tpl_pf[i]);
276 } else {
277 c.first.append(sig_tpl_pf[i]);
278 c.second.append(sig_mod[i]);
279 }
280 }
281 extra_connect.first = sig_tpl_pf;
282 extra_connect.second = sig_mod;
283 }
284
285 if (c.second.size() > c.first.size())
286 c.second.remove(c.first.size(), c.second.size() - c.first.size());
287
288 if (c.second.size() < c.first.size())
289 c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
290
291 log_assert(c.first.size() == c.second.size());
292
293 if (flatten_mode)
294 {
295 // more conservative approach:
296 // connect internal and external wires
297
298 if (sigmaps.count(module) == 0)
299 sigmaps[module].set(module);
300
301 if (sigmaps.at(module)(c.first).has_const())
302 log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
303 log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second));
304
305 module->connect(c);
306 }
307 else
308 {
309 // approach that yields nicer outputs:
310 // replace internal wires that are connected to external wires
311
312 if (w->port_output && !w->port_input) {
313 port_signal_map.add(c.second, c.first);
314 } else
315 if (!w->port_output && w->port_input) {
316 port_signal_map.add(c.first, c.second);
317 } else {
318 module->connect(c);
319 extra_connect = SigSig();
320 }
321
322 for (auto &attr : w->attributes) {
323 if (attr.first == "\\src")
324 continue;
325 module->connect(extra_connect);
326 break;
327 }
328 }
329 }
330
331 for (auto &it : tpl->cells_)
332 {
333 std::string c_name = it.second->name.str();
334 bool techmap_replace_cell = (!flatten_mode) && (c_name == "\\_TECHMAP_REPLACE_");
335
336 if (techmap_replace_cell)
337 c_name = orig_cell_name;
338 else
339 apply_prefix(cell->name.str(), c_name);
340
341 RTLIL::Cell *c = module->addCell(c_name, it.second);
342 design->select(module, c);
343
344 if (!flatten_mode && c->type.begins_with("\\$"))
345 c->type = c->type.substr(1);
346
347 for (auto &it2 : c->connections_) {
348 apply_prefix(cell->name.str(), it2.second, module);
349 port_signal_map.apply(it2.second);
350 }
351
352 if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
353 IdString memid = c->getParam("\\MEMID").decode_string();
354 log_assert(memory_renames.count(memid) != 0);
355 c->setParam("\\MEMID", Const(memory_renames[memid].str()));
356 }
357
358 if (c->type == ID($mem)) {
359 string memid = c->getParam("\\MEMID").decode_string();
360 apply_prefix(cell->name.str(), memid);
361 c->setParam("\\MEMID", Const(memid));
362 }
363
364 if (c->attributes.count("\\src"))
365 c->add_strpool_attribute("\\src", extra_src_attrs);
366
367 if (techmap_replace_cell)
368 for (auto attr : cell->attributes)
369 if (!c->attributes.count(attr.first))
370 c->attributes[attr.first] = attr.second;
371 }
372
373 for (auto &it : tpl->connections()) {
374 RTLIL::SigSig c = it;
375 apply_prefix(cell->name.str(), c.first, module);
376 apply_prefix(cell->name.str(), c.second, module);
377 port_signal_map.apply(c.first);
378 port_signal_map.apply(c.second);
379 module->connect(c);
380 }
381
382 module->remove(cell);
383 }
384
385 bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
386 const std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> &celltypeMap, bool in_recursion)
387 {
388 std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";
389
390 if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb))
391 return false;
392
393 bool log_continue = false;
394 bool did_something = false;
395 LogMakeDebugHdl mkdebug;
396
397 SigMap sigmap(module);
398
399 TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
400 std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
401 std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
402
403 for (auto cell : module->cells())
404 {
405 if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
406 continue;
407
408 std::string cell_type = cell->type.str();
409 if (in_recursion && cell->type.begins_with("\\$"))
410 cell_type = cell_type.substr(1);
411
412 if (celltypeMap.count(cell_type) == 0) {
413 if (assert_mode && cell_type.back() != '_')
414 log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type));
415 continue;
416 }
417
418 if (flatten_mode) {
419 bool keepit = cell->get_bool_attribute("\\keep_hierarchy");
420 for (auto &tpl_name : celltypeMap.at(cell_type))
421 if (map->modules_[tpl_name]->get_bool_attribute("\\keep_hierarchy"))
422 keepit = true;
423 if (keepit) {
424 if (!flatten_keep_list[cell]) {
425 log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell));
426 flatten_keep_list.insert(cell);
427 }
428 if (!flatten_done_list[cell->type])
429 flatten_do_list.insert(cell->type);
430 continue;
431 }
432 }
433
434 for (auto &conn : cell->connections())
435 {
436 RTLIL::SigSpec sig = sigmap(conn.second);
437 sig.remove_const();
438
439 if (GetSize(sig) == 0)
440 continue;
441
442 for (auto &tpl_name : celltypeMap.at(cell_type)) {
443 RTLIL::Module *tpl = map->modules_[tpl_name];
444 RTLIL::Wire *port = tpl->wire(conn.first);
445 if (port && port->port_input)
446 cell_to_inbit[cell].insert(sig.begin(), sig.end());
447 if (port && port->port_output)
448 for (auto &bit : sig)
449 outbit_to_cell[bit].insert(cell);
450 }
451 }
452
453 cells.node(cell);
454 }
455
456 for (auto &it_right : cell_to_inbit)
457 for (auto &it_sigbit : it_right.second)
458 for (auto &it_left : outbit_to_cell[it_sigbit])
459 cells.edge(it_left, it_right.first);
460
461 cells.sort();
462
463 for (auto cell : cells.sorted)
464 {
465 log_assert(handled_cells.count(cell) == 0);
466 log_assert(cell == module->cell(cell->name));
467 bool mapped_cell = false;
468
469 std::string cell_type = cell->type.str();
470
471 if (in_recursion && cell->type.begins_with("\\$"))
472 cell_type = cell_type.substr(1);
473
474 for (auto &tpl_name : celltypeMap.at(cell_type))
475 {
476 RTLIL::IdString derived_name = tpl_name;
477 RTLIL::Module *tpl = map->modules_[tpl_name];
478 std::map<RTLIL::IdString, RTLIL::Const> parameters(cell->parameters.begin(), cell->parameters.end());
479
480 if (tpl->get_blackbox_attribute(ignore_wb))
481 continue;
482
483 if (!flatten_mode)
484 {
485 std::string extmapper_name;
486
487 if (tpl->get_bool_attribute("\\techmap_simplemap"))
488 extmapper_name = "simplemap";
489
490 if (tpl->get_bool_attribute("\\techmap_maccmap"))
491 extmapper_name = "maccmap";
492
493 if (tpl->attributes.count("\\techmap_wrap"))
494 extmapper_name = "wrap";
495
496 if (!extmapper_name.empty())
497 {
498 cell->type = cell_type;
499
500 if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
501 {
502 std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
503
504 for (auto &c : cell->parameters)
505 m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
506
507 if (extmapper_name == "wrap")
508 m_name += ":" + sha1(tpl->attributes.at("\\techmap_wrap").decode_string());
509
510 RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
511 RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
512
513 if (extmapper_module == nullptr)
514 {
515 extmapper_module = extmapper_design->addModule(m_name);
516 RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
517
518 extmapper_cell->set_src_attribute(cell->get_src_attribute());
519
520 int port_counter = 1;
521 for (auto &c : extmapper_cell->connections_) {
522 RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
523 if (w->name.in("\\Y", "\\Q"))
524 w->port_output = true;
525 else
526 w->port_input = true;
527 w->port_id = port_counter++;
528 c.second = w;
529 }
530
531 extmapper_module->fixup_ports();
532 extmapper_module->check();
533
534 if (extmapper_name == "simplemap") {
535 log("Creating %s with simplemap.\n", log_id(extmapper_module));
536 if (simplemap_mappers.count(extmapper_cell->type) == 0)
537 log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
538 simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
539 extmapper_module->remove(extmapper_cell);
540 }
541
542 if (extmapper_name == "maccmap") {
543 log("Creating %s with maccmap.\n", log_id(extmapper_module));
544 if (extmapper_cell->type != ID($macc))
545 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
546 maccmap(extmapper_module, extmapper_cell);
547 extmapper_module->remove(extmapper_cell);
548 }
549
550 if (extmapper_name == "wrap") {
551 std::string cmd_string = tpl->attributes.at("\\techmap_wrap").decode_string();
552 log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
553 mkdebug.on();
554 Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
555 log_continue = true;
556 }
557 }
558
559 cell->type = extmapper_module->name;
560 cell->parameters.clear();
561
562 if (!extern_mode || in_recursion) {
563 tpl = extmapper_module;
564 goto use_wrapper_tpl;
565 }
566
567 auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
568 if (!log_msg_cache.count(msg)) {
569 log_msg_cache.insert(msg);
570 log("%s\n", msg.c_str());
571 }
572 log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
573 }
574 else
575 {
576 auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type));
577 if (!log_msg_cache.count(msg)) {
578 log_msg_cache.insert(msg);
579 log("%s\n", msg.c_str());
580 }
581 log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
582
583 if (extmapper_name == "simplemap") {
584 if (simplemap_mappers.count(cell->type) == 0)
585 log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
586 simplemap_mappers.at(cell->type)(module, cell);
587 }
588
589 if (extmapper_name == "maccmap") {
590 if (cell->type != ID($macc))
591 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
592 maccmap(module, cell);
593 }
594
595 module->remove(cell);
596 cell = NULL;
597 }
598
599 did_something = true;
600 mapped_cell = true;
601 break;
602 }
603
604 for (auto conn : cell->connections()) {
605 if (conn.first.begins_with("$"))
606 continue;
607 if (tpl->wires_.count(conn.first) > 0 && tpl->wires_.at(conn.first)->port_id > 0)
608 continue;
609 if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
610 goto next_tpl;
611 parameters[conn.first] = conn.second.as_const();
612 }
613
614 if (0) {
615 next_tpl:
616 continue;
617 }
618
619 if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0)
620 parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type);
621
622 for (auto conn : cell->connections()) {
623 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
624 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
625 for (auto &bit : v)
626 bit = RTLIL::SigBit(bit.wire == NULL ? RTLIL::State::S1 : RTLIL::State::S0);
627 parameters[stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
628 }
629 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))) != 0) {
630 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
631 for (auto &bit : v)
632 if (bit.wire != NULL)
633 bit = RTLIL::SigBit(RTLIL::State::Sx);
634 parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
635 }
636 }
637
638 int unique_bit_id_counter = 0;
639 std::map<RTLIL::SigBit, int> unique_bit_id;
640 unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++;
641 unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++;
642 unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++;
643 unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
644
645 for (auto conn : cell->connections())
646 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
647 for (auto &bit : sigmap(conn.second).to_sigbit_vector())
648 if (unique_bit_id.count(bit) == 0)
649 unique_bit_id[bit] = unique_bit_id_counter++;
650 }
651
652 // Find highest bit set
653 int bits = 0;
654 for (int i = 0; i < 32; i++)
655 if (((unique_bit_id_counter-1) & (1 << i)) != 0)
656 bits = i;
657 // Increment index by one to get number of bits
658 bits++;
659 if (tpl->avail_parameters.count("\\_TECHMAP_BITS_CONNMAP_"))
660 parameters["\\_TECHMAP_BITS_CONNMAP_"] = bits;
661
662 for (auto conn : cell->connections())
663 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
664 RTLIL::Const value;
665 for (auto &bit : sigmap(conn.second).to_sigbit_vector()) {
666 RTLIL::Const chunk(unique_bit_id.at(bit), bits);
667 value.bits.insert(value.bits.end(), chunk.bits.begin(), chunk.bits.end());
668 }
669 parameters[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))] = value;
670 }
671 }
672
673 if (0) {
674 use_wrapper_tpl:;
675 // do not register techmap_wrap modules with techmap_cache
676 } else {
677 std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
678 if (techmap_cache.count(key) > 0) {
679 tpl = techmap_cache[key];
680 } else {
681 if (parameters.size() != 0) {
682 mkdebug.on();
683 derived_name = tpl->derive(map, dict<RTLIL::IdString, RTLIL::Const>(parameters.begin(), parameters.end()));
684 tpl = map->module(derived_name);
685 log_continue = true;
686 }
687 techmap_cache[key] = tpl;
688 }
689 }
690
691 if (flatten_mode) {
692 techmap_do_cache[tpl] = true;
693 } else {
694 RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false));
695 if (constmapped_tpl != nullptr)
696 tpl = constmapped_tpl;
697 }
698
699 if (techmap_do_cache.count(tpl) == 0)
700 {
701 bool keep_running = true;
702 techmap_do_cache[tpl] = true;
703
704 std::set<std::string> techmap_wire_names;
705
706 while (keep_running)
707 {
708 TechmapWires twd = techmap_find_special_wires(tpl);
709 keep_running = false;
710
711 for (auto &it : twd)
712 techmap_wire_names.insert(it.first);
713
714 for (auto &it : twd["_TECHMAP_FAIL_"]) {
715 RTLIL::SigSpec value = it.value;
716 if (value.is_fully_const() && value.as_bool()) {
717 log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
718 derived_name.c_str(), RTLIL::id2cstr(it.wire->name), log_signal(value));
719 techmap_do_cache[tpl] = false;
720 }
721 }
722
723 if (!techmap_do_cache[tpl])
724 break;
725
726 for (auto &it : twd)
727 {
728 if (it.first.compare(0, 12, "_TECHMAP_DO_") != 0 || it.second.empty())
729 continue;
730
731 auto &data = it.second.front();
732
733 if (!data.value.is_fully_const())
734 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));
735
736 techmap_wire_names.erase(it.first);
737
738 const char *p = data.wire->name.c_str();
739 const char *q = strrchr(p+1, '.');
740 q = q ? q : p+1;
741
742 std::string cmd_string = data.value.as_const().decode_string();
743
744 restart_eval_cmd_string:
745 if (cmd_string.rfind("CONSTMAP; ", 0) == 0)
746 {
747 cmd_string = cmd_string.substr(strlen("CONSTMAP; "));
748
749 log("Analyzing pattern of constant bits for this cell:\n");
750 RTLIL::IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
751 log("Creating constmapped module `%s'.\n", log_id(new_tpl_name));
752 log_assert(map->module(new_tpl_name) == nullptr);
753
754 RTLIL::Module *new_tpl = map->addModule(new_tpl_name);
755 tpl->cloneInto(new_tpl);
756
757 techmap_do_cache.erase(tpl);
758 techmap_do_cache[new_tpl] = true;
759 tpl = new_tpl;
760
761 std::map<RTLIL::SigBit, RTLIL::SigBit> port_new2old_map;
762 std::map<RTLIL::SigBit, RTLIL::SigBit> port_connmap;
763 std::map<RTLIL::SigBit, RTLIL::SigBit> cellbits_to_tplbits;
764
765 for (auto wire : tpl->wires().to_vector())
766 {
767 if (!wire->port_input || wire->port_output)
768 continue;
769
770 RTLIL::IdString port_name = wire->name;
771 tpl->rename(wire, NEW_ID);
772
773 RTLIL::Wire *new_wire = tpl->addWire(port_name, wire);
774 wire->port_input = false;
775 wire->port_id = 0;
776
777 for (int i = 0; i < wire->width; i++) {
778 port_new2old_map[RTLIL::SigBit(new_wire, i)] = RTLIL::SigBit(wire, i);
779 port_connmap[RTLIL::SigBit(wire, i)] = RTLIL::SigBit(new_wire, i);
780 }
781 }
782
783 for (auto conn : cell->connections())
784 for (int i = 0; i < GetSize(conn.second); i++)
785 {
786 RTLIL::SigBit bit = sigmap(conn.second[i]);
787 RTLIL::SigBit tplbit(tpl->wire(conn.first), i);
788
789 if (bit.wire == nullptr)
790 {
791 RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
792 port_connmap.at(oldbit) = bit;
793 }
794 else if (cellbits_to_tplbits.count(bit))
795 {
796 RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
797 port_connmap.at(oldbit) = cellbits_to_tplbits[bit];
798 }
799 else
800 cellbits_to_tplbits[bit] = tplbit;
801 }
802
803 RTLIL::SigSig port_conn;
804 for (auto &it : port_connmap) {
805 port_conn.first.append_bit(it.first);
806 port_conn.second.append_bit(it.second);
807 }
808 tpl->connect(port_conn);
809
810 tpl->check();
811 goto restart_eval_cmd_string;
812 }
813
814 if (cmd_string.rfind("RECURSION; ", 0) == 0)
815 {
816 cmd_string = cmd_string.substr(strlen("RECURSION; "));
817 while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
818 goto restart_eval_cmd_string;
819 }
820
821 Pass::call_on_module(map, tpl, cmd_string);
822
823 log_assert(!strncmp(q, "_TECHMAP_DO_", 12));
824 std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
825 while (tpl->wires_.count(new_name))
826 new_name += "_";
827 tpl->rename(data.wire->name, new_name);
828
829 keep_running = true;
830 break;
831 }
832 }
833
834 TechmapWires twd = techmap_find_special_wires(tpl);
835 for (auto &it : twd) {
836 if (it.first != "_TECHMAP_FAIL_" && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
837 log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str());
838 if (techmap_do_cache[tpl])
839 for (auto &it2 : it.second)
840 if (!it2.value.is_fully_const())
841 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
842 techmap_wire_names.erase(it.first);
843 }
844
845 for (auto &it : techmap_wire_names)
846 log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it));
847
848 if (recursive_mode) {
849 if (log_continue) {
850 log_header(design, "Continuing TECHMAP pass.\n");
851 log_continue = false;
852 mkdebug.off();
853 }
854 while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
855 }
856 }
857
858 if (techmap_do_cache.at(tpl) == false)
859 continue;
860
861 if (log_continue) {
862 log_header(design, "Continuing TECHMAP pass.\n");
863 log_continue = false;
864 mkdebug.off();
865 }
866
867 if (extern_mode && !in_recursion)
868 {
869 std::string m_name = stringf("$extern:%s", log_id(tpl));
870
871 if (!design->module(m_name))
872 {
873 RTLIL::Module *m = design->addModule(m_name);
874 tpl->cloneInto(m);
875
876 for (auto cell : m->cells()) {
877 if (cell->type.begins_with("\\$"))
878 cell->type = cell->type.substr(1);
879 }
880
881 module_queue.insert(m);
882 }
883
884 log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name));
885 cell->type = m_name;
886 cell->parameters.clear();
887 }
888 else
889 {
890 auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type));
891 if (!log_msg_cache.count(msg)) {
892 log_msg_cache.insert(msg);
893 log("%s\n", msg.c_str());
894 }
895 log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl));
896 techmap_module_worker(design, module, cell, tpl);
897 cell = NULL;
898 }
899 did_something = true;
900 mapped_cell = true;
901 break;
902 }
903
904 if (assert_mode && !mapped_cell)
905 log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
906
907 handled_cells.insert(cell);
908 }
909
910 if (log_continue) {
911 log_header(design, "Continuing TECHMAP pass.\n");
912 log_continue = false;
913 mkdebug.off();
914 }
915
916 return did_something;
917 }
918 };
919
920 struct TechmapPass : public Pass {
921 TechmapPass() : Pass("techmap", "generic technology mapper") { }
922 void help() YS_OVERRIDE
923 {
924 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
925 log("\n");
926 log(" techmap [-map filename] [selection]\n");
927 log("\n");
928 log("This pass implements a very simple technology mapper that replaces cells in\n");
929 log("the design with implementations given in form of a Verilog or ilang source\n");
930 log("file.\n");
931 log("\n");
932 log(" -map filename\n");
933 log(" the library of cell implementations to be used.\n");
934 log(" without this parameter a builtin library is used that\n");
935 log(" transforms the internal RTL cells to the internal gate\n");
936 log(" library.\n");
937 log("\n");
938 log(" -map %%<design-name>\n");
939 log(" like -map above, but with an in-memory design instead of a file.\n");
940 log("\n");
941 log(" -extern\n");
942 log(" load the cell implementations as separate modules into the design\n");
943 log(" instead of inlining them.\n");
944 log("\n");
945 log(" -max_iter <number>\n");
946 log(" only run the specified number of iterations.\n");
947 log("\n");
948 log(" -recursive\n");
949 log(" instead of the iterative breadth-first algorithm use a recursive\n");
950 log(" depth-first algorithm. both methods should yield equivalent results,\n");
951 log(" but may differ in performance.\n");
952 log("\n");
953 log(" -autoproc\n");
954 log(" Automatically call \"proc\" on implementations that contain processes.\n");
955 log("\n");
956 log(" -wb\n");
957 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
958 log("\n");
959 log(" -assert\n");
960 log(" this option will cause techmap to exit with an error if it can't map\n");
961 log(" a selected cell. only cell types that end on an underscore are accepted\n");
962 log(" as final cell types by this mode.\n");
963 log("\n");
964 log(" -D <define>, -I <incdir>\n");
965 log(" this options are passed as-is to the Verilog frontend for loading the\n");
966 log(" map file. Note that the Verilog frontend is also called with the\n");
967 log(" '-nooverwrite' option set.\n");
968 log("\n");
969 log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
970 log("match cells with a type that match the text value of this attribute. Otherwise\n");
971 log("the module name will be used to match the cell.\n");
972 log("\n");
973 log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
974 log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
975 log("\n");
976 log("When a module in the map file has the 'techmap_maccmap' attribute set, techmap\n");
977 log("will use 'maccmap' (see 'help maccmap') to map cells matching the module.\n");
978 log("\n");
979 log("When a module in the map file has the 'techmap_wrap' attribute set, techmap\n");
980 log("will create a wrapper for the cell and then run the command string that the\n");
981 log("attribute is set to on the wrapper module.\n");
982 log("\n");
983 log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
984 log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
985 log("the mapping module to the techmap command. At the moment the following special\n");
986 log("wires are supported:\n");
987 log("\n");
988 log(" _TECHMAP_FAIL_\n");
989 log(" When this wire is set to a non-zero constant value, techmap will not\n");
990 log(" use this module and instead try the next module with a matching\n");
991 log(" 'techmap_celltype' attribute.\n");
992 log("\n");
993 log(" When such a wire exists but does not have a constant value after all\n");
994 log(" _TECHMAP_DO_* commands have been executed, an error is generated.\n");
995 log("\n");
996 log(" _TECHMAP_DO_*\n");
997 log(" This wires are evaluated in alphabetical order. The constant text value\n");
998 log(" of this wire is a yosys command (or sequence of commands) that is run\n");
999 log(" by techmap on the module. A common use case is to run 'proc' on modules\n");
1000 log(" that are written using always-statements.\n");
1001 log("\n");
1002 log(" When such a wire has a non-constant value at the time it is to be\n");
1003 log(" evaluated, an error is produced. That means it is possible for such a\n");
1004 log(" wire to start out as non-constant and evaluate to a constant value\n");
1005 log(" during processing of other _TECHMAP_DO_* commands.\n");
1006 log("\n");
1007 log(" A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.\n");
1008 log(" in this case techmap will create a copy for each distinct configuration\n");
1009 log(" of constant inputs and shorted inputs at this point and import the\n");
1010 log(" constant and connected bits into the map module. All further commands\n");
1011 log(" are executed in this copy. This is a very convenient way of creating\n");
1012 log(" optimized specializations of techmap modules without using the special\n");
1013 log(" parameters described below.\n");
1014 log("\n");
1015 log(" A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.\n");
1016 log(" then techmap will recursively replace the cells in the module with their\n");
1017 log(" implementation. This is not affected by the -max_iter option.\n");
1018 log("\n");
1019 log(" It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n");
1020 log("\n");
1021 log("In addition to this special wires, techmap also supports special parameters in\n");
1022 log("modules in the map file:\n");
1023 log("\n");
1024 log(" _TECHMAP_CELLTYPE_\n");
1025 log(" When a parameter with this name exists, it will be set to the type name\n");
1026 log(" of the cell that matches the module.\n");
1027 log("\n");
1028 log(" _TECHMAP_CONSTMSK_<port-name>_\n");
1029 log(" _TECHMAP_CONSTVAL_<port-name>_\n");
1030 log(" When this pair of parameters is available in a module for a port, then\n");
1031 log(" former has a 1-bit for each constant input bit and the latter has the\n");
1032 log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
1033 log("\n");
1034 log(" _TECHMAP_BITS_CONNMAP_\n");
1035 log(" _TECHMAP_CONNMAP_<port-name>_\n");
1036 log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
1037 log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n");
1038 log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n");
1039 log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n");
1040 log(" This can be used to detect shorted inputs.\n");
1041 log("\n");
1042 log("When a module in the map file has a parameter where the according cell in the\n");
1043 log("design has a port, the module from the map file is only used if the port in\n");
1044 log("the design is connected to a constant value. The parameter is then set to the\n");
1045 log("constant value.\n");
1046 log("\n");
1047 log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
1048 log("and attributes of the cell that is being replaced.\n");
1049 log("\n");
1050 log("See 'help extract' for a pass that does the opposite thing.\n");
1051 log("\n");
1052 log("See 'help flatten' for a pass that does flatten the design (which is\n");
1053 log("essentially techmap but using the design itself as map library).\n");
1054 log("\n");
1055 }
1056 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1057 {
1058 log_header(design, "Executing TECHMAP pass (map to technology primitives).\n");
1059 log_push();
1060
1061 TechmapWorker worker;
1062 simplemap_get_mappers(worker.simplemap_mappers);
1063
1064 std::vector<std::string> map_files;
1065 std::string verilog_frontend = "verilog -nooverwrite -noblackbox";
1066 int max_iter = -1;
1067
1068 size_t argidx;
1069 for (argidx = 1; argidx < args.size(); argidx++) {
1070 if (args[argidx] == "-map" && argidx+1 < args.size()) {
1071 map_files.push_back(args[++argidx]);
1072 continue;
1073 }
1074 if (args[argidx] == "-max_iter" && argidx+1 < args.size()) {
1075 max_iter = atoi(args[++argidx].c_str());
1076 continue;
1077 }
1078 if (args[argidx] == "-D" && argidx+1 < args.size()) {
1079 verilog_frontend += " -D " + args[++argidx];
1080 continue;
1081 }
1082 if (args[argidx] == "-I" && argidx+1 < args.size()) {
1083 verilog_frontend += " -I " + args[++argidx];
1084 continue;
1085 }
1086 if (args[argidx] == "-assert") {
1087 worker.assert_mode = true;
1088 continue;
1089 }
1090 if (args[argidx] == "-extern") {
1091 worker.extern_mode = true;
1092 continue;
1093 }
1094 if (args[argidx] == "-recursive") {
1095 worker.recursive_mode = true;
1096 continue;
1097 }
1098 if (args[argidx] == "-autoproc") {
1099 worker.autoproc_mode = true;
1100 continue;
1101 }
1102 if (args[argidx] == "-wb") {
1103 worker.ignore_wb = true;
1104 continue;
1105 }
1106 break;
1107 }
1108 extra_args(args, argidx, design);
1109
1110 RTLIL::Design *map = new RTLIL::Design;
1111 if (map_files.empty()) {
1112 std::istringstream f(stdcells_code);
1113 Frontend::frontend_call(map, &f, "<techmap.v>", verilog_frontend);
1114 } else {
1115 for (auto &fn : map_files)
1116 if (fn.compare(0, 1, "%") == 0) {
1117 if (!saved_designs.count(fn.substr(1))) {
1118 delete map;
1119 log_cmd_error("Can't saved design `%s'.\n", fn.c_str()+1);
1120 }
1121 for (auto mod : saved_designs.at(fn.substr(1))->modules())
1122 if (!map->has(mod->name))
1123 map->add(mod->clone());
1124 } else {
1125 std::ifstream f;
1126 rewrite_filename(fn);
1127 f.open(fn.c_str());
1128 yosys_input_files.insert(fn);
1129 if (f.fail())
1130 log_cmd_error("Can't open map file `%s'\n", fn.c_str());
1131 Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend));
1132 }
1133 }
1134
1135 log_header(design, "Continuing TECHMAP pass.\n");
1136
1137 std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
1138 for (auto &it : map->modules_) {
1139 if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) {
1140 char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str());
1141 for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
1142 celltypeMap[RTLIL::escape_id(q)].insert(it.first);
1143 free(p);
1144 } else {
1145 string module_name = it.first.str();
1146 if (it.first.begins_with("\\$"))
1147 module_name = module_name.substr(1);
1148 celltypeMap[module_name].insert(it.first);
1149 }
1150 }
1151
1152 for (auto module : design->modules())
1153 worker.module_queue.insert(module);
1154
1155 while (!worker.module_queue.empty())
1156 {
1157 RTLIL::Module *module = *worker.module_queue.begin();
1158 worker.module_queue.erase(module);
1159
1160 bool did_something = true;
1161 std::set<RTLIL::Cell*> handled_cells;
1162 while (did_something) {
1163 did_something = false;
1164 if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
1165 did_something = true;
1166 if (did_something)
1167 module->check();
1168 if (max_iter > 0 && --max_iter == 0)
1169 break;
1170 }
1171 }
1172
1173 log("No more expansions possible.\n");
1174 delete map;
1175
1176 log_pop();
1177 }
1178 } TechmapPass;
1179
1180 struct FlattenPass : public Pass {
1181 FlattenPass() : Pass("flatten", "flatten design") { }
1182 void help() YS_OVERRIDE
1183 {
1184 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1185 log("\n");
1186 log(" flatten [options] [selection]\n");
1187 log("\n");
1188 log("This pass flattens the design by replacing cells by their implementation. This\n");
1189 log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
1190 log("pass is using the current design as mapping library.\n");
1191 log("\n");
1192 log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
1193 log("flattened by this command.\n");
1194 log("\n");
1195 log(" -wb\n");
1196 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
1197 log("\n");
1198 }
1199 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1200 {
1201 log_header(design, "Executing FLATTEN pass (flatten design).\n");
1202 log_push();
1203
1204 TechmapWorker worker;
1205 worker.flatten_mode = true;
1206
1207 size_t argidx;
1208 for (argidx = 1; argidx < args.size(); argidx++) {
1209 if (args[argidx] == "-wb") {
1210 worker.ignore_wb = true;
1211 continue;
1212 }
1213 break;
1214 }
1215 extra_args(args, argidx, design);
1216
1217
1218 std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
1219 for (auto module : design->modules())
1220 celltypeMap[module->name].insert(module->name);
1221
1222 RTLIL::Module *top_mod = NULL;
1223 if (design->full_selection())
1224 for (auto mod : design->modules())
1225 if (mod->get_bool_attribute("\\top"))
1226 top_mod = mod;
1227
1228 std::set<RTLIL::Cell*> handled_cells;
1229 if (top_mod != NULL) {
1230 worker.flatten_do_list.insert(top_mod->name);
1231 while (!worker.flatten_do_list.empty()) {
1232 auto mod = design->module(*worker.flatten_do_list.begin());
1233 while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
1234 worker.flatten_done_list.insert(mod->name);
1235 worker.flatten_do_list.erase(mod->name);
1236 }
1237 } else {
1238 for (auto mod : vector<Module*>(design->modules())) {
1239 while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
1240 }
1241 }
1242
1243 log_suppressed();
1244 log("No more expansions possible.\n");
1245
1246 if (top_mod != NULL)
1247 {
1248 pool<RTLIL::IdString> used_modules, new_used_modules;
1249 new_used_modules.insert(top_mod->name);
1250 while (!new_used_modules.empty()) {
1251 pool<RTLIL::IdString> queue;
1252 queue.swap(new_used_modules);
1253 for (auto modname : queue)
1254 used_modules.insert(modname);
1255 for (auto modname : queue)
1256 for (auto cell : design->module(modname)->cells())
1257 if (design->module(cell->type) && !used_modules[cell->type])
1258 new_used_modules.insert(cell->type);
1259 }
1260
1261 dict<RTLIL::IdString, RTLIL::Module*> new_modules;
1262 for (auto mod : vector<Module*>(design->modules()))
1263 if (used_modules[mod->name] || mod->get_blackbox_attribute(worker.ignore_wb)) {
1264 new_modules[mod->name] = mod;
1265 } else {
1266 log("Deleting now unused module %s.\n", log_id(mod));
1267 delete mod;
1268 }
1269 design->modules_.swap(new_modules);
1270 }
1271
1272 log_pop();
1273 }
1274 } FlattenPass;
1275
1276 PRIVATE_NAMESPACE_END