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techmap: remove dead variable. NFC.
[yosys.git] / passes / techmap / techmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/utils.h"
22 #include "kernel/sigtools.h"
23 #include "libs/sha1/sha1.h"
24
25 #include <stdlib.h>
26 #include <stdio.h>
27 #include <string.h>
28
29 #include "simplemap.h"
30
31 YOSYS_NAMESPACE_BEGIN
32
33 // see maccmap.cc
34 extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false);
35
36 YOSYS_NAMESPACE_END
37
38 USING_YOSYS_NAMESPACE
39 PRIVATE_NAMESPACE_BEGIN
40
41 void apply_prefix(IdString prefix, IdString &id)
42 {
43 if (id[0] == '\\')
44 id = stringf("%s.%s", prefix.c_str(), id.c_str()+1);
45 else
46 id = stringf("$techmap%s.%s", prefix.c_str(), id.c_str());
47 }
48
49 void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
50 {
51 vector<SigChunk> chunks = sig;
52 for (auto &chunk : chunks)
53 if (chunk.wire != nullptr) {
54 IdString wire_name = chunk.wire->name;
55 apply_prefix(prefix, wire_name);
56 log_assert(module->wire(wire_name) != nullptr);
57 chunk.wire = module->wire(wire_name);
58 }
59 sig = chunks;
60 }
61
62 struct TechmapWorker
63 {
64 dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
65 dict<std::pair<IdString, dict<IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
66 dict<RTLIL::Module*, bool> techmap_do_cache;
67 pool<RTLIL::Module*> module_queue;
68 dict<Module*, SigMap> sigmaps;
69
70 pool<IdString> flatten_do_list;
71 pool<IdString> flatten_done_list;
72 pool<Cell*> flatten_keep_list;
73
74 pool<string> log_msg_cache;
75
76 struct TechmapWireData {
77 RTLIL::Wire *wire;
78 RTLIL::SigSpec value;
79 };
80
81 typedef dict<IdString, std::vector<TechmapWireData>> TechmapWires;
82
83 bool extern_mode = false;
84 bool assert_mode = false;
85 bool flatten_mode = false;
86 bool recursive_mode = false;
87 bool autoproc_mode = false;
88 bool ignore_wb = false;
89
90 std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose)
91 {
92 std::string constmap_info;
93 dict<RTLIL::SigBit, std::pair<IdString, int>> connbits_map;
94
95 for (auto &conn : cell->connections())
96 for (int i = 0; i < GetSize(conn.second); i++) {
97 RTLIL::SigBit bit = sigmap(conn.second[i]);
98 if (bit.wire == nullptr) {
99 if (verbose)
100 log(" Constant input on bit %d of port %s: %s\n", i, log_id(conn.first), log_signal(bit));
101 constmap_info += stringf("|%s %d %d", log_id(conn.first), i, bit.data);
102 } else if (connbits_map.count(bit)) {
103 if (verbose)
104 log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, log_id(conn.first),
105 connbits_map.at(bit).second, log_id(connbits_map.at(bit).first));
106 constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i,
107 log_id(connbits_map.at(bit).first), connbits_map.at(bit).second);
108 } else {
109 connbits_map.emplace(bit, std::make_pair(conn.first, i));
110 constmap_info += stringf("|%s %d", log_id(conn.first), i);
111 }
112 }
113
114 return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str());
115 }
116
117 TechmapWires techmap_find_special_wires(RTLIL::Module *module)
118 {
119 TechmapWires result;
120
121 if (module == nullptr)
122 return result;
123
124 for (auto w : module->wires()) {
125 const char *p = w->name.c_str();
126 if (*p == '$')
127 continue;
128
129 const char *q = strrchr(p+1, '.');
130 if (q)
131 p = q;
132
133 if (!strncmp(p, "\\_TECHMAP_", 10)) {
134 TechmapWireData record;
135 record.wire = w;
136 record.value = w;
137 result[p].push_back(record);
138 w->set_bool_attribute(ID::keep);
139 w->set_bool_attribute(ID::_techmap_special_);
140 }
141 }
142
143 if (!result.empty()) {
144 SigMap sigmap(module);
145 for (auto &it1 : result)
146 for (auto &it2 : it1.second)
147 sigmap.apply(it2.value);
148 }
149
150 return result;
151 }
152
153 void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl)
154 {
155 if (tpl->processes.size() != 0) {
156 log("Technology map yielded processes:");
157 for (auto &it : tpl->processes)
158 log(" %s",log_id(it.first));
159 log("\n");
160 if (autoproc_mode) {
161 Pass::call_on_module(tpl->design, tpl, "proc");
162 log_assert(GetSize(tpl->processes) == 0);
163 } else
164 log_error("Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).\n");
165 }
166
167 std::string orig_cell_name;
168 pool<string> extra_src_attrs = cell->get_strpool_attribute(ID::src);
169
170 orig_cell_name = cell->name.str();
171 if (!flatten_mode) {
172 for (auto tpl_cell : tpl->cells())
173 if (tpl_cell->name == ID::_TECHMAP_REPLACE_) {
174 module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
175 break;
176 }
177 }
178
179 dict<IdString, IdString> memory_renames;
180
181 for (auto &it : tpl->memories) {
182 IdString m_name = it.first;
183 apply_prefix(cell->name, m_name);
184 RTLIL::Memory *m = new RTLIL::Memory;
185 m->name = m_name;
186 m->width = it.second->width;
187 m->start_offset = it.second->start_offset;
188 m->size = it.second->size;
189 m->attributes = it.second->attributes;
190 if (m->attributes.count(ID::src))
191 m->add_strpool_attribute(ID::src, extra_src_attrs);
192 module->memories[m->name] = m;
193 memory_renames[it.first] = m->name;
194 design->select(module, m);
195 }
196
197 dict<IdString, IdString> positional_ports;
198 dict<Wire*, IdString> temp_renamed_wires;
199 pool<SigBit> autopurge_tpl_bits;
200
201 for (auto tpl_w : tpl->wires())
202 {
203 if (tpl_w->port_id > 0)
204 {
205 IdString posportname = stringf("$%d", tpl_w->port_id);
206 positional_ports.emplace(posportname, tpl_w->name);
207
208 if (!flatten_mode && tpl_w->get_bool_attribute(ID::techmap_autopurge) &&
209 (!cell->hasPort(tpl_w->name) || !GetSize(cell->getPort(tpl_w->name))) &&
210 (!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname))))
211 {
212 if (sigmaps.count(tpl) == 0)
213 sigmaps[tpl].set(tpl);
214
215 for (auto bit : sigmaps.at(tpl)(tpl_w))
216 if (bit.wire != nullptr)
217 autopurge_tpl_bits.insert(bit);
218 }
219 }
220 IdString w_name = tpl_w->name;
221 apply_prefix(cell->name, w_name);
222 RTLIL::Wire *w = module->wire(w_name);
223 if (w != nullptr) {
224 if (!flatten_mode || !w->get_bool_attribute(ID::hierconn)) {
225 temp_renamed_wires[w] = w->name;
226 module->rename(w, NEW_ID);
227 w = nullptr;
228 } else {
229 w->attributes.erase(ID::hierconn);
230 if (GetSize(w) < GetSize(tpl_w)) {
231 log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w),
232 log_id(tpl), log_id(tpl_w), log_id(module), log_id(cell));
233 w->width = GetSize(tpl_w);
234 }
235 }
236 }
237 if (w == nullptr) {
238 w = module->addWire(w_name, tpl_w);
239 w->port_input = false;
240 w->port_output = false;
241 w->port_id = 0;
242 if (!flatten_mode)
243 w->attributes.erase(ID::techmap_autopurge);
244 if (tpl_w->get_bool_attribute(ID::_techmap_special_))
245 w->attributes.clear();
246 if (w->attributes.count(ID::src))
247 w->add_strpool_attribute(ID::src, extra_src_attrs);
248 }
249 design->select(module, w);
250
251 if (tpl_w->name.begins_with("\\_TECHMAP_REPLACE_.")) {
252 IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), tpl_w->name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
253 Wire *replace_w = module->addWire(replace_name, tpl_w);
254 module->connect(replace_w, w);
255 }
256 }
257
258 SigMap tpl_sigmap(tpl);
259 pool<SigBit> tpl_written_bits;
260
261 for (auto tpl_cell : tpl->cells())
262 for (auto &conn : tpl_cell->connections())
263 if (tpl_cell->output(conn.first))
264 for (auto bit : tpl_sigmap(conn.second))
265 tpl_written_bits.insert(bit);
266 for (auto &conn : tpl->connections())
267 for (auto bit : tpl_sigmap(conn.first))
268 tpl_written_bits.insert(bit);
269
270 SigMap port_signal_map;
271
272 for (auto &it : cell->connections())
273 {
274 IdString portname = it.first;
275 if (positional_ports.count(portname) > 0)
276 portname = positional_ports.at(portname);
277 if (tpl->wire(portname) == nullptr || tpl->wire(portname)->port_id == 0) {
278 if (portname.begins_with("$"))
279 log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
280 continue;
281 }
282
283 if (GetSize(it.second) == 0)
284 continue;
285
286 RTLIL::Wire *w = tpl->wire(portname);
287 RTLIL::SigSig c, extra_connect;
288
289 if (w->port_output && !w->port_input) {
290 c.first = it.second;
291 c.second = RTLIL::SigSpec(w);
292 apply_prefix(cell->name, c.second, module);
293 extra_connect.first = c.second;
294 extra_connect.second = c.first;
295 } else if (!w->port_output && w->port_input) {
296 c.first = RTLIL::SigSpec(w);
297 c.second = it.second;
298 apply_prefix(cell->name, c.first, module);
299 extra_connect.first = c.first;
300 extra_connect.second = c.second;
301 } else {
302 SigSpec sig_tpl = w, sig_tpl_pf = w, sig_mod = it.second;
303 apply_prefix(cell->name, sig_tpl_pf, module);
304 for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) {
305 if (tpl_written_bits.count(tpl_sigmap(sig_tpl[i]))) {
306 c.first.append(sig_mod[i]);
307 c.second.append(sig_tpl_pf[i]);
308 } else {
309 c.first.append(sig_tpl_pf[i]);
310 c.second.append(sig_mod[i]);
311 }
312 }
313 extra_connect.first = sig_tpl_pf;
314 extra_connect.second = sig_mod;
315 }
316
317 if (c.second.size() > c.first.size())
318 c.second.remove(c.first.size(), c.second.size() - c.first.size());
319
320 if (c.second.size() < c.first.size())
321 c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
322
323 log_assert(c.first.size() == c.second.size());
324
325 if (flatten_mode)
326 {
327 // more conservative approach:
328 // connect internal and external wires
329
330 if (sigmaps.count(module) == 0)
331 sigmaps[module].set(module);
332
333 if (sigmaps.at(module)(c.first).has_const())
334 log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
335 log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second));
336
337 module->connect(c);
338 }
339 else
340 {
341 // approach that yields nicer outputs:
342 // replace internal wires that are connected to external wires
343
344 if (w->port_output && !w->port_input) {
345 port_signal_map.add(c.second, c.first);
346 } else
347 if (!w->port_output && w->port_input) {
348 port_signal_map.add(c.first, c.second);
349 } else {
350 module->connect(c);
351 extra_connect = SigSig();
352 }
353
354 for (auto &attr : w->attributes) {
355 if (attr.first == ID::src)
356 continue;
357 auto lhs = GetSize(extra_connect.first);
358 auto rhs = GetSize(extra_connect.second);
359 if (lhs > rhs)
360 extra_connect.first.remove(rhs, lhs-rhs);
361 else if (rhs > lhs)
362 extra_connect.second.remove(lhs, rhs-lhs);
363 module->connect(extra_connect);
364 break;
365 }
366 }
367 }
368
369 for (auto tpl_cell : tpl->cells())
370 {
371 IdString c_name = tpl_cell->name;
372 bool techmap_replace_cell = (!flatten_mode) && (c_name == ID::_TECHMAP_REPLACE_);
373
374 if (techmap_replace_cell)
375 c_name = orig_cell_name;
376 else if (tpl_cell->name.begins_with("\\_TECHMAP_REPLACE_."))
377 c_name = stringf("%s%s", orig_cell_name.c_str(), c_name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
378 else
379 apply_prefix(cell->name, c_name);
380
381 RTLIL::Cell *c = module->addCell(c_name, tpl_cell);
382 design->select(module, c);
383
384 if (!flatten_mode && c->type.begins_with("\\$"))
385 c->type = c->type.substr(1);
386
387 vector<IdString> autopurge_ports;
388
389 for (auto &conn : c->connections())
390 {
391 bool autopurge = false;
392 if (!autopurge_tpl_bits.empty()) {
393 autopurge = GetSize(conn.second) != 0;
394 for (auto &bit : sigmaps.at(tpl)(conn.second))
395 if (!autopurge_tpl_bits.count(bit)) {
396 autopurge = false;
397 break;
398 }
399 }
400
401 if (autopurge) {
402 autopurge_ports.push_back(conn.first);
403 } else {
404 RTLIL::SigSpec new_conn = conn.second;
405 apply_prefix(cell->name, new_conn, module);
406 port_signal_map.apply(new_conn);
407 c->setPort(conn.first, std::move(new_conn));
408 }
409 }
410
411 for (auto &it2 : autopurge_ports)
412 c->unsetPort(it2);
413
414 if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
415 IdString memid = c->getParam(ID::MEMID).decode_string();
416 log_assert(memory_renames.count(memid) != 0);
417 c->setParam(ID::MEMID, Const(memory_renames[memid].str()));
418 }
419
420 if (c->type == ID($mem)) {
421 IdString memid = c->getParam(ID::MEMID).decode_string();
422 apply_prefix(cell->name, memid);
423 c->setParam(ID::MEMID, Const(memid.c_str()));
424 }
425
426 if (c->attributes.count(ID::src))
427 c->add_strpool_attribute(ID::src, extra_src_attrs);
428
429 if (techmap_replace_cell)
430 for (auto attr : cell->attributes)
431 if (!c->attributes.count(attr.first))
432 c->attributes[attr.first] = attr.second;
433 }
434
435 for (auto &it : tpl->connections()) {
436 RTLIL::SigSig c = it;
437 apply_prefix(cell->name.str(), c.first, module);
438 apply_prefix(cell->name.str(), c.second, module);
439 port_signal_map.apply(c.first);
440 port_signal_map.apply(c.second);
441 module->connect(c);
442 }
443
444 module->remove(cell);
445
446 for (auto &it : temp_renamed_wires)
447 {
448 Wire *w = it.first;
449 IdString name = it.second;
450 IdString altname = module->uniquify(name);
451 Wire *other_w = module->wire(name);
452 module->rename(other_w, altname);
453 module->rename(w, name);
454 }
455 }
456
457 bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool<RTLIL::Cell*> &handled_cells,
458 const dict<IdString, pool<IdString>> &celltypeMap, bool in_recursion)
459 {
460 std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";
461
462 if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb))
463 return false;
464
465 bool log_continue = false;
466 bool did_something = false;
467 LogMakeDebugHdl mkdebug;
468
469 SigMap sigmap(module);
470
471 dict<SigBit, State> init_bits;
472 pool<SigBit> remove_init_bits;
473
474 for (auto wire : module->wires()) {
475 if (wire->attributes.count(ID::init)) {
476 Const value = wire->attributes.at(ID::init);
477 for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
478 if (value[i] != State::Sx)
479 init_bits[sigmap(SigBit(wire, i))] = value[i];
480 }
481 }
482
483 TopoSort<RTLIL::Cell*, IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
484 dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_to_inbit;
485 dict<RTLIL::SigBit, pool<RTLIL::Cell*>> outbit_to_cell;
486
487 for (auto cell : module->selected_cells())
488 {
489 if (handled_cells.count(cell) > 0)
490 continue;
491
492 std::string cell_type = cell->type.str();
493 if (in_recursion && cell->type.begins_with("\\$"))
494 cell_type = cell_type.substr(1);
495
496 if (celltypeMap.count(cell_type) == 0) {
497 if (assert_mode && cell_type.back() != '_')
498 log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type));
499 continue;
500 }
501
502 if (flatten_mode) {
503 bool keepit = cell->get_bool_attribute(ID::keep_hierarchy);
504 for (auto &tpl_name : celltypeMap.at(cell_type))
505 if (map->module(tpl_name)->get_bool_attribute(ID::keep_hierarchy))
506 keepit = true;
507 if (keepit) {
508 if (!flatten_keep_list[cell]) {
509 log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell));
510 flatten_keep_list.insert(cell);
511 }
512 if (!flatten_done_list[cell->type])
513 flatten_do_list.insert(cell->type);
514 continue;
515 }
516 }
517
518 for (auto &conn : cell->connections())
519 {
520 RTLIL::SigSpec sig = sigmap(conn.second);
521 sig.remove_const();
522
523 if (GetSize(sig) == 0)
524 continue;
525
526 for (auto &tpl_name : celltypeMap.at(cell_type)) {
527 RTLIL::Module *tpl = map->module(tpl_name);
528 RTLIL::Wire *port = tpl->wire(conn.first);
529 if (port && port->port_input)
530 cell_to_inbit[cell].insert(sig.begin(), sig.end());
531 if (port && port->port_output)
532 for (auto &bit : sig)
533 outbit_to_cell[bit].insert(cell);
534 }
535 }
536
537 cells.node(cell);
538 }
539
540 for (auto &it_right : cell_to_inbit)
541 for (auto &it_sigbit : it_right.second)
542 for (auto &it_left : outbit_to_cell[it_sigbit])
543 cells.edge(it_left, it_right.first);
544
545 cells.sort();
546
547 for (auto cell : cells.sorted)
548 {
549 log_assert(handled_cells.count(cell) == 0);
550 log_assert(cell == module->cell(cell->name));
551 bool mapped_cell = false;
552
553 std::string cell_type = cell->type.str();
554
555 if (in_recursion && cell->type.begins_with("\\$"))
556 cell_type = cell_type.substr(1);
557
558 for (auto &tpl_name : celltypeMap.at(cell_type))
559 {
560 IdString derived_name = tpl_name;
561 RTLIL::Module *tpl = map->module(tpl_name);
562 dict<IdString, RTLIL::Const> parameters(cell->parameters);
563
564 if (tpl->get_blackbox_attribute(ignore_wb))
565 continue;
566
567 if (!flatten_mode)
568 {
569 std::string extmapper_name;
570
571 if (tpl->get_bool_attribute(ID::techmap_simplemap))
572 extmapper_name = "simplemap";
573
574 if (tpl->get_bool_attribute(ID::techmap_maccmap))
575 extmapper_name = "maccmap";
576
577 if (tpl->attributes.count(ID::techmap_wrap))
578 extmapper_name = "wrap";
579
580 if (!extmapper_name.empty())
581 {
582 cell->type = cell_type;
583
584 if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
585 {
586 std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
587
588 for (auto &c : cell->parameters)
589 m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
590
591 if (extmapper_name == "wrap")
592 m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string());
593
594 RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
595 RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
596
597 if (extmapper_module == nullptr)
598 {
599 extmapper_module = extmapper_design->addModule(m_name);
600 RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
601
602 extmapper_cell->set_src_attribute(cell->get_src_attribute());
603
604 int port_counter = 1;
605 for (auto &c : extmapper_cell->connections_) {
606 RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
607 if (w->name.in(ID::Y, ID::Q))
608 w->port_output = true;
609 else
610 w->port_input = true;
611 w->port_id = port_counter++;
612 c.second = w;
613 }
614
615 extmapper_module->fixup_ports();
616 extmapper_module->check();
617
618 if (extmapper_name == "simplemap") {
619 log("Creating %s with simplemap.\n", log_id(extmapper_module));
620 if (simplemap_mappers.count(extmapper_cell->type) == 0)
621 log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
622 simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
623 extmapper_module->remove(extmapper_cell);
624 }
625
626 if (extmapper_name == "maccmap") {
627 log("Creating %s with maccmap.\n", log_id(extmapper_module));
628 if (extmapper_cell->type != ID($macc))
629 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
630 maccmap(extmapper_module, extmapper_cell);
631 extmapper_module->remove(extmapper_cell);
632 }
633
634 if (extmapper_name == "wrap") {
635 std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string();
636 log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
637 mkdebug.on();
638 Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
639 log_continue = true;
640 }
641 }
642
643 cell->type = extmapper_module->name;
644 cell->parameters.clear();
645
646 if (!extern_mode || in_recursion) {
647 tpl = extmapper_module;
648 goto use_wrapper_tpl;
649 }
650
651 auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
652 if (!log_msg_cache.count(msg)) {
653 log_msg_cache.insert(msg);
654 log("%s\n", msg.c_str());
655 }
656 log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
657 }
658 else
659 {
660 auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type));
661 if (!log_msg_cache.count(msg)) {
662 log_msg_cache.insert(msg);
663 log("%s\n", msg.c_str());
664 }
665 log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
666
667 if (extmapper_name == "simplemap") {
668 if (simplemap_mappers.count(cell->type) == 0)
669 log_error("No simplemap mapper for cell type %s found!\n", log_id(cell->type));
670 simplemap_mappers.at(cell->type)(module, cell);
671 }
672
673 if (extmapper_name == "maccmap") {
674 if (cell->type != ID($macc))
675 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
676 maccmap(module, cell);
677 }
678
679 module->remove(cell);
680 cell = nullptr;
681 }
682
683 did_something = true;
684 mapped_cell = true;
685 break;
686 }
687
688 for (auto &conn : cell->connections()) {
689 if (conn.first.begins_with("$"))
690 continue;
691 if (tpl->wire(conn.first) != nullptr && tpl->wire(conn.first)->port_id > 0)
692 continue;
693 if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
694 goto next_tpl;
695 parameters[conn.first] = conn.second.as_const();
696 }
697
698 if (0) {
699 next_tpl:
700 continue;
701 }
702
703 if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0)
704 parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type));
705
706 for (auto &conn : cell->connections()) {
707 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) {
708 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
709 for (auto &bit : v)
710 bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0);
711 parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
712 }
713 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) {
714 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
715 for (auto &bit : v)
716 if (bit.wire != nullptr)
717 bit = RTLIL::SigBit(RTLIL::State::Sx);
718 parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
719 }
720 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) {
721 auto sig = sigmap(conn.second);
722 RTLIL::Const value(State::Sx, sig.size());
723 for (int i = 0; i < sig.size(); i++) {
724 auto it = init_bits.find(sig[i]);
725 if (it != init_bits.end()) {
726 value[i] = it->second;
727 }
728 }
729 parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), value);
730 }
731 }
732
733 int unique_bit_id_counter = 0;
734 dict<RTLIL::SigBit, int> unique_bit_id;
735 unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++;
736 unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++;
737 unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++;
738 unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
739
740 for (auto &conn : cell->connections())
741 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) {
742 for (auto &bit : sigmap(conn.second))
743 if (unique_bit_id.count(bit) == 0)
744 unique_bit_id[bit] = unique_bit_id_counter++;
745 }
746
747 // Find highest bit set
748 int bits = 0;
749 for (int i = 0; i < 32; i++)
750 if (((unique_bit_id_counter-1) & (1 << i)) != 0)
751 bits = i;
752 // Increment index by one to get number of bits
753 bits++;
754 if (tpl->avail_parameters.count(ID::_TECHMAP_BITS_CONNMAP_))
755 parameters[ID::_TECHMAP_BITS_CONNMAP_] = bits;
756
757 for (auto &conn : cell->connections())
758 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) {
759 RTLIL::Const value;
760 for (auto &bit : sigmap(conn.second)) {
761 int val = unique_bit_id.at(bit);
762 for (int i = 0; i < bits; i++) {
763 value.bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
764 val = val >> 1;
765 }
766 }
767 parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first)), value);
768 }
769 }
770
771 if (0) {
772 use_wrapper_tpl:;
773 // do not register techmap_wrap modules with techmap_cache
774 } else {
775 std::pair<IdString, dict<IdString, RTLIL::Const>> key(tpl_name, parameters);
776 auto it = techmap_cache.find(key);
777 if (it != techmap_cache.end()) {
778 tpl = it->second;
779 } else {
780 if (parameters.size() != 0) {
781 mkdebug.on();
782 derived_name = tpl->derive(map, parameters);
783 tpl = map->module(derived_name);
784 log_continue = true;
785 }
786 techmap_cache.emplace(std::move(key), tpl);
787 }
788 }
789
790 if (flatten_mode) {
791 techmap_do_cache[tpl] = true;
792 } else {
793 RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false));
794 if (constmapped_tpl != nullptr)
795 tpl = constmapped_tpl;
796 }
797
798 if (techmap_do_cache.count(tpl) == 0)
799 {
800 bool keep_running = true;
801 techmap_do_cache[tpl] = true;
802
803 pool<IdString> techmap_wire_names;
804
805 while (keep_running)
806 {
807 TechmapWires twd = techmap_find_special_wires(tpl);
808 keep_running = false;
809
810 for (auto &it : twd)
811 techmap_wire_names.insert(it.first);
812
813 for (auto &it : twd[ID::_TECHMAP_FAIL_]) {
814 RTLIL::SigSpec value = it.value;
815 if (value.is_fully_const() && value.as_bool()) {
816 log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
817 derived_name.c_str(), log_id(it.wire->name), log_signal(value));
818 techmap_do_cache[tpl] = false;
819 }
820 }
821
822 if (!techmap_do_cache[tpl])
823 break;
824
825 for (auto &it : twd)
826 {
827 if (!it.first.begins_with("\\_TECHMAP_DO_") || it.second.empty())
828 continue;
829
830 auto &data = it.second.front();
831
832 if (!data.value.is_fully_const())
833 log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(data.wire->name), log_signal(data.value));
834
835 techmap_wire_names.erase(it.first);
836
837 const char *p = data.wire->name.c_str();
838 const char *q = strrchr(p+1, '.');
839 q = q ? q : p+1;
840
841 std::string cmd_string = data.value.as_const().decode_string();
842
843 restart_eval_cmd_string:
844 if (cmd_string.rfind("CONSTMAP; ", 0) == 0)
845 {
846 cmd_string = cmd_string.substr(strlen("CONSTMAP; "));
847
848 log("Analyzing pattern of constant bits for this cell:\n");
849 IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
850 log("Creating constmapped module `%s'.\n", log_id(new_tpl_name));
851 log_assert(map->module(new_tpl_name) == nullptr);
852
853 RTLIL::Module *new_tpl = map->addModule(new_tpl_name);
854 tpl->cloneInto(new_tpl);
855
856 techmap_do_cache.erase(tpl);
857 techmap_do_cache[new_tpl] = true;
858 tpl = new_tpl;
859
860 dict<RTLIL::SigBit, RTLIL::SigBit> port_new2old_map;
861 dict<RTLIL::SigBit, RTLIL::SigBit> port_connmap;
862 dict<RTLIL::SigBit, RTLIL::SigBit> cellbits_to_tplbits;
863
864 for (auto wire : tpl->wires().to_vector())
865 {
866 if (!wire->port_input || wire->port_output)
867 continue;
868
869 IdString port_name = wire->name;
870 tpl->rename(wire, NEW_ID);
871
872 RTLIL::Wire *new_wire = tpl->addWire(port_name, wire);
873 wire->port_input = false;
874 wire->port_id = 0;
875
876 for (int i = 0; i < wire->width; i++) {
877 port_new2old_map.emplace(RTLIL::SigBit(new_wire, i), RTLIL::SigBit(wire, i));
878 port_connmap.emplace(RTLIL::SigBit(wire, i), RTLIL::SigBit(new_wire, i));
879 }
880 }
881
882 for (auto &conn : cell->connections())
883 for (int i = 0; i < GetSize(conn.second); i++)
884 {
885 RTLIL::SigBit bit = sigmap(conn.second[i]);
886 RTLIL::SigBit tplbit(tpl->wire(conn.first), i);
887
888 if (bit.wire == nullptr)
889 {
890 RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
891 port_connmap.at(oldbit) = bit;
892 }
893 else if (cellbits_to_tplbits.count(bit))
894 {
895 RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
896 port_connmap.at(oldbit) = cellbits_to_tplbits[bit];
897 }
898 else
899 cellbits_to_tplbits[bit] = tplbit;
900 }
901
902 RTLIL::SigSig port_conn;
903 for (auto &it : port_connmap) {
904 port_conn.first.append(it.first);
905 port_conn.second.append(it.second);
906 }
907 tpl->connect(port_conn);
908
909 tpl->check();
910 goto restart_eval_cmd_string;
911 }
912
913 if (cmd_string.rfind("RECURSION; ", 0) == 0)
914 {
915 cmd_string = cmd_string.substr(strlen("RECURSION; "));
916 while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
917 goto restart_eval_cmd_string;
918 }
919
920 Pass::call_on_module(map, tpl, cmd_string);
921
922 log_assert(!strncmp(q, "_TECHMAP_DO_", 12));
923 std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
924 while (tpl->wire(new_name) != nullptr)
925 new_name += "_";
926 tpl->rename(data.wire->name, new_name);
927
928 keep_running = true;
929 break;
930 }
931 }
932
933 TechmapWires twd = techmap_find_special_wires(tpl);
934 for (auto &it : twd) {
935 if (it.first != ID::_TECHMAP_FAIL_ && (!it.first.begins_with("\\_TECHMAP_REMOVEINIT_") || !it.first.ends_with("_")) && !it.first.begins_with("\\_TECHMAP_DO_") && !it.first.begins_with("\\_TECHMAP_DONE_"))
936 log_error("Techmap yielded unknown config wire %s.\n", log_id(it.first));
937 if (techmap_do_cache[tpl])
938 for (auto &it2 : it.second)
939 if (!it2.value.is_fully_const())
940 log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(it2.wire->name), log_signal(it2.value));
941 techmap_wire_names.erase(it.first);
942 }
943
944 for (auto &it : techmap_wire_names)
945 log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", log_id(it));
946
947 if (recursive_mode) {
948 if (log_continue) {
949 log_header(design, "Continuing TECHMAP pass.\n");
950 log_continue = false;
951 mkdebug.off();
952 }
953 while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
954 }
955 }
956
957 if (techmap_do_cache.at(tpl) == false)
958 continue;
959
960 if (log_continue) {
961 log_header(design, "Continuing TECHMAP pass.\n");
962 log_continue = false;
963 mkdebug.off();
964 }
965
966 TechmapWires twd = techmap_find_special_wires(tpl);
967 for (auto &it : twd) {
968 if (it.first.begins_with("\\_TECHMAP_REMOVEINIT_")) {
969 for (auto &it2 : it.second) {
970 auto val = it2.value.as_const();
971 auto wirename = RTLIL::escape_id(it.first.substr(21, it.first.size() - 21 - 1));
972 auto it = cell->connections().find(wirename);
973 if (it != cell->connections().end()) {
974 auto sig = sigmap(it->second);
975 for (int i = 0; i < sig.size(); i++)
976 if (val[i] == State::S1)
977 remove_init_bits.insert(sig[i]);
978 }
979 }
980 }
981 }
982
983 if (extern_mode && !in_recursion)
984 {
985 std::string m_name = stringf("$extern:%s", log_id(tpl));
986
987 if (!design->module(m_name))
988 {
989 RTLIL::Module *m = design->addModule(m_name);
990 tpl->cloneInto(m);
991
992 for (auto cell : m->cells()) {
993 if (cell->type.begins_with("\\$"))
994 cell->type = cell->type.substr(1);
995 }
996
997 module_queue.insert(m);
998 }
999
1000 log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name));
1001 cell->type = m_name;
1002 cell->parameters.clear();
1003 }
1004 else
1005 {
1006 auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type));
1007 if (!log_msg_cache.count(msg)) {
1008 log_msg_cache.insert(msg);
1009 log("%s\n", msg.c_str());
1010 }
1011 log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl));
1012 techmap_module_worker(design, module, cell, tpl);
1013 cell = nullptr;
1014 }
1015 did_something = true;
1016 mapped_cell = true;
1017 break;
1018 }
1019
1020 if (assert_mode && !mapped_cell)
1021 log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
1022
1023 handled_cells.insert(cell);
1024 }
1025
1026 if (!remove_init_bits.empty()) {
1027 for (auto wire : module->wires())
1028 if (wire->attributes.count(ID::init)) {
1029 Const &value = wire->attributes.at(ID::init);
1030 bool do_cleanup = true;
1031 for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
1032 SigBit bit = sigmap(SigBit(wire, i));
1033 if (remove_init_bits.count(bit))
1034 value[i] = State::Sx;
1035 else if (value[i] != State::Sx)
1036 do_cleanup = false;
1037 }
1038 if (do_cleanup) {
1039 log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
1040 wire->attributes.erase(ID::init);
1041 }
1042 }
1043 }
1044
1045 if (log_continue) {
1046 log_header(design, "Continuing TECHMAP pass.\n");
1047 log_continue = false;
1048 mkdebug.off();
1049 }
1050
1051 return did_something;
1052 }
1053 };
1054
1055 struct TechmapPass : public Pass {
1056 TechmapPass() : Pass("techmap", "generic technology mapper") { }
1057 void help() YS_OVERRIDE
1058 {
1059 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1060 log("\n");
1061 log(" techmap [-map filename] [selection]\n");
1062 log("\n");
1063 log("This pass implements a very simple technology mapper that replaces cells in\n");
1064 log("the design with implementations given in form of a Verilog or ilang source\n");
1065 log("file.\n");
1066 log("\n");
1067 log(" -map filename\n");
1068 log(" the library of cell implementations to be used.\n");
1069 log(" without this parameter a builtin library is used that\n");
1070 log(" transforms the internal RTL cells to the internal gate\n");
1071 log(" library.\n");
1072 log("\n");
1073 log(" -map %%<design-name>\n");
1074 log(" like -map above, but with an in-memory design instead of a file.\n");
1075 log("\n");
1076 log(" -extern\n");
1077 log(" load the cell implementations as separate modules into the design\n");
1078 log(" instead of inlining them.\n");
1079 log("\n");
1080 log(" -max_iter <number>\n");
1081 log(" only run the specified number of iterations on each module.\n");
1082 log(" default: unlimited\n");
1083 log("\n");
1084 log(" -recursive\n");
1085 log(" instead of the iterative breadth-first algorithm use a recursive\n");
1086 log(" depth-first algorithm. both methods should yield equivalent results,\n");
1087 log(" but may differ in performance.\n");
1088 log("\n");
1089 log(" -autoproc\n");
1090 log(" Automatically call \"proc\" on implementations that contain processes.\n");
1091 log("\n");
1092 log(" -wb\n");
1093 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
1094 log("\n");
1095 log(" -assert\n");
1096 log(" this option will cause techmap to exit with an error if it can't map\n");
1097 log(" a selected cell. only cell types that end on an underscore are accepted\n");
1098 log(" as final cell types by this mode.\n");
1099 log("\n");
1100 log(" -D <define>, -I <incdir>\n");
1101 log(" this options are passed as-is to the Verilog frontend for loading the\n");
1102 log(" map file. Note that the Verilog frontend is also called with the\n");
1103 log(" '-nooverwrite' option set.\n");
1104 log("\n");
1105 log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
1106 log("match cells with a type that match the text value of this attribute. Otherwise\n");
1107 log("the module name will be used to match the cell.\n");
1108 log("\n");
1109 log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
1110 log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
1111 log("\n");
1112 log("When a module in the map file has the 'techmap_maccmap' attribute set, techmap\n");
1113 log("will use 'maccmap' (see 'help maccmap') to map cells matching the module.\n");
1114 log("\n");
1115 log("When a module in the map file has the 'techmap_wrap' attribute set, techmap\n");
1116 log("will create a wrapper for the cell and then run the command string that the\n");
1117 log("attribute is set to on the wrapper module.\n");
1118 log("\n");
1119 log("When a port on a module in the map file has the 'techmap_autopurge' attribute\n");
1120 log("set, and that port is not connected in the instantiation that is mapped, then\n");
1121 log("then a cell port connected only to such wires will be omitted in the mapped\n");
1122 log("version of the circuit.\n");
1123 log("\n");
1124 log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
1125 log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
1126 log("the mapping module to the techmap command. At the moment the following special\n");
1127 log("wires are supported:\n");
1128 log("\n");
1129 log(" _TECHMAP_FAIL_\n");
1130 log(" When this wire is set to a non-zero constant value, techmap will not\n");
1131 log(" use this module and instead try the next module with a matching\n");
1132 log(" 'techmap_celltype' attribute.\n");
1133 log("\n");
1134 log(" When such a wire exists but does not have a constant value after all\n");
1135 log(" _TECHMAP_DO_* commands have been executed, an error is generated.\n");
1136 log("\n");
1137 log(" _TECHMAP_DO_*\n");
1138 log(" This wires are evaluated in alphabetical order. The constant text value\n");
1139 log(" of this wire is a yosys command (or sequence of commands) that is run\n");
1140 log(" by techmap on the module. A common use case is to run 'proc' on modules\n");
1141 log(" that are written using always-statements.\n");
1142 log("\n");
1143 log(" When such a wire has a non-constant value at the time it is to be\n");
1144 log(" evaluated, an error is produced. That means it is possible for such a\n");
1145 log(" wire to start out as non-constant and evaluate to a constant value\n");
1146 log(" during processing of other _TECHMAP_DO_* commands.\n");
1147 log("\n");
1148 log(" A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.\n");
1149 log(" in this case techmap will create a copy for each distinct configuration\n");
1150 log(" of constant inputs and shorted inputs at this point and import the\n");
1151 log(" constant and connected bits into the map module. All further commands\n");
1152 log(" are executed in this copy. This is a very convenient way of creating\n");
1153 log(" optimized specializations of techmap modules without using the special\n");
1154 log(" parameters described below.\n");
1155 log("\n");
1156 log(" A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.\n");
1157 log(" then techmap will recursively replace the cells in the module with their\n");
1158 log(" implementation. This is not affected by the -max_iter option.\n");
1159 log("\n");
1160 log(" It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n");
1161 log("\n");
1162 log(" _TECHMAP_REMOVEINIT_<port-name>_\n");
1163 log(" When this wire is set to a constant value, the init attribute of the wire(s)\n");
1164 log(" connected to this port will be consumed. This wire must have the same\n");
1165 log(" width as the given port, and for every bit that is set to 1 in the value,\n");
1166 log(" the corresponding init attribute bit will be changed to 1'bx. If all\n");
1167 log(" bits of an init attribute are left as x, it will be removed.\n");
1168 log("\n");
1169 log("In addition to this special wires, techmap also supports special parameters in\n");
1170 log("modules in the map file:\n");
1171 log("\n");
1172 log(" _TECHMAP_CELLTYPE_\n");
1173 log(" When a parameter with this name exists, it will be set to the type name\n");
1174 log(" of the cell that matches the module.\n");
1175 log("\n");
1176 log(" _TECHMAP_CONSTMSK_<port-name>_\n");
1177 log(" _TECHMAP_CONSTVAL_<port-name>_\n");
1178 log(" When this pair of parameters is available in a module for a port, then\n");
1179 log(" former has a 1-bit for each constant input bit and the latter has the\n");
1180 log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
1181 log("\n");
1182 log(" _TECHMAP_WIREINIT_<port-name>_\n");
1183 log(" When a parameter with this name exists, it will be set to the initial\n");
1184 log(" value of the wire(s) connected to the given port, as specified by the init\n");
1185 log(" attribute. If the attribute doesn't exist, x will be filled for the\n");
1186 log(" missing bits. To remove the init attribute bits used, use the\n");
1187 log(" _TECHMAP_REMOVEINIT_*_ wires.\n");
1188 log("\n");
1189 log(" _TECHMAP_BITS_CONNMAP_\n");
1190 log(" _TECHMAP_CONNMAP_<port-name>_\n");
1191 log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
1192 log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n");
1193 log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n");
1194 log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n");
1195 log(" This can be used to detect shorted inputs.\n");
1196 log("\n");
1197 log("When a module in the map file has a parameter where the according cell in the\n");
1198 log("design has a port, the module from the map file is only used if the port in\n");
1199 log("the design is connected to a constant value. The parameter is then set to the\n");
1200 log("constant value.\n");
1201 log("\n");
1202 log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
1203 log("and attributes of the cell that is being replaced.\n");
1204 log("A cell with a name of the form `_TECHMAP_REPLACE_.<suffix>` in the map file will\n");
1205 log("be named thus but with the `_TECHMAP_REPLACE_' prefix substituted with the name\n");
1206 log("of the cell being replaced.\n");
1207 log("Similarly, a wire named in the form `_TECHMAP_REPLACE_.<suffix>` will cause a\n");
1208 log("new wire alias to be created and named as above but with the `_TECHMAP_REPLACE_'\n");
1209 log("prefix also substituted.\n");
1210 log("\n");
1211 log("See 'help extract' for a pass that does the opposite thing.\n");
1212 log("\n");
1213 log("See 'help flatten' for a pass that does flatten the design (which is\n");
1214 log("essentially techmap but using the design itself as map library).\n");
1215 log("\n");
1216 }
1217 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1218 {
1219 log_header(design, "Executing TECHMAP pass (map to technology primitives).\n");
1220 log_push();
1221
1222 TechmapWorker worker;
1223 simplemap_get_mappers(worker.simplemap_mappers);
1224
1225 std::vector<std::string> map_files;
1226 std::string verilog_frontend = "verilog -nooverwrite -noblackbox";
1227 int max_iter = -1;
1228
1229 size_t argidx;
1230 for (argidx = 1; argidx < args.size(); argidx++) {
1231 if (args[argidx] == "-map" && argidx+1 < args.size()) {
1232 map_files.push_back(args[++argidx]);
1233 continue;
1234 }
1235 if (args[argidx] == "-max_iter" && argidx+1 < args.size()) {
1236 max_iter = atoi(args[++argidx].c_str());
1237 continue;
1238 }
1239 if (args[argidx] == "-D" && argidx+1 < args.size()) {
1240 verilog_frontend += " -D " + args[++argidx];
1241 continue;
1242 }
1243 if (args[argidx] == "-I" && argidx+1 < args.size()) {
1244 verilog_frontend += " -I " + args[++argidx];
1245 continue;
1246 }
1247 if (args[argidx] == "-assert") {
1248 worker.assert_mode = true;
1249 continue;
1250 }
1251 if (args[argidx] == "-extern") {
1252 worker.extern_mode = true;
1253 continue;
1254 }
1255 if (args[argidx] == "-recursive") {
1256 worker.recursive_mode = true;
1257 continue;
1258 }
1259 if (args[argidx] == "-autoproc") {
1260 worker.autoproc_mode = true;
1261 continue;
1262 }
1263 if (args[argidx] == "-wb") {
1264 worker.ignore_wb = true;
1265 continue;
1266 }
1267 break;
1268 }
1269 extra_args(args, argidx, design);
1270
1271 RTLIL::Design *map = new RTLIL::Design;
1272 if (map_files.empty()) {
1273 Frontend::frontend_call(map, nullptr, "+/techmap.v", verilog_frontend);
1274 } else {
1275 for (auto &fn : map_files)
1276 if (fn.compare(0, 1, "%") == 0) {
1277 if (!saved_designs.count(fn.substr(1))) {
1278 delete map;
1279 log_cmd_error("Can't open saved design `%s'.\n", fn.c_str()+1);
1280 }
1281 for (auto mod : saved_designs.at(fn.substr(1))->modules())
1282 if (!map->module(mod->name))
1283 map->add(mod->clone());
1284 } else {
1285 Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend));
1286 }
1287 }
1288
1289 log_header(design, "Continuing TECHMAP pass.\n");
1290
1291 dict<IdString, pool<IdString>> celltypeMap;
1292 for (auto module : map->modules()) {
1293 if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).bits.empty()) {
1294 char *p = strdup(module->attributes.at(ID::techmap_celltype).decode_string().c_str());
1295 for (char *q = strtok(p, " \t\r\n"); q; q = strtok(nullptr, " \t\r\n"))
1296 celltypeMap[RTLIL::escape_id(q)].insert(module->name);
1297 free(p);
1298 } else {
1299 IdString module_name = module->name.begins_with("\\$") ?
1300 module->name.substr(1) : module->name.str();
1301 celltypeMap[module_name].insert(module->name);
1302 }
1303 }
1304 for (auto &i : celltypeMap)
1305 i.second.sort(RTLIL::sort_by_id_str());
1306
1307 for (auto module : design->modules())
1308 worker.module_queue.insert(module);
1309
1310 while (!worker.module_queue.empty())
1311 {
1312 RTLIL::Module *module = *worker.module_queue.begin();
1313 worker.module_queue.erase(module);
1314
1315 int module_max_iter = max_iter;
1316 bool did_something = true;
1317 pool<RTLIL::Cell*> handled_cells;
1318 while (did_something) {
1319 did_something = false;
1320 if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
1321 did_something = true;
1322 if (did_something)
1323 module->check();
1324 if (module_max_iter > 0 && --module_max_iter == 0)
1325 break;
1326 }
1327 }
1328
1329 log("No more expansions possible.\n");
1330 delete map;
1331
1332 log_pop();
1333 }
1334 } TechmapPass;
1335
1336 struct FlattenPass : public Pass {
1337 FlattenPass() : Pass("flatten", "flatten design") { }
1338 void help() YS_OVERRIDE
1339 {
1340 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1341 log("\n");
1342 log(" flatten [options] [selection]\n");
1343 log("\n");
1344 log("This pass flattens the design by replacing cells by their implementation. This\n");
1345 log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
1346 log("pass is using the current design as mapping library.\n");
1347 log("\n");
1348 log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
1349 log("flattened by this command.\n");
1350 log("\n");
1351 log(" -wb\n");
1352 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
1353 log("\n");
1354 }
1355 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1356 {
1357 log_header(design, "Executing FLATTEN pass (flatten design).\n");
1358 log_push();
1359
1360 TechmapWorker worker;
1361 worker.flatten_mode = true;
1362
1363 size_t argidx;
1364 for (argidx = 1; argidx < args.size(); argidx++) {
1365 if (args[argidx] == "-wb") {
1366 worker.ignore_wb = true;
1367 continue;
1368 }
1369 break;
1370 }
1371 extra_args(args, argidx, design);
1372
1373
1374 dict<IdString, pool<IdString>> celltypeMap;
1375 for (auto module : design->modules())
1376 celltypeMap[module->name].insert(module->name);
1377 for (auto &i : celltypeMap)
1378 i.second.sort(RTLIL::sort_by_id_str());
1379
1380 RTLIL::Module *top_mod = nullptr;
1381 if (design->full_selection())
1382 for (auto mod : design->modules())
1383 if (mod->get_bool_attribute(ID::top))
1384 top_mod = mod;
1385
1386 pool<RTLIL::Cell*> handled_cells;
1387 if (top_mod != nullptr) {
1388 worker.flatten_do_list.insert(top_mod->name);
1389 while (!worker.flatten_do_list.empty()) {
1390 auto mod = design->module(*worker.flatten_do_list.begin());
1391 while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
1392 worker.flatten_done_list.insert(mod->name);
1393 worker.flatten_do_list.erase(mod->name);
1394 }
1395 } else {
1396 for (auto mod : design->modules().to_vector())
1397 while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
1398 }
1399
1400 log_suppressed();
1401 log("No more expansions possible.\n");
1402
1403 if (top_mod != nullptr)
1404 {
1405 pool<IdString> used_modules, new_used_modules;
1406 new_used_modules.insert(top_mod->name);
1407 while (!new_used_modules.empty()) {
1408 pool<IdString> queue;
1409 queue.swap(new_used_modules);
1410 for (auto modname : queue)
1411 used_modules.insert(modname);
1412 for (auto modname : queue)
1413 for (auto cell : design->module(modname)->cells())
1414 if (design->module(cell->type) && !used_modules[cell->type])
1415 new_used_modules.insert(cell->type);
1416 }
1417
1418 for (auto mod : design->modules().to_vector())
1419 if (!used_modules[mod->name] && !mod->get_blackbox_attribute(worker.ignore_wb)) {
1420 log("Deleting now unused module %s.\n", log_id(mod));
1421 design->remove(mod);
1422 }
1423 }
1424
1425 log_pop();
1426 }
1427 } FlattenPass;
1428
1429 PRIVATE_NAMESPACE_END