2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/utils.h"
22 #include "kernel/sigtools.h"
23 #include "libs/sha1/sha1.h"
29 #include "simplemap.h"
30 #include "passes/techmap/techmap.inc"
35 extern void maccmap(RTLIL::Module
*module
, RTLIL::Cell
*cell
, bool unmap
= false);
40 PRIVATE_NAMESPACE_BEGIN
42 void apply_prefix(IdString prefix
, IdString
&id
)
45 id
= stringf("%s.%s", prefix
.c_str(), id
.c_str()+1);
47 id
= stringf("$techmap%s.%s", prefix
.c_str(), id
.c_str());
50 void apply_prefix(IdString prefix
, RTLIL::SigSpec
&sig
, RTLIL::Module
*module
)
52 vector
<SigChunk
> chunks
= sig
;
53 for (auto &chunk
: chunks
)
54 if (chunk
.wire
!= NULL
) {
55 IdString wire_name
= chunk
.wire
->name
;
56 apply_prefix(prefix
, wire_name
);
57 log_assert(module
->wires_
.count(wire_name
) > 0);
58 chunk
.wire
= module
->wires_
[wire_name
];
65 std::map
<RTLIL::IdString
, void(*)(RTLIL::Module
*, RTLIL::Cell
*)> simplemap_mappers
;
66 std::map
<std::pair
<RTLIL::IdString
, std::map
<RTLIL::IdString
, RTLIL::Const
>>, RTLIL::Module
*> techmap_cache
;
67 std::map
<RTLIL::Module
*, bool> techmap_do_cache
;
68 std::set
<RTLIL::Module
*, RTLIL::IdString::compare_ptr_by_name
<RTLIL::Module
>> module_queue
;
69 dict
<Module
*, SigMap
> sigmaps
;
71 pool
<IdString
> flatten_do_list
;
72 pool
<IdString
> flatten_done_list
;
73 pool
<Cell
*> flatten_keep_list
;
75 pool
<string
> log_msg_cache
;
77 struct TechmapWireData
{
82 typedef std::map
<std::string
, std::vector
<TechmapWireData
>> TechmapWires
;
96 recursive_mode
= false;
97 autoproc_mode
= false;
101 std::string
constmap_tpl_name(SigMap
&sigmap
, RTLIL::Module
*tpl
, RTLIL::Cell
*cell
, bool verbose
)
103 std::string constmap_info
;
104 std::map
<RTLIL::SigBit
, std::pair
<RTLIL::IdString
, int>> connbits_map
;
106 for (auto conn
: cell
->connections())
107 for (int i
= 0; i
< GetSize(conn
.second
); i
++) {
108 RTLIL::SigBit bit
= sigmap(conn
.second
[i
]);
109 if (bit
.wire
== nullptr) {
111 log(" Constant input on bit %d of port %s: %s\n", i
, log_id(conn
.first
), log_signal(bit
));
112 constmap_info
+= stringf("|%s %d %d", log_id(conn
.first
), i
, bit
.data
);
113 } else if (connbits_map
.count(bit
)) {
115 log(" Bit %d of port %s and bit %d of port %s are connected.\n", i
, log_id(conn
.first
),
116 connbits_map
.at(bit
).second
, log_id(connbits_map
.at(bit
).first
));
117 constmap_info
+= stringf("|%s %d %s %d", log_id(conn
.first
), i
,
118 log_id(connbits_map
.at(bit
).first
), connbits_map
.at(bit
).second
);
120 connbits_map
[bit
] = std::pair
<RTLIL::IdString
, int>(conn
.first
, i
);
121 constmap_info
+= stringf("|%s %d", log_id(conn
.first
), i
);
125 return stringf("$paramod$constmap:%s%s", sha1(constmap_info
).c_str(), tpl
->name
.c_str());
128 TechmapWires
techmap_find_special_wires(RTLIL::Module
*module
)
135 for (auto &it
: module
->wires_
) {
136 const char *p
= it
.first
.c_str();
140 const char *q
= strrchr(p
+1, '.');
143 if (!strncmp(p
, "_TECHMAP_", 9)) {
144 TechmapWireData record
;
145 record
.wire
= it
.second
;
146 record
.value
= it
.second
;
147 result
[p
].push_back(record
);
148 it
.second
->attributes
[ID::keep
] = RTLIL::Const(1);
149 it
.second
->attributes
[ID(_techmap_special_
)] = RTLIL::Const(1);
153 if (!result
.empty()) {
154 SigMap
sigmap(module
);
155 for (auto &it1
: result
)
156 for (auto &it2
: it1
.second
)
157 sigmap
.apply(it2
.value
);
163 void techmap_module_worker(RTLIL::Design
*design
, RTLIL::Module
*module
, RTLIL::Cell
*cell
, RTLIL::Module
*tpl
)
165 if (tpl
->processes
.size() != 0) {
166 log("Technology map yielded processes:");
167 for (auto &it
: tpl
->processes
)
168 log(" %s",RTLIL::id2cstr(it
.first
));
171 Pass::call_on_module(tpl
->design
, tpl
, "proc");
172 log_assert(GetSize(tpl
->processes
) == 0);
174 log_error("Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).\n");
177 std::string orig_cell_name
;
178 pool
<string
> extra_src_attrs
= cell
->get_strpool_attribute(ID(src
));
181 for (auto &it
: tpl
->cells_
)
182 if (it
.first
== ID(_TECHMAP_REPLACE_
)) {
183 orig_cell_name
= cell
->name
.str();
184 module
->rename(cell
, stringf("$techmap%d", autoidx
++) + cell
->name
.str());
189 dict
<IdString
, IdString
> memory_renames
;
191 for (auto &it
: tpl
->memories
) {
192 IdString m_name
= it
.first
;
193 apply_prefix(cell
->name
, m_name
);
194 RTLIL::Memory
*m
= new RTLIL::Memory
;
196 m
->width
= it
.second
->width
;
197 m
->start_offset
= it
.second
->start_offset
;
198 m
->size
= it
.second
->size
;
199 m
->attributes
= it
.second
->attributes
;
200 if (m
->attributes
.count(ID(src
)))
201 m
->add_strpool_attribute(ID(src
), extra_src_attrs
);
202 module
->memories
[m
->name
] = m
;
203 memory_renames
[it
.first
] = m
->name
;
204 design
->select(module
, m
);
207 std::map
<RTLIL::IdString
, RTLIL::IdString
> positional_ports
;
208 dict
<Wire
*, IdString
> temp_renamed_wires
;
210 for (auto &it
: tpl
->wires_
) {
211 if (it
.second
->port_id
> 0)
212 positional_ports
[stringf("$%d", it
.second
->port_id
)] = it
.first
;
213 IdString w_name
= it
.second
->name
;
214 apply_prefix(cell
->name
, w_name
);
215 RTLIL::Wire
*w
= module
->wire(w_name
);
217 if (!flatten_mode
|| !w
->get_bool_attribute(ID(hierconn
))) {
218 temp_renamed_wires
[w
] = w
->name
;
219 module
->rename(w
, NEW_ID
);
222 w
->attributes
.erase(ID(hierconn
));
223 if (GetSize(w
) < GetSize(it
.second
)) {
224 log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module
), log_id(w
),
225 log_id(tpl
), log_id(it
.second
), log_id(module
), log_id(cell
));
226 w
->width
= GetSize(it
.second
);
231 w
= module
->addWire(w_name
, it
.second
);
232 w
->port_input
= false;
233 w
->port_output
= false;
235 if (it
.second
->get_bool_attribute(ID(_techmap_special_
)))
236 w
->attributes
.clear();
237 if (w
->attributes
.count(ID(src
)))
238 w
->add_strpool_attribute(ID(src
), extra_src_attrs
);
240 design
->select(module
, w
);
243 SigMap
tpl_sigmap(tpl
);
244 pool
<SigBit
> tpl_written_bits
;
246 for (auto &it1
: tpl
->cells_
)
247 for (auto &it2
: it1
.second
->connections_
)
248 if (it1
.second
->output(it2
.first
))
249 for (auto bit
: tpl_sigmap(it2
.second
))
250 tpl_written_bits
.insert(bit
);
251 for (auto &it1
: tpl
->connections_
)
252 for (auto bit
: tpl_sigmap(it1
.first
))
253 tpl_written_bits
.insert(bit
);
255 SigMap port_signal_map
;
256 SigSig port_signal_assign
;
258 for (auto &it
: cell
->connections())
260 RTLIL::IdString portname
= it
.first
;
261 if (positional_ports
.count(portname
) > 0)
262 portname
= positional_ports
.at(portname
);
263 if (tpl
->wires_
.count(portname
) == 0 || tpl
->wires_
.at(portname
)->port_id
== 0) {
264 if (portname
.begins_with("$"))
265 log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname
.c_str(), cell
->name
.c_str(), tpl
->name
.c_str());
269 if (GetSize(it
.second
) == 0)
272 RTLIL::Wire
*w
= tpl
->wires_
.at(portname
);
273 RTLIL::SigSig c
, extra_connect
;
275 if (w
->port_output
&& !w
->port_input
) {
277 c
.second
= RTLIL::SigSpec(w
);
278 apply_prefix(cell
->name
, c
.second
, module
);
279 extra_connect
.first
= c
.second
;
280 extra_connect
.second
= c
.first
;
281 } else if (!w
->port_output
&& w
->port_input
) {
282 c
.first
= RTLIL::SigSpec(w
);
283 c
.second
= it
.second
;
284 apply_prefix(cell
->name
, c
.first
, module
);
285 extra_connect
.first
= c
.first
;
286 extra_connect
.second
= c
.second
;
288 SigSpec sig_tpl
= w
, sig_tpl_pf
= w
, sig_mod
= it
.second
;
289 apply_prefix(cell
->name
, sig_tpl_pf
, module
);
290 for (int i
= 0; i
< GetSize(sig_tpl
) && i
< GetSize(sig_mod
); i
++) {
291 if (tpl_written_bits
.count(tpl_sigmap(sig_tpl
[i
]))) {
292 c
.first
.append(sig_mod
[i
]);
293 c
.second
.append(sig_tpl_pf
[i
]);
295 c
.first
.append(sig_tpl_pf
[i
]);
296 c
.second
.append(sig_mod
[i
]);
299 extra_connect
.first
= sig_tpl_pf
;
300 extra_connect
.second
= sig_mod
;
303 if (c
.second
.size() > c
.first
.size())
304 c
.second
.remove(c
.first
.size(), c
.second
.size() - c
.first
.size());
306 if (c
.second
.size() < c
.first
.size())
307 c
.second
.append(RTLIL::SigSpec(RTLIL::State::S0
, c
.first
.size() - c
.second
.size()));
309 log_assert(c
.first
.size() == c
.second
.size());
313 // more conservative approach:
314 // connect internal and external wires
316 if (sigmaps
.count(module
) == 0)
317 sigmaps
[module
].set(module
);
319 if (sigmaps
.at(module
)(c
.first
).has_const())
320 log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
321 log_id(module
), log_id(cell
), log_id(it
.first
), log_signal(c
.first
), log_signal(c
.second
));
327 // approach that yields nicer outputs:
328 // replace internal wires that are connected to external wires
330 if (w
->port_output
&& !w
->port_input
) {
331 port_signal_map
.add(c
.second
, c
.first
);
333 if (!w
->port_output
&& w
->port_input
) {
334 port_signal_map
.add(c
.first
, c
.second
);
337 extra_connect
= SigSig();
340 for (auto &attr
: w
->attributes
) {
341 if (attr
.first
== ID(src
))
343 module
->connect(extra_connect
);
349 for (auto &it
: tpl
->cells_
)
351 IdString c_name
= it
.second
->name
.str();
352 bool techmap_replace_cell
= (!flatten_mode
) && (c_name
== ID(_TECHMAP_REPLACE_
));
354 if (techmap_replace_cell
)
355 c_name
= orig_cell_name
;
357 apply_prefix(cell
->name
, c_name
);
359 RTLIL::Cell
*c
= module
->addCell(c_name
, it
.second
);
360 design
->select(module
, c
);
362 if (!flatten_mode
&& c
->type
.begins_with("\\$"))
363 c
->type
= c
->type
.substr(1);
365 for (auto &it2
: c
->connections_
) {
366 apply_prefix(cell
->name
, it2
.second
, module
);
367 port_signal_map
.apply(it2
.second
);
370 if (c
->type
.in(ID($memrd
), ID($memwr
), ID($meminit
))) {
371 IdString memid
= c
->getParam(ID(MEMID
)).decode_string();
372 log_assert(memory_renames
.count(memid
) != 0);
373 c
->setParam(ID(MEMID
), Const(memory_renames
[memid
].str()));
376 if (c
->type
== ID($mem
)) {
377 IdString memid
= c
->getParam(ID(MEMID
)).decode_string();
378 apply_prefix(cell
->name
, memid
);
379 c
->setParam(ID(MEMID
), Const(memid
.c_str()));
382 if (c
->attributes
.count(ID(src
)))
383 c
->add_strpool_attribute(ID(src
), extra_src_attrs
);
385 if (techmap_replace_cell
)
386 for (auto attr
: cell
->attributes
)
387 if (!c
->attributes
.count(attr
.first
))
388 c
->attributes
[attr
.first
] = attr
.second
;
391 for (auto &it
: tpl
->connections()) {
392 RTLIL::SigSig c
= it
;
393 apply_prefix(cell
->name
.str(), c
.first
, module
);
394 apply_prefix(cell
->name
.str(), c
.second
, module
);
395 port_signal_map
.apply(c
.first
);
396 port_signal_map
.apply(c
.second
);
400 module
->remove(cell
);
402 for (auto &it
: temp_renamed_wires
)
405 IdString name
= it
.second
;
406 IdString altname
= module
->uniquify(name
);
407 Wire
*other_w
= module
->wire(name
);
408 module
->rename(other_w
, altname
);
409 module
->rename(w
, name
);
413 bool techmap_module(RTLIL::Design
*design
, RTLIL::Module
*module
, RTLIL::Design
*map
, std::set
<RTLIL::Cell
*> &handled_cells
,
414 const std::map
<RTLIL::IdString
, std::set
<RTLIL::IdString
, RTLIL::sort_by_id_str
>> &celltypeMap
, bool in_recursion
)
416 std::string mapmsg_prefix
= in_recursion
? "Recursively mapping" : "Mapping";
418 if (!design
->selected(module
) || module
->get_blackbox_attribute(ignore_wb
))
421 bool log_continue
= false;
422 bool did_something
= false;
423 LogMakeDebugHdl mkdebug
;
425 SigMap
sigmap(module
);
427 TopoSort
<RTLIL::Cell
*, RTLIL::IdString::compare_ptr_by_name
<RTLIL::Cell
>> cells
;
428 std::map
<RTLIL::Cell
*, std::set
<RTLIL::SigBit
>> cell_to_inbit
;
429 std::map
<RTLIL::SigBit
, std::set
<RTLIL::Cell
*>> outbit_to_cell
;
431 for (auto cell
: module
->cells())
433 if (!design
->selected(module
, cell
) || handled_cells
.count(cell
) > 0)
436 std::string cell_type
= cell
->type
.str();
437 if (in_recursion
&& cell
->type
.begins_with("\\$"))
438 cell_type
= cell_type
.substr(1);
440 if (celltypeMap
.count(cell_type
) == 0) {
441 if (assert_mode
&& cell_type
.back() != '_')
442 log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type
));
447 bool keepit
= cell
->get_bool_attribute(ID(keep_hierarchy
));
448 for (auto &tpl_name
: celltypeMap
.at(cell_type
))
449 if (map
->modules_
[tpl_name
]->get_bool_attribute(ID(keep_hierarchy
)))
452 if (!flatten_keep_list
[cell
]) {
453 log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module
), log_id(cell
));
454 flatten_keep_list
.insert(cell
);
456 if (!flatten_done_list
[cell
->type
])
457 flatten_do_list
.insert(cell
->type
);
462 for (auto &conn
: cell
->connections())
464 RTLIL::SigSpec sig
= sigmap(conn
.second
);
467 if (GetSize(sig
) == 0)
470 for (auto &tpl_name
: celltypeMap
.at(cell_type
)) {
471 RTLIL::Module
*tpl
= map
->modules_
[tpl_name
];
472 RTLIL::Wire
*port
= tpl
->wire(conn
.first
);
473 if (port
&& port
->port_input
)
474 cell_to_inbit
[cell
].insert(sig
.begin(), sig
.end());
475 if (port
&& port
->port_output
)
476 for (auto &bit
: sig
)
477 outbit_to_cell
[bit
].insert(cell
);
484 for (auto &it_right
: cell_to_inbit
)
485 for (auto &it_sigbit
: it_right
.second
)
486 for (auto &it_left
: outbit_to_cell
[it_sigbit
])
487 cells
.edge(it_left
, it_right
.first
);
491 for (auto cell
: cells
.sorted
)
493 log_assert(handled_cells
.count(cell
) == 0);
494 log_assert(cell
== module
->cell(cell
->name
));
495 bool mapped_cell
= false;
497 std::string cell_type
= cell
->type
.str();
499 if (in_recursion
&& cell
->type
.begins_with("\\$"))
500 cell_type
= cell_type
.substr(1);
502 for (auto &tpl_name
: celltypeMap
.at(cell_type
))
504 RTLIL::IdString derived_name
= tpl_name
;
505 RTLIL::Module
*tpl
= map
->modules_
[tpl_name
];
506 std::map
<RTLIL::IdString
, RTLIL::Const
> parameters(cell
->parameters
.begin(), cell
->parameters
.end());
508 if (tpl
->get_blackbox_attribute(ignore_wb
))
513 std::string extmapper_name
;
515 if (tpl
->get_bool_attribute(ID(techmap_simplemap
)))
516 extmapper_name
= "simplemap";
518 if (tpl
->get_bool_attribute(ID(techmap_maccmap
)))
519 extmapper_name
= "maccmap";
521 if (tpl
->attributes
.count(ID(techmap_wrap
)))
522 extmapper_name
= "wrap";
524 if (!extmapper_name
.empty())
526 cell
->type
= cell_type
;
528 if ((extern_mode
&& !in_recursion
) || extmapper_name
== "wrap")
530 std::string m_name
= stringf("$extern:%s:%s", extmapper_name
.c_str(), log_id(cell
->type
));
532 for (auto &c
: cell
->parameters
)
533 m_name
+= stringf(":%s=%s", log_id(c
.first
), log_signal(c
.second
));
535 if (extmapper_name
== "wrap")
536 m_name
+= ":" + sha1(tpl
->attributes
.at(ID(techmap_wrap
)).decode_string());
538 RTLIL::Design
*extmapper_design
= extern_mode
&& !in_recursion
? design
: tpl
->design
;
539 RTLIL::Module
*extmapper_module
= extmapper_design
->module(m_name
);
541 if (extmapper_module
== nullptr)
543 extmapper_module
= extmapper_design
->addModule(m_name
);
544 RTLIL::Cell
*extmapper_cell
= extmapper_module
->addCell(cell
->type
, cell
);
546 extmapper_cell
->set_src_attribute(cell
->get_src_attribute());
548 int port_counter
= 1;
549 for (auto &c
: extmapper_cell
->connections_
) {
550 RTLIL::Wire
*w
= extmapper_module
->addWire(c
.first
, GetSize(c
.second
));
551 if (w
->name
.in(ID::Y
, ID(Q
)))
552 w
->port_output
= true;
554 w
->port_input
= true;
555 w
->port_id
= port_counter
++;
559 extmapper_module
->fixup_ports();
560 extmapper_module
->check();
562 if (extmapper_name
== "simplemap") {
563 log("Creating %s with simplemap.\n", log_id(extmapper_module
));
564 if (simplemap_mappers
.count(extmapper_cell
->type
) == 0)
565 log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell
->type
));
566 simplemap_mappers
.at(extmapper_cell
->type
)(extmapper_module
, extmapper_cell
);
567 extmapper_module
->remove(extmapper_cell
);
570 if (extmapper_name
== "maccmap") {
571 log("Creating %s with maccmap.\n", log_id(extmapper_module
));
572 if (extmapper_cell
->type
!= ID($macc
))
573 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell
->type
));
574 maccmap(extmapper_module
, extmapper_cell
);
575 extmapper_module
->remove(extmapper_cell
);
578 if (extmapper_name
== "wrap") {
579 std::string cmd_string
= tpl
->attributes
.at(ID(techmap_wrap
)).decode_string();
580 log("Running \"%s\" on wrapper %s.\n", cmd_string
.c_str(), log_id(extmapper_module
));
582 Pass::call_on_module(extmapper_design
, extmapper_module
, cmd_string
);
587 cell
->type
= extmapper_module
->name
;
588 cell
->parameters
.clear();
590 if (!extern_mode
|| in_recursion
) {
591 tpl
= extmapper_module
;
592 goto use_wrapper_tpl
;
595 auto msg
= stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module
), log_id(cell
->type
));
596 if (!log_msg_cache
.count(msg
)) {
597 log_msg_cache
.insert(msg
);
598 log("%s\n", msg
.c_str());
600 log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix
.c_str(), log_id(module
), log_id(cell
), log_id(cell
->type
), log_id(extmapper_module
));
604 auto msg
= stringf("Using extmapper %s for cells of type %s.", extmapper_name
.c_str(), log_id(cell
->type
));
605 if (!log_msg_cache
.count(msg
)) {
606 log_msg_cache
.insert(msg
);
607 log("%s\n", msg
.c_str());
609 log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix
.c_str(), log_id(module
), log_id(cell
), log_id(cell
->type
), extmapper_name
.c_str());
611 if (extmapper_name
== "simplemap") {
612 if (simplemap_mappers
.count(cell
->type
) == 0)
613 log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell
->type
));
614 simplemap_mappers
.at(cell
->type
)(module
, cell
);
617 if (extmapper_name
== "maccmap") {
618 if (cell
->type
!= ID($macc
))
619 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell
->type
));
620 maccmap(module
, cell
);
623 module
->remove(cell
);
627 did_something
= true;
632 for (auto conn
: cell
->connections()) {
633 if (conn
.first
.begins_with("$"))
635 if (tpl
->wires_
.count(conn
.first
) > 0 && tpl
->wires_
.at(conn
.first
)->port_id
> 0)
637 if (!conn
.second
.is_fully_const() || parameters
.count(conn
.first
) > 0 || tpl
->avail_parameters
.count(conn
.first
) == 0)
639 parameters
[conn
.first
] = conn
.second
.as_const();
647 if (tpl
->avail_parameters
.count(ID(_TECHMAP_CELLTYPE_
)) != 0)
648 parameters
[ID(_TECHMAP_CELLTYPE_
)] = RTLIL::unescape_id(cell
->type
);
650 for (auto conn
: cell
->connections()) {
651 if (tpl
->avail_parameters
.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn
.first
))) != 0) {
652 std::vector
<RTLIL::SigBit
> v
= sigmap(conn
.second
).to_sigbit_vector();
654 bit
= RTLIL::SigBit(bit
.wire
== NULL
? RTLIL::State::S1
: RTLIL::State::S0
);
655 parameters
[stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn
.first
))] = RTLIL::SigSpec(v
).as_const();
657 if (tpl
->avail_parameters
.count(stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn
.first
))) != 0) {
658 std::vector
<RTLIL::SigBit
> v
= sigmap(conn
.second
).to_sigbit_vector();
660 if (bit
.wire
!= NULL
)
661 bit
= RTLIL::SigBit(RTLIL::State::Sx
);
662 parameters
[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn
.first
))] = RTLIL::SigSpec(v
).as_const();
666 int unique_bit_id_counter
= 0;
667 std::map
<RTLIL::SigBit
, int> unique_bit_id
;
668 unique_bit_id
[RTLIL::State::S0
] = unique_bit_id_counter
++;
669 unique_bit_id
[RTLIL::State::S1
] = unique_bit_id_counter
++;
670 unique_bit_id
[RTLIL::State::Sx
] = unique_bit_id_counter
++;
671 unique_bit_id
[RTLIL::State::Sz
] = unique_bit_id_counter
++;
673 for (auto conn
: cell
->connections())
674 if (tpl
->avail_parameters
.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn
.first
))) != 0) {
675 for (auto &bit
: sigmap(conn
.second
).to_sigbit_vector())
676 if (unique_bit_id
.count(bit
) == 0)
677 unique_bit_id
[bit
] = unique_bit_id_counter
++;
680 // Find highest bit set
682 for (int i
= 0; i
< 32; i
++)
683 if (((unique_bit_id_counter
-1) & (1 << i
)) != 0)
685 // Increment index by one to get number of bits
687 if (tpl
->avail_parameters
.count(ID(_TECHMAP_BITS_CONNMAP_
)))
688 parameters
[ID(_TECHMAP_BITS_CONNMAP_
)] = bits
;
690 for (auto conn
: cell
->connections())
691 if (tpl
->avail_parameters
.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn
.first
))) != 0) {
693 for (auto &bit
: sigmap(conn
.second
).to_sigbit_vector()) {
694 RTLIL::Const
chunk(unique_bit_id
.at(bit
), bits
);
695 value
.bits
.insert(value
.bits
.end(), chunk
.bits
.begin(), chunk
.bits
.end());
697 parameters
[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn
.first
))] = value
;
703 // do not register techmap_wrap modules with techmap_cache
705 std::pair
<RTLIL::IdString
, std::map
<RTLIL::IdString
, RTLIL::Const
>> key(tpl_name
, parameters
);
706 if (techmap_cache
.count(key
) > 0) {
707 tpl
= techmap_cache
[key
];
709 if (parameters
.size() != 0) {
711 derived_name
= tpl
->derive(map
, dict
<RTLIL::IdString
, RTLIL::Const
>(parameters
.begin(), parameters
.end()));
712 tpl
= map
->module(derived_name
);
715 techmap_cache
[key
] = tpl
;
720 techmap_do_cache
[tpl
] = true;
722 RTLIL::Module
*constmapped_tpl
= map
->module(constmap_tpl_name(sigmap
, tpl
, cell
, false));
723 if (constmapped_tpl
!= nullptr)
724 tpl
= constmapped_tpl
;
727 if (techmap_do_cache
.count(tpl
) == 0)
729 bool keep_running
= true;
730 techmap_do_cache
[tpl
] = true;
732 std::set
<std::string
> techmap_wire_names
;
736 TechmapWires twd
= techmap_find_special_wires(tpl
);
737 keep_running
= false;
740 techmap_wire_names
.insert(it
.first
);
742 for (auto &it
: twd
["_TECHMAP_FAIL_"]) {
743 RTLIL::SigSpec value
= it
.value
;
744 if (value
.is_fully_const() && value
.as_bool()) {
745 log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
746 derived_name
.c_str(), RTLIL::id2cstr(it
.wire
->name
), log_signal(value
));
747 techmap_do_cache
[tpl
] = false;
751 if (!techmap_do_cache
[tpl
])
756 if (it
.first
.compare(0, 12, "_TECHMAP_DO_") != 0 || it
.second
.empty())
759 auto &data
= it
.second
.front();
761 if (!data
.value
.is_fully_const())
762 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data
.wire
->name
), log_signal(data
.value
));
764 techmap_wire_names
.erase(it
.first
);
766 const char *p
= data
.wire
->name
.c_str();
767 const char *q
= strrchr(p
+1, '.');
770 std::string cmd_string
= data
.value
.as_const().decode_string();
772 restart_eval_cmd_string
:
773 if (cmd_string
.rfind("CONSTMAP; ", 0) == 0)
775 cmd_string
= cmd_string
.substr(strlen("CONSTMAP; "));
777 log("Analyzing pattern of constant bits for this cell:\n");
778 RTLIL::IdString new_tpl_name
= constmap_tpl_name(sigmap
, tpl
, cell
, true);
779 log("Creating constmapped module `%s'.\n", log_id(new_tpl_name
));
780 log_assert(map
->module(new_tpl_name
) == nullptr);
782 RTLIL::Module
*new_tpl
= map
->addModule(new_tpl_name
);
783 tpl
->cloneInto(new_tpl
);
785 techmap_do_cache
.erase(tpl
);
786 techmap_do_cache
[new_tpl
] = true;
789 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> port_new2old_map
;
790 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> port_connmap
;
791 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> cellbits_to_tplbits
;
793 for (auto wire
: tpl
->wires().to_vector())
795 if (!wire
->port_input
|| wire
->port_output
)
798 RTLIL::IdString port_name
= wire
->name
;
799 tpl
->rename(wire
, NEW_ID
);
801 RTLIL::Wire
*new_wire
= tpl
->addWire(port_name
, wire
);
802 wire
->port_input
= false;
805 for (int i
= 0; i
< wire
->width
; i
++) {
806 port_new2old_map
[RTLIL::SigBit(new_wire
, i
)] = RTLIL::SigBit(wire
, i
);
807 port_connmap
[RTLIL::SigBit(wire
, i
)] = RTLIL::SigBit(new_wire
, i
);
811 for (auto conn
: cell
->connections())
812 for (int i
= 0; i
< GetSize(conn
.second
); i
++)
814 RTLIL::SigBit bit
= sigmap(conn
.second
[i
]);
815 RTLIL::SigBit
tplbit(tpl
->wire(conn
.first
), i
);
817 if (bit
.wire
== nullptr)
819 RTLIL::SigBit oldbit
= port_new2old_map
.at(tplbit
);
820 port_connmap
.at(oldbit
) = bit
;
822 else if (cellbits_to_tplbits
.count(bit
))
824 RTLIL::SigBit oldbit
= port_new2old_map
.at(tplbit
);
825 port_connmap
.at(oldbit
) = cellbits_to_tplbits
[bit
];
828 cellbits_to_tplbits
[bit
] = tplbit
;
831 RTLIL::SigSig port_conn
;
832 for (auto &it
: port_connmap
) {
833 port_conn
.first
.append_bit(it
.first
);
834 port_conn
.second
.append_bit(it
.second
);
836 tpl
->connect(port_conn
);
839 goto restart_eval_cmd_string
;
842 if (cmd_string
.rfind("RECURSION; ", 0) == 0)
844 cmd_string
= cmd_string
.substr(strlen("RECURSION; "));
845 while (techmap_module(map
, tpl
, map
, handled_cells
, celltypeMap
, true)) { }
846 goto restart_eval_cmd_string
;
849 Pass::call_on_module(map
, tpl
, cmd_string
);
851 log_assert(!strncmp(q
, "_TECHMAP_DO_", 12));
852 std::string new_name
= data
.wire
->name
.substr(0, q
-p
) + "_TECHMAP_DONE_" + data
.wire
->name
.substr(q
-p
+12);
853 while (tpl
->wires_
.count(new_name
))
855 tpl
->rename(data
.wire
->name
, new_name
);
862 TechmapWires twd
= techmap_find_special_wires(tpl
);
863 for (auto &it
: twd
) {
864 if (it
.first
!= "_TECHMAP_FAIL_" && it
.first
.substr(0, 12) != "_TECHMAP_DO_" && it
.first
.substr(0, 14) != "_TECHMAP_DONE_")
865 log_error("Techmap yielded unknown config wire %s.\n", it
.first
.c_str());
866 if (techmap_do_cache
[tpl
])
867 for (auto &it2
: it
.second
)
868 if (!it2
.value
.is_fully_const())
869 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2
.wire
->name
), log_signal(it2
.value
));
870 techmap_wire_names
.erase(it
.first
);
873 for (auto &it
: techmap_wire_names
)
874 log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it
));
876 if (recursive_mode
) {
878 log_header(design
, "Continuing TECHMAP pass.\n");
879 log_continue
= false;
882 while (techmap_module(map
, tpl
, map
, handled_cells
, celltypeMap
, true)) { }
886 if (techmap_do_cache
.at(tpl
) == false)
890 log_header(design
, "Continuing TECHMAP pass.\n");
891 log_continue
= false;
895 if (extern_mode
&& !in_recursion
)
897 std::string m_name
= stringf("$extern:%s", log_id(tpl
));
899 if (!design
->module(m_name
))
901 RTLIL::Module
*m
= design
->addModule(m_name
);
904 for (auto cell
: m
->cells()) {
905 if (cell
->type
.begins_with("\\$"))
906 cell
->type
= cell
->type
.substr(1);
909 module_queue
.insert(m
);
912 log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix
.c_str(), log_id(module
), log_id(cell
), log_id(m_name
));
914 cell
->parameters
.clear();
918 auto msg
= stringf("Using template %s for cells of type %s.", log_id(tpl
), log_id(cell
->type
));
919 if (!log_msg_cache
.count(msg
)) {
920 log_msg_cache
.insert(msg
);
921 log("%s\n", msg
.c_str());
923 log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix
.c_str(), log_id(module
), log_id(cell
), log_id(cell
->type
), log_id(tpl
));
924 techmap_module_worker(design
, module
, cell
, tpl
);
927 did_something
= true;
932 if (assert_mode
&& !mapped_cell
)
933 log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", log_id(module
), log_id(cell
), log_id(cell
->type
));
935 handled_cells
.insert(cell
);
939 log_header(design
, "Continuing TECHMAP pass.\n");
940 log_continue
= false;
944 return did_something
;
948 struct TechmapPass
: public Pass
{
949 TechmapPass() : Pass("techmap", "generic technology mapper") { }
950 void help() YS_OVERRIDE
952 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
954 log(" techmap [-map filename] [selection]\n");
956 log("This pass implements a very simple technology mapper that replaces cells in\n");
957 log("the design with implementations given in form of a Verilog or ilang source\n");
960 log(" -map filename\n");
961 log(" the library of cell implementations to be used.\n");
962 log(" without this parameter a builtin library is used that\n");
963 log(" transforms the internal RTL cells to the internal gate\n");
966 log(" -map %%<design-name>\n");
967 log(" like -map above, but with an in-memory design instead of a file.\n");
970 log(" load the cell implementations as separate modules into the design\n");
971 log(" instead of inlining them.\n");
973 log(" -max_iter <number>\n");
974 log(" only run the specified number of iterations on each module.\n");
975 log(" default: unlimited\n");
977 log(" -recursive\n");
978 log(" instead of the iterative breadth-first algorithm use a recursive\n");
979 log(" depth-first algorithm. both methods should yield equivalent results,\n");
980 log(" but may differ in performance.\n");
983 log(" Automatically call \"proc\" on implementations that contain processes.\n");
986 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
989 log(" this option will cause techmap to exit with an error if it can't map\n");
990 log(" a selected cell. only cell types that end on an underscore are accepted\n");
991 log(" as final cell types by this mode.\n");
993 log(" -D <define>, -I <incdir>\n");
994 log(" this options are passed as-is to the Verilog frontend for loading the\n");
995 log(" map file. Note that the Verilog frontend is also called with the\n");
996 log(" '-nooverwrite' option set.\n");
998 log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
999 log("match cells with a type that match the text value of this attribute. Otherwise\n");
1000 log("the module name will be used to match the cell.\n");
1002 log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
1003 log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
1005 log("When a module in the map file has the 'techmap_maccmap' attribute set, techmap\n");
1006 log("will use 'maccmap' (see 'help maccmap') to map cells matching the module.\n");
1008 log("When a module in the map file has the 'techmap_wrap' attribute set, techmap\n");
1009 log("will create a wrapper for the cell and then run the command string that the\n");
1010 log("attribute is set to on the wrapper module.\n");
1012 log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
1013 log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
1014 log("the mapping module to the techmap command. At the moment the following special\n");
1015 log("wires are supported:\n");
1017 log(" _TECHMAP_FAIL_\n");
1018 log(" When this wire is set to a non-zero constant value, techmap will not\n");
1019 log(" use this module and instead try the next module with a matching\n");
1020 log(" 'techmap_celltype' attribute.\n");
1022 log(" When such a wire exists but does not have a constant value after all\n");
1023 log(" _TECHMAP_DO_* commands have been executed, an error is generated.\n");
1025 log(" _TECHMAP_DO_*\n");
1026 log(" This wires are evaluated in alphabetical order. The constant text value\n");
1027 log(" of this wire is a yosys command (or sequence of commands) that is run\n");
1028 log(" by techmap on the module. A common use case is to run 'proc' on modules\n");
1029 log(" that are written using always-statements.\n");
1031 log(" When such a wire has a non-constant value at the time it is to be\n");
1032 log(" evaluated, an error is produced. That means it is possible for such a\n");
1033 log(" wire to start out as non-constant and evaluate to a constant value\n");
1034 log(" during processing of other _TECHMAP_DO_* commands.\n");
1036 log(" A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.\n");
1037 log(" in this case techmap will create a copy for each distinct configuration\n");
1038 log(" of constant inputs and shorted inputs at this point and import the\n");
1039 log(" constant and connected bits into the map module. All further commands\n");
1040 log(" are executed in this copy. This is a very convenient way of creating\n");
1041 log(" optimized specializations of techmap modules without using the special\n");
1042 log(" parameters described below.\n");
1044 log(" A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.\n");
1045 log(" then techmap will recursively replace the cells in the module with their\n");
1046 log(" implementation. This is not affected by the -max_iter option.\n");
1048 log(" It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n");
1050 log("In addition to this special wires, techmap also supports special parameters in\n");
1051 log("modules in the map file:\n");
1053 log(" _TECHMAP_CELLTYPE_\n");
1054 log(" When a parameter with this name exists, it will be set to the type name\n");
1055 log(" of the cell that matches the module.\n");
1057 log(" _TECHMAP_CONSTMSK_<port-name>_\n");
1058 log(" _TECHMAP_CONSTVAL_<port-name>_\n");
1059 log(" When this pair of parameters is available in a module for a port, then\n");
1060 log(" former has a 1-bit for each constant input bit and the latter has the\n");
1061 log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
1063 log(" _TECHMAP_BITS_CONNMAP_\n");
1064 log(" _TECHMAP_CONNMAP_<port-name>_\n");
1065 log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
1066 log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n");
1067 log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n");
1068 log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n");
1069 log(" This can be used to detect shorted inputs.\n");
1071 log("When a module in the map file has a parameter where the according cell in the\n");
1072 log("design has a port, the module from the map file is only used if the port in\n");
1073 log("the design is connected to a constant value. The parameter is then set to the\n");
1074 log("constant value.\n");
1076 log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
1077 log("and attributes of the cell that is being replaced.\n");
1079 log("See 'help extract' for a pass that does the opposite thing.\n");
1081 log("See 'help flatten' for a pass that does flatten the design (which is\n");
1082 log("essentially techmap but using the design itself as map library).\n");
1085 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1087 log_header(design
, "Executing TECHMAP pass (map to technology primitives).\n");
1090 TechmapWorker worker
;
1091 simplemap_get_mappers(worker
.simplemap_mappers
);
1093 std::vector
<std::string
> map_files
;
1094 std::string verilog_frontend
= "verilog -nooverwrite -noblackbox";
1098 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
1099 if (args
[argidx
] == "-map" && argidx
+1 < args
.size()) {
1100 map_files
.push_back(args
[++argidx
]);
1103 if (args
[argidx
] == "-max_iter" && argidx
+1 < args
.size()) {
1104 max_iter
= atoi(args
[++argidx
].c_str());
1107 if (args
[argidx
] == "-D" && argidx
+1 < args
.size()) {
1108 verilog_frontend
+= " -D " + args
[++argidx
];
1111 if (args
[argidx
] == "-I" && argidx
+1 < args
.size()) {
1112 verilog_frontend
+= " -I " + args
[++argidx
];
1115 if (args
[argidx
] == "-assert") {
1116 worker
.assert_mode
= true;
1119 if (args
[argidx
] == "-extern") {
1120 worker
.extern_mode
= true;
1123 if (args
[argidx
] == "-recursive") {
1124 worker
.recursive_mode
= true;
1127 if (args
[argidx
] == "-autoproc") {
1128 worker
.autoproc_mode
= true;
1131 if (args
[argidx
] == "-wb") {
1132 worker
.ignore_wb
= true;
1137 extra_args(args
, argidx
, design
);
1139 RTLIL::Design
*map
= new RTLIL::Design
;
1140 if (map_files
.empty()) {
1141 std::istringstream
f(stdcells_code
);
1142 Frontend::frontend_call(map
, &f
, "<techmap.v>", verilog_frontend
);
1144 for (auto &fn
: map_files
)
1145 if (fn
.compare(0, 1, "%") == 0) {
1146 if (!saved_designs
.count(fn
.substr(1))) {
1148 log_cmd_error("Can't saved design `%s'.\n", fn
.c_str()+1);
1150 for (auto mod
: saved_designs
.at(fn
.substr(1))->modules())
1151 if (!map
->has(mod
->name
))
1152 map
->add(mod
->clone());
1155 rewrite_filename(fn
);
1157 yosys_input_files
.insert(fn
);
1159 log_cmd_error("Can't open map file `%s'\n", fn
.c_str());
1160 Frontend::frontend_call(map
, &f
, fn
, (fn
.size() > 3 && fn
.compare(fn
.size()-3, std::string::npos
, ".il") == 0 ? "ilang" : verilog_frontend
));
1164 log_header(design
, "Continuing TECHMAP pass.\n");
1166 std::map
<RTLIL::IdString
, std::set
<RTLIL::IdString
, RTLIL::sort_by_id_str
>> celltypeMap
;
1167 for (auto &it
: map
->modules_
) {
1168 if (it
.second
->attributes
.count(ID(techmap_celltype
)) && !it
.second
->attributes
.at(ID(techmap_celltype
)).bits
.empty()) {
1169 char *p
= strdup(it
.second
->attributes
.at(ID(techmap_celltype
)).decode_string().c_str());
1170 for (char *q
= strtok(p
, " \t\r\n"); q
; q
= strtok(NULL
, " \t\r\n"))
1171 celltypeMap
[RTLIL::escape_id(q
)].insert(it
.first
);
1174 string module_name
= it
.first
.str();
1175 if (it
.first
.begins_with("\\$"))
1176 module_name
= module_name
.substr(1);
1177 celltypeMap
[module_name
].insert(it
.first
);
1181 for (auto module
: design
->modules())
1182 worker
.module_queue
.insert(module
);
1184 while (!worker
.module_queue
.empty())
1186 RTLIL::Module
*module
= *worker
.module_queue
.begin();
1187 worker
.module_queue
.erase(module
);
1189 int module_max_iter
= max_iter
;
1190 bool did_something
= true;
1191 std::set
<RTLIL::Cell
*> handled_cells
;
1192 while (did_something
) {
1193 did_something
= false;
1194 if (worker
.techmap_module(design
, module
, map
, handled_cells
, celltypeMap
, false))
1195 did_something
= true;
1198 if (module_max_iter
> 0 && --module_max_iter
== 0)
1203 log("No more expansions possible.\n");
1210 struct FlattenPass
: public Pass
{
1211 FlattenPass() : Pass("flatten", "flatten design") { }
1212 void help() YS_OVERRIDE
1214 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1216 log(" flatten [options] [selection]\n");
1218 log("This pass flattens the design by replacing cells by their implementation. This\n");
1219 log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
1220 log("pass is using the current design as mapping library.\n");
1222 log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
1223 log("flattened by this command.\n");
1226 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
1229 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1231 log_header(design
, "Executing FLATTEN pass (flatten design).\n");
1234 TechmapWorker worker
;
1235 worker
.flatten_mode
= true;
1238 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
1239 if (args
[argidx
] == "-wb") {
1240 worker
.ignore_wb
= true;
1245 extra_args(args
, argidx
, design
);
1248 std::map
<RTLIL::IdString
, std::set
<RTLIL::IdString
, RTLIL::sort_by_id_str
>> celltypeMap
;
1249 for (auto module
: design
->modules())
1250 celltypeMap
[module
->name
].insert(module
->name
);
1252 RTLIL::Module
*top_mod
= NULL
;
1253 if (design
->full_selection())
1254 for (auto mod
: design
->modules())
1255 if (mod
->get_bool_attribute(ID(top
)))
1258 std::set
<RTLIL::Cell
*> handled_cells
;
1259 if (top_mod
!= NULL
) {
1260 worker
.flatten_do_list
.insert(top_mod
->name
);
1261 while (!worker
.flatten_do_list
.empty()) {
1262 auto mod
= design
->module(*worker
.flatten_do_list
.begin());
1263 while (worker
.techmap_module(design
, mod
, design
, handled_cells
, celltypeMap
, false)) { }
1264 worker
.flatten_done_list
.insert(mod
->name
);
1265 worker
.flatten_do_list
.erase(mod
->name
);
1268 for (auto mod
: vector
<Module
*>(design
->modules())) {
1269 while (worker
.techmap_module(design
, mod
, design
, handled_cells
, celltypeMap
, false)) { }
1274 log("No more expansions possible.\n");
1276 if (top_mod
!= NULL
)
1278 pool
<RTLIL::IdString
> used_modules
, new_used_modules
;
1279 new_used_modules
.insert(top_mod
->name
);
1280 while (!new_used_modules
.empty()) {
1281 pool
<RTLIL::IdString
> queue
;
1282 queue
.swap(new_used_modules
);
1283 for (auto modname
: queue
)
1284 used_modules
.insert(modname
);
1285 for (auto modname
: queue
)
1286 for (auto cell
: design
->module(modname
)->cells())
1287 if (design
->module(cell
->type
) && !used_modules
[cell
->type
])
1288 new_used_modules
.insert(cell
->type
);
1291 dict
<RTLIL::IdString
, RTLIL::Module
*> new_modules
;
1292 for (auto mod
: vector
<Module
*>(design
->modules()))
1293 if (used_modules
[mod
->name
] || mod
->get_blackbox_attribute(worker
.ignore_wb
)) {
1294 new_modules
[mod
->name
] = mod
;
1296 log("Deleting now unused module %s.\n", log_id(mod
));
1299 design
->modules_
.swap(new_modules
);
1306 PRIVATE_NAMESPACE_END