2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/sigtools.h"
22 #include "kernel/log.h"
28 #include "passes/techmap/stdcells.inc"
30 static void apply_prefix(std::string prefix
, std::string
&id
)
33 id
= prefix
+ "." + id
.substr(1);
35 id
= "$techmap" + prefix
+ "." + id
;
38 static void apply_prefix(std::string prefix
, RTLIL::SigSpec
&sig
, RTLIL::Module
*module
)
40 for (size_t i
= 0; i
< sig
.chunks
.size(); i
++) {
41 if (sig
.chunks
[i
].wire
== NULL
)
43 std::string wire_name
= sig
.chunks
[i
].wire
->name
;
44 apply_prefix(prefix
, wire_name
);
45 assert(module
->wires
.count(wire_name
) > 0);
46 sig
.chunks
[i
].wire
= module
->wires
[wire_name
];
50 std::map
<std::pair
<RTLIL::IdString
, std::map
<RTLIL::IdString
, RTLIL::Const
>>, RTLIL::Module
*> techmap_cache
;
51 std::map
<RTLIL::Module
*, bool> techmap_fail_cache
;
52 std::set
<RTLIL::Module
*> techmap_opt_cache
;
54 static bool techmap_fail_check(RTLIL::Module
*module
)
59 if (techmap_fail_cache
.count(module
) > 0)
60 return techmap_fail_cache
.at(module
);
62 for (auto &it
: module
->wires
) {
63 std::string name
= it
.first
;
64 if (name
== "\\TECHMAP_FAIL")
65 return techmap_fail_cache
[module
] = true;
66 if (name
.size() > 13 && name
[0] == '\\' && name
.substr(name
.size()-13) == ".TECHMAP_FAIL")
67 return techmap_fail_cache
[module
] = true;
70 return techmap_fail_cache
[module
] = false;
73 static void techmap_module_worker(RTLIL::Design
*design
, RTLIL::Module
*module
, RTLIL::Cell
*cell
, RTLIL::Module
*tpl
, RTLIL::Selection
&new_members
, bool flatten_mode
)
75 log("Mapping `%s.%s' using `%s'.\n", RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(cell
->name
), RTLIL::id2cstr(tpl
->name
));
77 if (tpl
->memories
.size() != 0)
78 log_error("Technology map yielded memories -> this is not supported.\n");
80 if (tpl
->processes
.size() != 0)
81 log_error("Technology map yielded processes -> this is not supported.\n");
83 std::map
<RTLIL::IdString
, RTLIL::IdString
> positional_ports
;
85 for (auto &it
: tpl
->wires
) {
86 if (it
.second
->port_id
> 0)
87 positional_ports
[stringf("$%d", it
.second
->port_id
)] = it
.first
;
88 RTLIL::Wire
*w
= new RTLIL::Wire(*it
.second
);
89 apply_prefix(cell
->name
, w
->name
);
90 w
->port_input
= false;
91 w
->port_output
= false;
93 module
->wires
[w
->name
] = w
;
94 design
->select(module
, w
);
95 new_members
.select(module
, w
);
98 SigMap port_signal_map
;
100 for (auto &it
: cell
->connections
) {
101 RTLIL::IdString portname
= it
.first
;
102 if (positional_ports
.count(portname
) > 0)
103 portname
= positional_ports
.at(portname
);
104 if (tpl
->wires
.count(portname
) == 0 || tpl
->wires
.at(portname
)->port_id
== 0) {
105 if (portname
.substr(0, 1) == "$")
106 log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname
.c_str(), cell
->name
.c_str(), tpl
->name
.c_str());
109 RTLIL::Wire
*w
= tpl
->wires
.at(portname
);
111 if (w
->port_output
) {
113 c
.second
= RTLIL::SigSpec(w
);
114 apply_prefix(cell
->name
, c
.second
, module
);
116 c
.first
= RTLIL::SigSpec(w
);
117 c
.second
= it
.second
;
118 apply_prefix(cell
->name
, c
.first
, module
);
120 if (c
.second
.width
> c
.first
.width
)
121 c
.second
.remove(c
.first
.width
, c
.second
.width
- c
.first
.width
);
122 if (c
.second
.width
< c
.first
.width
)
123 c
.second
.append(RTLIL::SigSpec(RTLIL::State::S0
, c
.first
.width
- c
.second
.width
));
124 assert(c
.first
.width
== c
.second
.width
);
126 // more conservative approach:
127 // connect internal and external wires
128 module
->connections
.push_back(c
);
130 // approach that yields nicer outputs:
131 // replace internal wires that are connected to external wires
133 port_signal_map
.add(c
.second
, c
.first
);
135 port_signal_map
.add(c
.first
, c
.second
);
139 for (auto &it
: tpl
->cells
) {
140 RTLIL::Cell
*c
= new RTLIL::Cell(*it
.second
);
141 if (!flatten_mode
&& c
->type
.substr(0, 2) == "\\$")
142 c
->type
= c
->type
.substr(1);
143 apply_prefix(cell
->name
, c
->name
);
144 for (auto &it2
: c
->connections
) {
145 apply_prefix(cell
->name
, it2
.second
, module
);
146 port_signal_map
.apply(it2
.second
);
148 module
->cells
[c
->name
] = c
;
149 design
->select(module
, c
);
150 new_members
.select(module
, c
);
153 for (auto &it
: tpl
->connections
) {
154 RTLIL::SigSig c
= it
;
155 apply_prefix(cell
->name
, c
.first
, module
);
156 apply_prefix(cell
->name
, c
.second
, module
);
157 port_signal_map
.apply(c
.first
);
158 port_signal_map
.apply(c
.second
);
159 module
->connections
.push_back(c
);
162 module
->cells
.erase(cell
->name
);
166 static bool techmap_module(RTLIL::Design
*design
, RTLIL::Module
*module
, RTLIL::Design
*map
, std::set
<RTLIL::Cell
*> &handled_cells
,
167 const std::map
<RTLIL::IdString
, std::set
<RTLIL::IdString
>> &celltypeMap
, bool flatten_mode
, bool opt_mode
)
169 if (!design
->selected(module
))
172 bool did_something
= false;
173 std::vector
<std::string
> cell_names
;
174 RTLIL::Selection
new_members(false);
176 for (auto &cell_it
: module
->cells
)
177 cell_names
.push_back(cell_it
.first
);
179 for (auto &cell_name
: cell_names
)
181 if (module
->cells
.count(cell_name
) == 0)
184 RTLIL::Cell
*cell
= module
->cells
[cell_name
];
186 if (!design
->selected(module
, cell
) || handled_cells
.count(cell
) > 0)
189 if (celltypeMap
.count(cell
->type
) == 0)
192 for (auto &tpl_name
: celltypeMap
.at(cell
->type
))
194 std::string derived_name
= tpl_name
;
195 RTLIL::Module
*tpl
= map
->modules
[tpl_name
];
196 std::map
<RTLIL::IdString
, RTLIL::Const
> parameters
= cell
->parameters
;
198 for (auto conn
: cell
->connections
) {
199 if (conn
.first
.substr(0, 1) == "$")
201 if (tpl
->wires
.count(conn
.first
) > 0 && tpl
->wires
.at(conn
.first
)->port_id
> 0)
203 if (!conn
.second
.is_fully_const() || parameters
.count(conn
.first
) > 0)
205 parameters
[conn
.first
] = conn
.second
.as_const();
213 bool log_continue
= false;
214 std::pair
<RTLIL::IdString
, std::map
<RTLIL::IdString
, RTLIL::Const
>> key(tpl_name
, parameters
);
215 if (techmap_cache
.count(key
) > 0) {
216 tpl
= techmap_cache
[key
];
218 if (cell
->parameters
.size() != 0) {
219 derived_name
= tpl
->derive(map
, parameters
);
220 tpl
= map
->modules
[derived_name
];
223 techmap_cache
[key
] = tpl
;
226 if (techmap_fail_check(tpl
)) {
228 log_header("Continuing TECHMAP pass.\n");
229 log("Not using module `%s' from techmap as it contains a TECHMAP_FAIL marker wire.\n", derived_name
.c_str());
233 if (opt_mode
&& techmap_opt_cache
.count(tpl
) == 0) {
234 Pass::call(map
, "opt " + tpl
->name
);
235 techmap_opt_cache
.insert(tpl
);
240 log_header("Continuing TECHMAP pass.\n");
241 techmap_module_worker(design
, module
, cell
, tpl
, new_members
, flatten_mode
);
242 did_something
= true;
247 handled_cells
.insert(cell
);
250 if (did_something
&& opt_mode
) {
251 design
->selection_stack
.push_back(new_members
);
252 Pass::call(design
, "opt_const");
253 log_header("Continuing TECHMAP pass.\n");
254 design
->selection_stack
.pop_back();
257 return did_something
;
260 struct TechmapPass
: public Pass
{
261 TechmapPass() : Pass("techmap", "simple technology mapper") { }
264 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
266 log(" techmap [-map filename] [selection]\n");
268 log("This pass implements a very simple technology mapper that replaces cells in\n");
269 log("the design with implementations given in form of a verilog or ilang source\n");
272 log(" -map filename\n");
273 log(" the library of cell implementations to be used.\n");
274 log(" without this parameter a builtin library is used that\n");
275 log(" transforms the internal RTL cells to the internal gate\n");
279 log(" run 'opt' pass on all cells from map file before using them and run\n");
280 log(" 'opt_const' on all replacement cells before mapping recursively.\n");
282 log("When a module in the map file has the 'celltype' attribute set, it will match\n");
283 log("cells with a type that match the text value of this attribute.\n");
285 log("When a module in the map file contains a wire with the name 'TECHMAP_FAIL' (or\n");
286 log("one matching '*.TECHMAP_FAIL') then no substitution will be performed. The\n");
287 log("modules in the map file are tried in alphabetical order.\n");
289 log("When a module in the map file has a parameter where the according cell in the\n");
290 log("design has a port, the module from the map file is only used if the port in\n");
291 log("the design is connected to a constant value. The parameter is then set to the\n");
292 log("constant value.\n");
294 log("See 'help extract' for a pass that does the opposite thing.\n");
296 log("See 'help flatten' for a pass that does flatten the design (which is\n");
297 log("esentially techmap but using the design itself as map library).\n");
300 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
302 log_header("Executing TECHMAP pass (map to technology primitives).\n");
305 std::string filename
;
306 bool opt_mode
= false;
309 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
310 if (args
[argidx
] == "-map" && argidx
+1 < args
.size()) {
311 filename
= args
[++argidx
];
314 if (args
[argidx
] == "-opt") {
320 extra_args(args
, argidx
, design
);
322 FILE *f
= filename
.empty() ? fmemopen(stdcells_code
, strlen(stdcells_code
), "rt") : fopen(filename
.c_str(), "rt");
324 log_cmd_error("Can't open map file `%s'\n", filename
.c_str());
326 RTLIL::Design
*map
= new RTLIL::Design
;
327 Frontend::frontend_call(map
, f
, filename
.empty() ? "<stdcells.v>" : filename
,
328 (filename
.size() > 3 && filename
.substr(filename
.size()-3) == ".il") ? "ilang" : "verilog");
332 std::map
<RTLIL::IdString
, RTLIL::Module
*> modules_new
;
333 for (auto &it
: map
->modules
) {
334 if (it
.first
.substr(0, 2) == "\\$")
335 it
.second
->name
= it
.first
.substr(1);
336 modules_new
[it
.second
->name
] = it
.second
;
338 map
->modules
.swap(modules_new
);
340 std::map
<RTLIL::IdString
, std::set
<RTLIL::IdString
>> celltypeMap
;
341 for (auto &it
: map
->modules
) {
342 if (it
.second
->attributes
.count("\\celltype") && !it
.second
->attributes
.at("\\celltype").str
.empty()) {
343 celltypeMap
[RTLIL::escape_id(it
.second
->attributes
.at("\\celltype").str
)].insert(it
.first
);
345 celltypeMap
[it
.first
].insert(it
.first
);
348 bool did_something
= true;
349 std::set
<RTLIL::Cell
*> handled_cells
;
350 while (did_something
) {
351 did_something
= false;
352 for (auto &mod_it
: design
->modules
)
353 if (techmap_module(design
, mod_it
.second
, map
, handled_cells
, celltypeMap
, false, opt_mode
))
354 did_something
= true;
359 log("No more expansions possible.\n");
360 techmap_cache
.clear();
361 techmap_fail_cache
.clear();
362 techmap_opt_cache
.clear();
368 struct FlattenPass
: public Pass
{
369 FlattenPass() : Pass("flatten", "flatten design") { }
372 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
374 log(" flatten [selection]\n");
376 log("This pass flattens the design by replacing cells by their implementation. This\n");
377 log("pass is very simmilar to the 'techmap' pass. The only difference is that this\n");
378 log("pass is using the current design as mapping library.\n");
381 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
383 log_header("Executing FLATTEN pass (flatten design).\n");
386 extra_args(args
, 1, design
);
388 std::map
<RTLIL::IdString
, std::set
<RTLIL::IdString
>> celltypeMap
;
389 for (auto &it
: design
->modules
)
390 celltypeMap
[it
.first
].insert(it
.first
);
392 bool did_something
= true;
393 std::set
<RTLIL::Cell
*> handled_cells
;
394 while (did_something
) {
395 did_something
= false;
396 for (auto &mod_it
: design
->modules
)
397 if (techmap_module(design
, mod_it
.second
, design
, handled_cells
, celltypeMap
, true, false))
398 did_something
= true;
401 log("No more expansions possible.\n");
402 techmap_cache
.clear();
403 techmap_fail_cache
.clear();
404 techmap_opt_cache
.clear();