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Improved attributes API and handling of "src" attributes
[yosys.git] / passes / techmap / techmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/utils.h"
22 #include "kernel/sigtools.h"
23 #include "libs/sha1/sha1.h"
24
25 #include <stdlib.h>
26 #include <stdio.h>
27 #include <string.h>
28
29 #include "simplemap.h"
30 #include "passes/techmap/techmap.inc"
31
32 YOSYS_NAMESPACE_BEGIN
33
34 // see maccmap.cc
35 extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false);
36
37 YOSYS_NAMESPACE_END
38
39 USING_YOSYS_NAMESPACE
40 PRIVATE_NAMESPACE_BEGIN
41
42 void apply_prefix(std::string prefix, std::string &id)
43 {
44 if (id[0] == '\\')
45 id = prefix + "." + id.substr(1);
46 else
47 id = "$techmap" + prefix + "." + id;
48 }
49
50 void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
51 {
52 std::vector<RTLIL::SigChunk> chunks = sig;
53 for (auto &chunk : chunks)
54 if (chunk.wire != NULL) {
55 std::string wire_name = chunk.wire->name.str();
56 apply_prefix(prefix, wire_name);
57 log_assert(module->wires_.count(wire_name) > 0);
58 chunk.wire = module->wires_[wire_name];
59 }
60 sig = chunks;
61 }
62
63 struct TechmapWorker
64 {
65 std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
66 std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
67 std::map<RTLIL::Module*, bool> techmap_do_cache;
68 std::set<RTLIL::Module*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Module>> module_queue;
69 dict<Module*, SigMap> sigmaps;
70
71 pool<IdString> flatten_do_list;
72 pool<IdString> flatten_done_list;
73 pool<Cell*> flatten_keep_list;
74
75 struct TechmapWireData {
76 RTLIL::Wire *wire;
77 RTLIL::SigSpec value;
78 };
79
80 typedef std::map<std::string, std::vector<TechmapWireData>> TechmapWires;
81
82 bool extern_mode;
83 bool assert_mode;
84 bool flatten_mode;
85 bool recursive_mode;
86 bool autoproc_mode;
87
88 TechmapWorker()
89 {
90 extern_mode = false;
91 assert_mode = false;
92 flatten_mode = false;
93 recursive_mode = false;
94 autoproc_mode = false;
95 }
96
97 std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose)
98 {
99 std::string constmap_info;
100 std::map<RTLIL::SigBit, std::pair<RTLIL::IdString, int>> connbits_map;
101
102 for (auto conn : cell->connections())
103 for (int i = 0; i < GetSize(conn.second); i++) {
104 RTLIL::SigBit bit = sigmap(conn.second[i]);
105 if (bit.wire == nullptr) {
106 if (verbose)
107 log(" Constant input on bit %d of port %s: %s\n", i, log_id(conn.first), log_signal(bit));
108 constmap_info += stringf("|%s %d %d", log_id(conn.first), i, bit.data);
109 } else if (connbits_map.count(bit)) {
110 if (verbose)
111 log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, log_id(conn.first),
112 connbits_map.at(bit).second, log_id(connbits_map.at(bit).first));
113 constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i,
114 log_id(connbits_map.at(bit).first), connbits_map.at(bit).second);
115 } else {
116 connbits_map[bit] = std::pair<RTLIL::IdString, int>(conn.first, i);
117 constmap_info += stringf("|%s %d", log_id(conn.first), i);
118 }
119 }
120
121 return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str());
122 }
123
124 TechmapWires techmap_find_special_wires(RTLIL::Module *module)
125 {
126 TechmapWires result;
127
128 if (module == NULL)
129 return result;
130
131 for (auto &it : module->wires_) {
132 const char *p = it.first.c_str();
133 if (*p == '$')
134 continue;
135
136 const char *q = strrchr(p+1, '.');
137 p = q ? q+1 : p+1;
138
139 if (!strncmp(p, "_TECHMAP_", 9)) {
140 TechmapWireData record;
141 record.wire = it.second;
142 record.value = it.second;
143 result[p].push_back(record);
144 it.second->attributes["\\keep"] = RTLIL::Const(1);
145 it.second->attributes["\\_techmap_special_"] = RTLIL::Const(1);
146 }
147 }
148
149 if (!result.empty()) {
150 SigMap sigmap(module);
151 for (auto &it1 : result)
152 for (auto &it2 : it1.second)
153 sigmap.apply(it2.value);
154 }
155
156 return result;
157 }
158
159 void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl)
160 {
161 if (tpl->processes.size() != 0) {
162 log("Technology map yielded processes:\n");
163 for (auto &it : tpl->processes)
164 log(" %s",RTLIL::id2cstr(it.first));
165 if (autoproc_mode) {
166 Pass::call_on_module(tpl->design, tpl, "proc");
167 log_assert(GetSize(tpl->processes) == 0);
168 } else
169 log_error("Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).\n");
170 }
171
172 std::string orig_cell_name;
173 pool<string> extra_src_attrs;
174
175 if (!flatten_mode)
176 {
177 for (auto &it : tpl->cells_)
178 if (it.first == "\\_TECHMAP_REPLACE_") {
179 orig_cell_name = cell->name.str();
180 module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
181 break;
182 }
183
184 extra_src_attrs = cell->get_strpool_attribute("\\src");
185 }
186
187 dict<IdString, IdString> memory_renames;
188
189 for (auto &it : tpl->memories) {
190 std::string m_name = it.first.str();
191 apply_prefix(cell->name.str(), m_name);
192 RTLIL::Memory *m = new RTLIL::Memory;
193 m->name = m_name;
194 m->width = it.second->width;
195 m->start_offset = it.second->start_offset;
196 m->size = it.second->size;
197 m->attributes = it.second->attributes;
198 if (m->attributes.count("\\src"))
199 m->add_strpool_attribute("\\src", extra_src_attrs);
200 module->memories[m->name] = m;
201 memory_renames[it.first] = m->name;
202 design->select(module, m);
203 }
204
205 std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
206
207 for (auto &it : tpl->wires_) {
208 if (it.second->port_id > 0)
209 positional_ports[stringf("$%d", it.second->port_id)] = it.first;
210 std::string w_name = it.second->name.str();
211 apply_prefix(cell->name.str(), w_name);
212 RTLIL::Wire *w = module->addWire(w_name, it.second);
213 w->port_input = false;
214 w->port_output = false;
215 w->port_id = 0;
216 if (it.second->get_bool_attribute("\\_techmap_special_"))
217 w->attributes.clear();
218 if (w->attributes.count("\\src"))
219 w->add_strpool_attribute("\\src", extra_src_attrs);
220 design->select(module, w);
221 }
222
223 SigMap port_signal_map;
224
225 for (auto &it : cell->connections()) {
226 RTLIL::IdString portname = it.first;
227 if (positional_ports.count(portname) > 0)
228 portname = positional_ports.at(portname);
229 if (tpl->wires_.count(portname) == 0 || tpl->wires_.at(portname)->port_id == 0) {
230 if (portname.substr(0, 1) == "$")
231 log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
232 continue;
233 }
234 RTLIL::Wire *w = tpl->wires_.at(portname);
235 RTLIL::SigSig c;
236 if (w->port_output) {
237 c.first = it.second;
238 c.second = RTLIL::SigSpec(w);
239 apply_prefix(cell->name.str(), c.second, module);
240 } else {
241 c.first = RTLIL::SigSpec(w);
242 c.second = it.second;
243 apply_prefix(cell->name.str(), c.first, module);
244 }
245 if (c.second.size() > c.first.size())
246 c.second.remove(c.first.size(), c.second.size() - c.first.size());
247 if (c.second.size() < c.first.size())
248 c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
249 log_assert(c.first.size() == c.second.size());
250 if (flatten_mode) {
251 // more conservative approach:
252 // connect internal and external wires
253 if (sigmaps.count(module) == 0)
254 sigmaps[module].set(module);
255 if (sigmaps.at(module)(c.first).has_const())
256 log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
257 log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second));
258 module->connect(c);
259 } else {
260 // approach that yields nicer outputs:
261 // replace internal wires that are connected to external wires
262 if (w->port_output)
263 port_signal_map.add(c.second, c.first);
264 else
265 port_signal_map.add(c.first, c.second);
266 }
267 }
268
269 for (auto &it : tpl->cells_)
270 {
271 std::string c_name = it.second->name.str();
272
273 if (!flatten_mode && c_name == "\\_TECHMAP_REPLACE_")
274 c_name = orig_cell_name;
275 else
276 apply_prefix(cell->name.str(), c_name);
277
278 RTLIL::Cell *c = module->addCell(c_name, it.second);
279 design->select(module, c);
280
281 if (!flatten_mode && c->type.substr(0, 2) == "\\$")
282 c->type = c->type.substr(1);
283
284 for (auto &it2 : c->connections_) {
285 apply_prefix(cell->name.str(), it2.second, module);
286 port_signal_map.apply(it2.second);
287 }
288
289 if (c->type == "$memrd" || c->type == "$memwr") {
290 IdString memid = c->getParam("\\MEMID").decode_string();
291 log_assert(memory_renames.count(memid));
292 c->setParam("\\MEMID", Const(memory_renames[memid].str()));
293 }
294
295 if (c->attributes.count("\\src"))
296 c->add_strpool_attribute("\\src", extra_src_attrs);
297 }
298
299 for (auto &it : tpl->connections()) {
300 RTLIL::SigSig c = it;
301 apply_prefix(cell->name.str(), c.first, module);
302 apply_prefix(cell->name.str(), c.second, module);
303 port_signal_map.apply(c.first);
304 port_signal_map.apply(c.second);
305 module->connect(c);
306 }
307
308 module->remove(cell);
309 }
310
311 bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
312 const std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> &celltypeMap, bool in_recursion)
313 {
314 std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";
315
316 if (!design->selected(module))
317 return false;
318
319 bool log_continue = false;
320 bool did_something = false;
321
322 SigMap sigmap(module);
323
324 TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
325 std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
326 std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
327
328 for (auto cell : module->cells())
329 {
330 if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
331 continue;
332
333 std::string cell_type = cell->type.str();
334 if (in_recursion && cell_type.substr(0, 2) == "\\$")
335 cell_type = cell_type.substr(1);
336
337 if (celltypeMap.count(cell_type) == 0) {
338 if (assert_mode && cell_type.back() != '_')
339 log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type));
340 continue;
341 }
342
343 if (flatten_mode) {
344 bool keepit = cell->get_bool_attribute("\\keep_hierarchy");
345 for (auto &tpl_name : celltypeMap.at(cell_type))
346 if (map->modules_[tpl_name]->get_bool_attribute("\\keep_hierarchy"))
347 keepit = true;
348 if (keepit) {
349 if (!flatten_keep_list[cell]) {
350 log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell));
351 flatten_keep_list.insert(cell);
352 }
353 if (!flatten_done_list[cell->type])
354 flatten_do_list.insert(cell->type);
355 continue;
356 }
357 }
358
359 for (auto &conn : cell->connections())
360 {
361 RTLIL::SigSpec sig = sigmap(conn.second);
362 sig.remove_const();
363
364 if (GetSize(sig) == 0)
365 continue;
366
367 for (auto &tpl_name : celltypeMap.at(cell_type)) {
368 RTLIL::Module *tpl = map->modules_[tpl_name];
369 RTLIL::Wire *port = tpl->wire(conn.first);
370 if (port && port->port_input)
371 cell_to_inbit[cell].insert(sig.begin(), sig.end());
372 if (port && port->port_output)
373 for (auto &bit : sig)
374 outbit_to_cell[bit].insert(cell);
375 }
376 }
377
378 cells.node(cell);
379 }
380
381 for (auto &it_right : cell_to_inbit)
382 for (auto &it_sigbit : it_right.second)
383 for (auto &it_left : outbit_to_cell[it_sigbit])
384 cells.edge(it_left, it_right.first);
385
386 cells.sort();
387
388 for (auto cell : cells.sorted)
389 {
390 log_assert(handled_cells.count(cell) == 0);
391 log_assert(cell == module->cell(cell->name));
392 bool mapped_cell = false;
393
394 std::string cell_type = cell->type.str();
395 if (in_recursion && cell_type.substr(0, 2) == "\\$")
396 cell_type = cell_type.substr(1);
397
398 for (auto &tpl_name : celltypeMap.at(cell_type))
399 {
400 RTLIL::IdString derived_name = tpl_name;
401 RTLIL::Module *tpl = map->modules_[tpl_name];
402 std::map<RTLIL::IdString, RTLIL::Const> parameters(cell->parameters.begin(), cell->parameters.end());
403
404 if (tpl->get_bool_attribute("\\blackbox"))
405 continue;
406
407 if (!flatten_mode)
408 {
409 std::string extmapper_name;
410
411 if (tpl->get_bool_attribute("\\techmap_simplemap"))
412 extmapper_name = "simplemap";
413
414 if (tpl->get_bool_attribute("\\techmap_maccmap"))
415 extmapper_name = "maccmap";
416
417 if (tpl->attributes.count("\\techmap_wrap"))
418 extmapper_name = "wrap";
419
420 if (!extmapper_name.empty())
421 {
422 cell->type = cell_type;
423
424 if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
425 {
426 std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
427
428 for (auto &c : cell->parameters)
429 m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
430
431 if (extmapper_name == "wrap")
432 m_name += ":" + sha1(tpl->attributes.at("\\techmap_wrap").decode_string());
433
434 RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
435 RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
436
437 if (extmapper_module == nullptr)
438 {
439 extmapper_module = extmapper_design->addModule(m_name);
440 RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
441
442 int port_counter = 1;
443 for (auto &c : extmapper_cell->connections_) {
444 RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
445 if (w->name == "\\Y" || w->name == "\\Q")
446 w->port_output = true;
447 else
448 w->port_input = true;
449 w->port_id = port_counter++;
450 c.second = w;
451 }
452
453 extmapper_module->fixup_ports();
454 extmapper_module->check();
455
456 if (extmapper_name == "simplemap") {
457 log("Creating %s with simplemap.\n", log_id(extmapper_module));
458 if (simplemap_mappers.count(extmapper_cell->type) == 0)
459 log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
460 simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
461 extmapper_module->remove(extmapper_cell);
462 }
463
464 if (extmapper_name == "maccmap") {
465 log("Creating %s with maccmap.\n", log_id(extmapper_module));
466 if (extmapper_cell->type != "$macc")
467 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
468 maccmap(extmapper_module, extmapper_cell);
469 extmapper_module->remove(extmapper_cell);
470 }
471
472 if (extmapper_name == "wrap") {
473 std::string cmd_string = tpl->attributes.at("\\techmap_wrap").decode_string();
474 log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
475 Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
476 log_continue = true;
477 }
478 }
479
480 cell->type = extmapper_module->name;
481 cell->parameters.clear();
482
483 if (!extern_mode || in_recursion) {
484 tpl = extmapper_module;
485 goto use_wrapper_tpl;
486 }
487
488 log("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
489 }
490 else
491 {
492 log("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
493
494 if (extmapper_name == "simplemap") {
495 if (simplemap_mappers.count(cell->type) == 0)
496 log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
497 simplemap_mappers.at(cell->type)(module, cell);
498 }
499
500 if (extmapper_name == "maccmap") {
501 if (cell->type != "$macc")
502 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
503 maccmap(module, cell);
504 }
505
506 module->remove(cell);
507 cell = NULL;
508 }
509
510 did_something = true;
511 mapped_cell = true;
512 break;
513 }
514
515 for (auto conn : cell->connections()) {
516 if (conn.first.substr(0, 1) == "$")
517 continue;
518 if (tpl->wires_.count(conn.first) > 0 && tpl->wires_.at(conn.first)->port_id > 0)
519 continue;
520 if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
521 goto next_tpl;
522 parameters[conn.first] = conn.second.as_const();
523 }
524
525 if (0) {
526 next_tpl:
527 continue;
528 }
529
530 if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0)
531 parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type);
532
533 for (auto conn : cell->connections()) {
534 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
535 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
536 for (auto &bit : v)
537 bit = RTLIL::SigBit(bit.wire == NULL ? RTLIL::State::S1 : RTLIL::State::S0);
538 parameters[stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
539 }
540 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))) != 0) {
541 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
542 for (auto &bit : v)
543 if (bit.wire != NULL)
544 bit = RTLIL::SigBit(RTLIL::State::Sx);
545 parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
546 }
547 }
548
549 int unique_bit_id_counter = 0;
550 std::map<RTLIL::SigBit, int> unique_bit_id;
551 unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++;
552 unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++;
553 unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++;
554 unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
555
556 for (auto conn : cell->connections())
557 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
558 for (auto &bit : sigmap(conn.second).to_sigbit_vector())
559 if (unique_bit_id.count(bit) == 0)
560 unique_bit_id[bit] = unique_bit_id_counter++;
561 }
562
563 int bits = 0;
564 for (int i = 0; i < 32; i++)
565 if (((unique_bit_id_counter-1) & (1 << i)) != 0)
566 bits = i;
567 if (tpl->avail_parameters.count("\\_TECHMAP_BITS_CONNMAP_"))
568 parameters["\\_TECHMAP_BITS_CONNMAP_"] = bits;
569
570 for (auto conn : cell->connections())
571 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
572 RTLIL::Const value;
573 for (auto &bit : sigmap(conn.second).to_sigbit_vector()) {
574 RTLIL::Const chunk(unique_bit_id.at(bit), bits);
575 value.bits.insert(value.bits.end(), chunk.bits.begin(), chunk.bits.end());
576 }
577 parameters[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))] = value;
578 }
579 }
580
581 if (0) {
582 use_wrapper_tpl:;
583 // do not register techmap_wrap modules with techmap_cache
584 } else {
585 std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
586 if (techmap_cache.count(key) > 0) {
587 tpl = techmap_cache[key];
588 } else {
589 if (cell->parameters.size() != 0) {
590 derived_name = tpl->derive(map, dict<RTLIL::IdString, RTLIL::Const>(parameters.begin(), parameters.end()));
591 tpl = map->module(derived_name);
592 log_continue = true;
593 }
594 techmap_cache[key] = tpl;
595 }
596 }
597
598 if (flatten_mode) {
599 techmap_do_cache[tpl] = true;
600 } else {
601 RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false));
602 if (constmapped_tpl != nullptr)
603 tpl = constmapped_tpl;
604 }
605
606 if (techmap_do_cache.count(tpl) == 0)
607 {
608 bool keep_running = true;
609 techmap_do_cache[tpl] = true;
610
611 std::set<std::string> techmap_wire_names;
612
613 while (keep_running)
614 {
615 TechmapWires twd = techmap_find_special_wires(tpl);
616 keep_running = false;
617
618 for (auto &it : twd)
619 techmap_wire_names.insert(it.first);
620
621 for (auto &it : twd["_TECHMAP_FAIL_"]) {
622 RTLIL::SigSpec value = it.value;
623 if (value.is_fully_const() && value.as_bool()) {
624 log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
625 derived_name.c_str(), RTLIL::id2cstr(it.wire->name), log_signal(value));
626 techmap_do_cache[tpl] = false;
627 }
628 }
629
630 if (!techmap_do_cache[tpl])
631 break;
632
633 for (auto &it : twd)
634 {
635 if (it.first.substr(0, 12) != "_TECHMAP_DO_" || it.second.empty())
636 continue;
637
638 auto &data = it.second.front();
639
640 if (!data.value.is_fully_const())
641 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));
642
643 techmap_wire_names.erase(it.first);
644
645 const char *p = data.wire->name.c_str();
646 const char *q = strrchr(p+1, '.');
647 q = q ? q : p+1;
648
649 std::string cmd_string = data.value.as_const().decode_string();
650
651 restart_eval_cmd_string:
652 if (cmd_string.rfind("CONSTMAP; ", 0) == 0)
653 {
654 cmd_string = cmd_string.substr(strlen("CONSTMAP; "));
655
656 log("Analyzing pattern of constant bits for this cell:\n");
657 RTLIL::IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
658 log("Creating constmapped module `%s'.\n", log_id(new_tpl_name));
659 log_assert(map->module(new_tpl_name) == nullptr);
660
661 RTLIL::Module *new_tpl = map->addModule(new_tpl_name);
662 tpl->cloneInto(new_tpl);
663
664 techmap_do_cache.erase(tpl);
665 techmap_do_cache[new_tpl] = true;
666 tpl = new_tpl;
667
668 std::map<RTLIL::SigBit, RTLIL::SigBit> port_new2old_map;
669 std::map<RTLIL::SigBit, RTLIL::SigBit> port_connmap;
670 std::map<RTLIL::SigBit, RTLIL::SigBit> cellbits_to_tplbits;
671
672 for (auto wire : tpl->wires().to_vector())
673 {
674 if (!wire->port_input || wire->port_output)
675 continue;
676
677 RTLIL::IdString port_name = wire->name;
678 tpl->rename(wire, NEW_ID);
679
680 RTLIL::Wire *new_wire = tpl->addWire(port_name, wire);
681 wire->port_input = false;
682 wire->port_id = 0;
683
684 for (int i = 0; i < wire->width; i++) {
685 port_new2old_map[RTLIL::SigBit(new_wire, i)] = RTLIL::SigBit(wire, i);
686 port_connmap[RTLIL::SigBit(wire, i)] = RTLIL::SigBit(new_wire, i);
687 }
688 }
689
690 for (auto conn : cell->connections())
691 for (int i = 0; i < GetSize(conn.second); i++)
692 {
693 RTLIL::SigBit bit = sigmap(conn.second[i]);
694 RTLIL::SigBit tplbit(tpl->wire(conn.first), i);
695
696 if (bit.wire == nullptr)
697 {
698 RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
699 port_connmap.at(oldbit) = bit;
700 }
701 else if (cellbits_to_tplbits.count(bit))
702 {
703 RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
704 port_connmap.at(oldbit) = cellbits_to_tplbits[bit];
705 }
706 else
707 cellbits_to_tplbits[bit] = tplbit;
708 }
709
710 RTLIL::SigSig port_conn;
711 for (auto &it : port_connmap) {
712 port_conn.first.append_bit(it.first);
713 port_conn.second.append_bit(it.second);
714 }
715 tpl->connect(port_conn);
716
717 tpl->check();
718 goto restart_eval_cmd_string;
719 }
720
721 if (cmd_string.rfind("RECURSION; ", 0) == 0)
722 {
723 cmd_string = cmd_string.substr(strlen("RECURSION; "));
724 while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
725 goto restart_eval_cmd_string;
726 }
727
728 Pass::call_on_module(map, tpl, cmd_string);
729
730 log_assert(!strncmp(q, "_TECHMAP_DO_", 12));
731 std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
732 while (tpl->wires_.count(new_name))
733 new_name += "_";
734 tpl->rename(data.wire->name, new_name);
735
736 keep_running = true;
737 break;
738 }
739 }
740
741 TechmapWires twd = techmap_find_special_wires(tpl);
742 for (auto &it : twd) {
743 if (it.first != "_TECHMAP_FAIL_" && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
744 log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str());
745 if (techmap_do_cache[tpl])
746 for (auto &it2 : it.second)
747 if (!it2.value.is_fully_const())
748 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
749 techmap_wire_names.erase(it.first);
750 }
751
752 for (auto &it : techmap_wire_names)
753 log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it));
754
755 if (recursive_mode) {
756 if (log_continue) {
757 log_header("Continuing TECHMAP pass.\n");
758 log_continue = false;
759 }
760 while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
761 }
762 }
763
764 if (techmap_do_cache.at(tpl) == false)
765 continue;
766
767 if (log_continue) {
768 log_header("Continuing TECHMAP pass.\n");
769 log_continue = false;
770 }
771
772 if (extern_mode && !in_recursion)
773 {
774 std::string m_name = stringf("$extern:%s", log_id(tpl));
775
776 if (!design->module(m_name))
777 {
778 RTLIL::Module *m = design->addModule(m_name);
779 tpl->cloneInto(m);
780
781 for (auto cell : m->cells()) {
782 if (cell->type.substr(0, 2) == "\\$")
783 cell->type = cell->type.substr(1);
784 }
785
786 module_queue.insert(m);
787 }
788
789 log("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name));
790 cell->type = m_name;
791 cell->parameters.clear();
792 }
793 else
794 {
795 log("%s %s.%s using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(tpl));
796 techmap_module_worker(design, module, cell, tpl);
797 cell = NULL;
798 }
799 did_something = true;
800 mapped_cell = true;
801 break;
802 }
803
804 if (assert_mode && !mapped_cell)
805 log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
806
807 handled_cells.insert(cell);
808 }
809
810 if (log_continue) {
811 log_header("Continuing TECHMAP pass.\n");
812 log_continue = false;
813 }
814
815 return did_something;
816 }
817 };
818
819 struct TechmapPass : public Pass {
820 TechmapPass() : Pass("techmap", "generic technology mapper") { }
821 virtual void help()
822 {
823 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
824 log("\n");
825 log(" techmap [-map filename] [selection]\n");
826 log("\n");
827 log("This pass implements a very simple technology mapper that replaces cells in\n");
828 log("the design with implementations given in form of a verilog or ilang source\n");
829 log("file.\n");
830 log("\n");
831 log(" -map filename\n");
832 log(" the library of cell implementations to be used.\n");
833 log(" without this parameter a builtin library is used that\n");
834 log(" transforms the internal RTL cells to the internal gate\n");
835 log(" library.\n");
836 log("\n");
837 log(" -map %%<design-name>\n");
838 log(" like -map above, but with an in-memory design instead of a file.\n");
839 log("\n");
840 log(" -extern\n");
841 log(" load the cell implementations as separate modules into the design\n");
842 log(" instead of inlining them.\n");
843 log("\n");
844 log(" -max_iter <number>\n");
845 log(" only run the specified number of iterations.\n");
846 log("\n");
847 log(" -recursive\n");
848 log(" instead of the iterative breadth-first algorithm use a recursive\n");
849 log(" depth-first algorithm. both methods should yield equivialent results,\n");
850 log(" but may differ in performance.\n");
851 log("\n");
852 log(" -autoproc\n");
853 log(" Automatically call \"proc\" on implementations that contain processes.\n");
854 log("\n");
855 log(" -assert\n");
856 log(" this option will cause techmap to exit with an error if it can't map\n");
857 log(" a selected cell. only cell types that end on an underscore are accepted\n");
858 log(" as final cell types by this mode.\n");
859 log("\n");
860 log(" -D <define>, -I <incdir>\n");
861 log(" this options are passed as-is to the verilog frontend for loading the\n");
862 log(" map file. Note that the verilog frontend is also called with the\n");
863 log(" '-ignore_redef' option set.\n");
864 log("\n");
865 log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
866 log("match cells with a type that match the text value of this attribute. Otherwise\n");
867 log("the module name will be used to match the cell.\n");
868 log("\n");
869 log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
870 log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
871 log("\n");
872 log("When a module in the map file has the 'techmap_maccmap' attribute set, techmap\n");
873 log("will use 'maccmap' (see 'help maccmap') to map cells matching the module.\n");
874 log("\n");
875 log("When a module in the map file has the 'techmap_wrap' attribute set, techmap\n");
876 log("will create a wrapper for the cell and then run the command string that the\n");
877 log("attribute is set to on the wrapper module.\n");
878 log("\n");
879 log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
880 log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
881 log("the mapping module to the techmap command. At the moment the following special\n");
882 log("wires are supported:\n");
883 log("\n");
884 log(" _TECHMAP_FAIL_\n");
885 log(" When this wire is set to a non-zero constant value, techmap will not\n");
886 log(" use this module and instead try the next module with a matching\n");
887 log(" 'techmap_celltype' attribute.\n");
888 log("\n");
889 log(" When such a wire exists but does not have a constant value after all\n");
890 log(" _TECHMAP_DO_* commands have been executed, an error is generated.\n");
891 log("\n");
892 log(" _TECHMAP_DO_*\n");
893 log(" This wires are evaluated in alphabetical order. The constant text value\n");
894 log(" of this wire is a yosys command (or sequence of commands) that is run\n");
895 log(" by techmap on the module. A common use case is to run 'proc' on modules\n");
896 log(" that are written using always-statements.\n");
897 log("\n");
898 log(" When such a wire has a non-constant value at the time it is to be\n");
899 log(" evaluated, an error is produced. That means it is possible for such a\n");
900 log(" wire to start out as non-constant and evaluate to a constant value\n");
901 log(" during processing of other _TECHMAP_DO_* commands.\n");
902 log("\n");
903 log(" A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.\n");
904 log(" in this case techmap will create a copy for each distinct configuration\n");
905 log(" of constant inputs and shorted inputs at this point and import the\n");
906 log(" constant and connected bits into the map module. All further commands\n");
907 log(" are executed in this copy. This is a very convenient way of creating\n");
908 log(" optimizied specializations of techmap modules without using the special\n");
909 log(" parameters described below.\n");
910 log("\n");
911 log(" A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.\n");
912 log(" then techmap will recursively replace the cells in the module with their\n");
913 log(" implementation. This is not affected by the -max_iter option.\n");
914 log("\n");
915 log(" It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n");
916 log("\n");
917 log("In addition to this special wires, techmap also supports special parameters in\n");
918 log("modules in the map file:\n");
919 log("\n");
920 log(" _TECHMAP_CELLTYPE_\n");
921 log(" When a parameter with this name exists, it will be set to the type name\n");
922 log(" of the cell that matches the module.\n");
923 log("\n");
924 log(" _TECHMAP_CONSTMSK_<port-name>_\n");
925 log(" _TECHMAP_CONSTVAL_<port-name>_\n");
926 log(" When this pair of parameters is available in a module for a port, then\n");
927 log(" former has a 1-bit for each constant input bit and the latter has the\n");
928 log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
929 log("\n");
930 log(" _TECHMAP_BITS_CONNMAP_\n");
931 log(" _TECHMAP_CONNMAP_<port-name>_\n");
932 log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
933 log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n");
934 log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n");
935 log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n");
936 log(" This can be used to detect shorted inputs.\n");
937 log("\n");
938 log("When a module in the map file has a parameter where the according cell in the\n");
939 log("design has a port, the module from the map file is only used if the port in\n");
940 log("the design is connected to a constant value. The parameter is then set to the\n");
941 log("constant value.\n");
942 log("\n");
943 log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
944 log("of the cell that is beeing replaced.\n");
945 log("\n");
946 log("See 'help extract' for a pass that does the opposite thing.\n");
947 log("\n");
948 log("See 'help flatten' for a pass that does flatten the design (which is\n");
949 log("esentially techmap but using the design itself as map library).\n");
950 log("\n");
951 }
952 virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
953 {
954 log_header("Executing TECHMAP pass (map to technology primitives).\n");
955 log_push();
956
957 TechmapWorker worker;
958 simplemap_get_mappers(worker.simplemap_mappers);
959
960 std::vector<std::string> map_files;
961 std::string verilog_frontend = "verilog -ignore_redef";
962 int max_iter = -1;
963
964 size_t argidx;
965 for (argidx = 1; argidx < args.size(); argidx++) {
966 if (args[argidx] == "-map" && argidx+1 < args.size()) {
967 map_files.push_back(args[++argidx]);
968 continue;
969 }
970 if (args[argidx] == "-max_iter" && argidx+1 < args.size()) {
971 max_iter = atoi(args[++argidx].c_str());
972 continue;
973 }
974 if (args[argidx] == "-D" && argidx+1 < args.size()) {
975 verilog_frontend += " -D " + args[++argidx];
976 continue;
977 }
978 if (args[argidx] == "-I" && argidx+1 < args.size()) {
979 verilog_frontend += " -I " + args[++argidx];
980 continue;
981 }
982 if (args[argidx] == "-assert") {
983 worker.assert_mode = true;
984 continue;
985 }
986 if (args[argidx] == "-extern") {
987 worker.extern_mode = true;
988 continue;
989 }
990 if (args[argidx] == "-recursive") {
991 worker.recursive_mode = true;
992 continue;
993 }
994 if (args[argidx] == "-autoproc") {
995 worker.autoproc_mode = true;
996 continue;
997 }
998 break;
999 }
1000 extra_args(args, argidx, design);
1001
1002 RTLIL::Design *map = new RTLIL::Design;
1003 if (map_files.empty()) {
1004 std::istringstream f(stdcells_code);
1005 Frontend::frontend_call(map, &f, "<techmap.v>", verilog_frontend);
1006 } else
1007 for (auto &fn : map_files)
1008 if (fn.substr(0, 1) == "%") {
1009 if (!saved_designs.count(fn.substr(1))) {
1010 delete map;
1011 log_cmd_error("Can't saved design `%s'.\n", fn.c_str()+1);
1012 }
1013 for (auto mod : saved_designs.at(fn.substr(1))->modules())
1014 if (!map->has(mod->name))
1015 map->add(mod->clone());
1016 } else {
1017 std::ifstream f;
1018 rewrite_filename(fn);
1019 f.open(fn.c_str());
1020 if (f.fail())
1021 log_cmd_error("Can't open map file `%s'\n", fn.c_str());
1022 Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend);
1023 }
1024
1025 std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
1026 for (auto &it : map->modules_) {
1027 if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) {
1028 char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str());
1029 for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
1030 celltypeMap[RTLIL::escape_id(q)].insert(it.first);
1031 free(p);
1032 } else {
1033 string module_name = it.first.str();
1034 if (module_name.substr(0, 2) == "\\$")
1035 module_name = module_name.substr(1);
1036 celltypeMap[module_name].insert(it.first);
1037 }
1038 }
1039
1040 for (auto module : design->modules())
1041 worker.module_queue.insert(module);
1042
1043 while (!worker.module_queue.empty())
1044 {
1045 RTLIL::Module *module = *worker.module_queue.begin();
1046 worker.module_queue.erase(module);
1047
1048 bool did_something = true;
1049 std::set<RTLIL::Cell*> handled_cells;
1050 while (did_something) {
1051 did_something = false;
1052 if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
1053 did_something = true;
1054 if (did_something)
1055 module->check();
1056 if (max_iter > 0 && --max_iter == 0)
1057 break;
1058 }
1059 }
1060
1061 log("No more expansions possible.\n");
1062 delete map;
1063
1064 log_pop();
1065 }
1066 } TechmapPass;
1067
1068 struct FlattenPass : public Pass {
1069 FlattenPass() : Pass("flatten", "flatten design") { }
1070 virtual void help()
1071 {
1072 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1073 log("\n");
1074 log(" flatten [selection]\n");
1075 log("\n");
1076 log("This pass flattens the design by replacing cells by their implementation. This\n");
1077 log("pass is very simmilar to the 'techmap' pass. The only difference is that this\n");
1078 log("pass is using the current design as mapping library.\n");
1079 log("\n");
1080 log("Cells and/or modules with the 'keep_hiearchy' attribute set will not be\n");
1081 log("flattened by this command.\n");
1082 log("\n");
1083 }
1084 virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
1085 {
1086 log_header("Executing FLATTEN pass (flatten design).\n");
1087 log_push();
1088
1089 extra_args(args, 1, design);
1090
1091 TechmapWorker worker;
1092 worker.flatten_mode = true;
1093
1094 std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
1095 for (auto module : design->modules())
1096 celltypeMap[module->name].insert(module->name);
1097
1098 RTLIL::Module *top_mod = NULL;
1099 if (design->full_selection())
1100 for (auto mod : design->modules())
1101 if (mod->get_bool_attribute("\\top"))
1102 top_mod = mod;
1103
1104 std::set<RTLIL::Cell*> handled_cells;
1105 if (top_mod != NULL) {
1106 worker.flatten_do_list.insert(top_mod->name);
1107 while (!worker.flatten_do_list.empty()) {
1108 auto mod = design->module(*worker.flatten_do_list.begin());
1109 while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
1110 worker.flatten_done_list.insert(mod->name);
1111 worker.flatten_do_list.erase(mod->name);
1112 }
1113 } else {
1114 for (auto mod : vector<Module*>(design->modules()))
1115 while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
1116 }
1117
1118 log("No more expansions possible.\n");
1119
1120 if (top_mod != NULL)
1121 {
1122 pool<RTLIL::IdString> used_modules, new_used_modules;
1123 new_used_modules.insert(top_mod->name);
1124 while (!new_used_modules.empty()) {
1125 pool<RTLIL::IdString> queue;
1126 queue.swap(new_used_modules);
1127 for (auto modname : queue)
1128 used_modules.insert(modname);
1129 for (auto modname : queue)
1130 for (auto cell : design->module(modname)->cells())
1131 if (design->module(cell->type) && !used_modules[cell->type])
1132 new_used_modules.insert(cell->type);
1133 }
1134
1135 dict<RTLIL::IdString, RTLIL::Module*> new_modules;
1136 for (auto mod : vector<Module*>(design->modules()))
1137 if (used_modules[mod->name] || mod->get_bool_attribute("\\blackbox")) {
1138 new_modules[mod->name] = mod;
1139 } else {
1140 log("Deleting now unused module %s.\n", log_id(mod));
1141 delete mod;
1142 }
1143 design->modules_.swap(new_modules);
1144 }
1145
1146 log_pop();
1147 }
1148 } FlattenPass;
1149
1150 PRIVATE_NAMESPACE_END