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Fixed all users of SigSpec::chunks_rw() and removed it
[yosys.git] / passes / techmap / techmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/compatibility.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/log.h"
24 #include <stdlib.h>
25 #include <assert.h>
26 #include <stdio.h>
27 #include <string.h>
28
29 #include "passes/techmap/stdcells.inc"
30
31 // see simplemap.cc
32 extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
33
34 static void apply_prefix(std::string prefix, std::string &id)
35 {
36 if (id[0] == '\\')
37 id = prefix + "." + id.substr(1);
38 else
39 id = "$techmap" + prefix + "." + id;
40 }
41
42 static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
43 {
44 std::vector<RTLIL::SigChunk> chunks = sig;
45 for (auto &chunk : chunks)
46 if (chunk.wire != NULL) {
47 std::string wire_name = chunk.wire->name;
48 apply_prefix(prefix, wire_name);
49 assert(module->wires.count(wire_name) > 0);
50 chunk.wire = module->wires[wire_name];
51 }
52 sig = chunks;
53 }
54
55 struct TechmapWorker
56 {
57 std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
58 std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
59 std::map<RTLIL::Module*, bool> techmap_do_cache;
60
61 struct TechmapWireData {
62 RTLIL::Wire *wire;
63 RTLIL::SigSpec value;
64 };
65
66 typedef std::map<std::string, std::vector<TechmapWireData>> TechmapWires;
67
68 TechmapWires techmap_find_special_wires(RTLIL::Module *module)
69 {
70 TechmapWires result;
71
72 if (module == NULL)
73 return result;
74
75 for (auto &it : module->wires) {
76 const char *p = it.first.c_str();
77 if (*p == '$')
78 continue;
79
80 const char *q = strrchr(p+1, '.');
81 p = q ? q : p+1;
82
83 if (!strncmp(p, "_TECHMAP_", 9)) {
84 TechmapWireData record;
85 record.wire = it.second;
86 record.value = it.second;
87 result[p].push_back(record);
88 it.second->attributes["\\keep"] = RTLIL::Const(1);
89 it.second->attributes["\\_techmap_special_"] = RTLIL::Const(1);
90 }
91 }
92
93 if (!result.empty()) {
94 SigMap sigmap(module);
95 for (auto &it1 : result)
96 for (auto &it2 : it1.second)
97 sigmap.apply(it2.value);
98 }
99
100 return result;
101 }
102
103 void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, bool flatten_mode)
104 {
105 log("Mapping `%s.%s' using `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(tpl->name));
106
107 if (tpl->memories.size() != 0)
108 log_error("Technology map yielded memories -> this is not supported.\n");
109
110 if (tpl->processes.size() != 0) {
111 log("Technology map yielded processes:\n");
112 for (auto &it : tpl->processes)
113 log(" %s",RTLIL::id2cstr(it.first));
114 log_error("Technology map yielded processes -> this is not supported.\n");
115 }
116
117 // erase from namespace first for _TECHMAP_REPLACE_ to work
118 module->cells.erase(cell->name);
119 std::string orig_cell_name;
120
121 if (!flatten_mode)
122 for (auto &it : tpl->cells)
123 if (it.first == "\\_TECHMAP_REPLACE_") {
124 orig_cell_name = cell->name;
125 cell->name = stringf("$techmap%d", RTLIL::autoidx++) + cell->name;
126 break;
127 }
128
129 std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
130
131 for (auto &it : tpl->wires) {
132 if (it.second->port_id > 0)
133 positional_ports[stringf("$%d", it.second->port_id)] = it.first;
134 RTLIL::Wire *w = new RTLIL::Wire(*it.second);
135 apply_prefix(cell->name, w->name);
136 w->port_input = false;
137 w->port_output = false;
138 w->port_id = 0;
139 if (it.second->get_bool_attribute("\\_techmap_special_"))
140 w->attributes.clear();
141 module->add(w);
142 design->select(module, w);
143 }
144
145 SigMap port_signal_map;
146
147 for (auto &it : cell->connections) {
148 RTLIL::IdString portname = it.first;
149 if (positional_ports.count(portname) > 0)
150 portname = positional_ports.at(portname);
151 if (tpl->wires.count(portname) == 0 || tpl->wires.at(portname)->port_id == 0) {
152 if (portname.substr(0, 1) == "$")
153 log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
154 continue;
155 }
156 RTLIL::Wire *w = tpl->wires.at(portname);
157 RTLIL::SigSig c;
158 if (w->port_output) {
159 c.first = it.second;
160 c.second = RTLIL::SigSpec(w);
161 apply_prefix(cell->name, c.second, module);
162 } else {
163 c.first = RTLIL::SigSpec(w);
164 c.second = it.second;
165 apply_prefix(cell->name, c.first, module);
166 }
167 if (c.second.size() > c.first.size())
168 c.second.remove(c.first.size(), c.second.size() - c.first.size());
169 if (c.second.size() < c.first.size())
170 c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
171 assert(c.first.size() == c.second.size());
172 if (flatten_mode) {
173 // more conservative approach:
174 // connect internal and external wires
175 module->connections.push_back(c);
176 } else {
177 // approach that yields nicer outputs:
178 // replace internal wires that are connected to external wires
179 if (w->port_output)
180 port_signal_map.add(c.second, c.first);
181 else
182 port_signal_map.add(c.first, c.second);
183 }
184 }
185
186 for (auto &it : tpl->cells) {
187 RTLIL::Cell *c = new RTLIL::Cell(*it.second);
188 if (!flatten_mode && c->type.substr(0, 2) == "\\$")
189 c->type = c->type.substr(1);
190 if (!flatten_mode && c->name == "\\_TECHMAP_REPLACE_")
191 c->name = orig_cell_name;
192 else
193 apply_prefix(cell->name, c->name);
194 for (auto &it2 : c->connections) {
195 apply_prefix(cell->name, it2.second, module);
196 port_signal_map.apply(it2.second);
197 }
198 module->add(c);
199 design->select(module, c);
200 }
201
202 for (auto &it : tpl->connections) {
203 RTLIL::SigSig c = it;
204 apply_prefix(cell->name, c.first, module);
205 apply_prefix(cell->name, c.second, module);
206 port_signal_map.apply(c.first);
207 port_signal_map.apply(c.second);
208 module->connections.push_back(c);
209 }
210
211 delete cell;
212 }
213
214 bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
215 const std::map<RTLIL::IdString, std::set<RTLIL::IdString>> &celltypeMap, bool flatten_mode)
216 {
217 if (!design->selected(module))
218 return false;
219
220 bool log_continue = false;
221 bool did_something = false;
222 std::vector<std::string> cell_names;
223
224 SigMap sigmap(module);
225 for (auto &cell_it : module->cells)
226 cell_names.push_back(cell_it.first);
227
228 for (auto &cell_name : cell_names)
229 {
230 if (module->cells.count(cell_name) == 0)
231 continue;
232
233 RTLIL::Cell *cell = module->cells[cell_name];
234
235 if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
236 continue;
237
238 if (celltypeMap.count(cell->type) == 0)
239 continue;
240
241 for (auto &tpl_name : celltypeMap.at(cell->type))
242 {
243 std::string derived_name = tpl_name;
244 RTLIL::Module *tpl = map->modules[tpl_name];
245 std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters;
246
247 if (tpl->get_bool_attribute("\\blackbox"))
248 continue;
249
250 if (!flatten_mode)
251 {
252 if (tpl->get_bool_attribute("\\techmap_simplemap")) {
253 log("Mapping %s.%s (%s) with simplemap.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
254 if (simplemap_mappers.count(cell->type) == 0)
255 log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
256 simplemap_mappers.at(cell->type)(module, cell);
257 module->cells.erase(cell->name);
258 delete cell;
259 cell = NULL;
260 did_something = true;
261 break;
262 }
263
264 for (auto conn : cell->connections) {
265 if (conn.first.substr(0, 1) == "$")
266 continue;
267 if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0)
268 continue;
269 if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
270 goto next_tpl;
271 parameters[conn.first] = conn.second.as_const();
272 }
273
274 if (0) {
275 next_tpl:
276 continue;
277 }
278
279 if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0)
280 parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type);
281
282 for (auto conn : cell->connections) {
283 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
284 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
285 for (auto &bit : v)
286 bit = RTLIL::SigBit(bit.wire == NULL ? RTLIL::State::S1 : RTLIL::State::S0);
287 parameters[stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
288 }
289 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))) != 0) {
290 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
291 for (auto &bit : v)
292 if (bit.wire != NULL)
293 bit = RTLIL::SigBit(RTLIL::State::Sx);
294 parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
295 }
296 }
297
298 int unique_bit_id_counter = 0;
299 std::map<RTLIL::SigBit, int> unique_bit_id;
300 unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++;
301 unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++;
302 unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++;
303 unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
304
305 for (auto conn : cell->connections)
306 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
307 for (auto &bit : sigmap(conn.second).to_sigbit_vector())
308 if (unique_bit_id.count(bit) == 0)
309 unique_bit_id[bit] = unique_bit_id_counter++;
310 }
311
312 int bits = 0;
313 for (int i = 0; i < 32; i++)
314 if (((unique_bit_id_counter-1) & (1 << i)) != 0)
315 bits = i;
316 if (tpl->avail_parameters.count("\\_TECHMAP_BITS_CONNMAP_"))
317 parameters["\\_TECHMAP_BITS_CONNMAP_"] = bits;
318
319 for (auto conn : cell->connections)
320 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
321 RTLIL::Const value;
322 for (auto &bit : sigmap(conn.second).to_sigbit_vector()) {
323 RTLIL::Const chunk(unique_bit_id.at(bit), bits);
324 value.bits.insert(value.bits.end(), chunk.bits.begin(), chunk.bits.end());
325 }
326 parameters[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))] = value;
327 }
328 }
329
330 std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
331 if (techmap_cache.count(key) > 0) {
332 tpl = techmap_cache[key];
333 } else {
334 if (cell->parameters.size() != 0) {
335 derived_name = tpl->derive(map, parameters);
336 tpl = map->modules[derived_name];
337 log_continue = true;
338 }
339 techmap_cache[key] = tpl;
340 }
341
342 if (flatten_mode)
343 techmap_do_cache[tpl] = true;
344
345 if (techmap_do_cache.count(tpl) == 0)
346 {
347 bool keep_running = true;
348 techmap_do_cache[tpl] = true;
349
350 std::set<std::string> techmap_wire_names;
351
352 while (keep_running)
353 {
354 TechmapWires twd = techmap_find_special_wires(tpl);
355 keep_running = false;
356
357 for (auto &it : twd)
358 techmap_wire_names.insert(it.first);
359
360 for (auto &it : twd["_TECHMAP_FAIL_"]) {
361 RTLIL::SigSpec value = it.value;
362 if (value.is_fully_const() && value.as_bool()) {
363 log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
364 derived_name.c_str(), RTLIL::id2cstr(it.wire->name), log_signal(value));
365 techmap_do_cache[tpl] = false;
366 }
367 }
368
369 if (!techmap_do_cache[tpl])
370 break;
371
372 for (auto &it : twd)
373 {
374 if (it.first.substr(0, 12) != "_TECHMAP_DO_" || it.second.empty())
375 continue;
376
377 auto &data = it.second.front();
378
379 if (!data.value.is_fully_const())
380 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));
381
382 techmap_wire_names.erase(it.first);
383 tpl->wires.erase(data.wire->name);
384
385 const char *p = data.wire->name.c_str();
386 const char *q = strrchr(p+1, '.');
387 q = q ? q : p+1;
388
389 assert(!strncmp(q, "_TECHMAP_DO_", 12));
390 std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
391 while (tpl->wires.count(new_name))
392 new_name += "_";
393 data.wire->name = new_name;
394 tpl->add(data.wire);
395
396 std::string cmd_string = data.value.as_const().decode_string();
397 Pass::call_on_module(map, tpl, cmd_string);
398
399 keep_running = true;
400 break;
401 }
402 }
403
404 TechmapWires twd = techmap_find_special_wires(tpl);
405 for (auto &it : twd) {
406 if (it.first != "_TECHMAP_FAIL_" && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
407 log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str());
408 if (techmap_do_cache[tpl])
409 for (auto &it2 : it.second)
410 if (!it2.value.is_fully_const())
411 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
412 techmap_wire_names.erase(it.first);
413 }
414
415 for (auto &it : techmap_wire_names)
416 log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it));
417 }
418
419 if (techmap_do_cache.at(tpl) == false)
420 continue;
421
422 if (log_continue) {
423 log_header("Continuing TECHMAP pass.\n");
424 log_continue = false;
425 }
426
427 techmap_module_worker(design, module, cell, tpl, flatten_mode);
428 did_something = true;
429 cell = NULL;
430 break;
431 }
432
433 handled_cells.insert(cell);
434 }
435
436 if (log_continue) {
437 log_header("Continuing TECHMAP pass.\n");
438 log_continue = false;
439 }
440
441 return did_something;
442 }
443 };
444
445 struct TechmapPass : public Pass {
446 TechmapPass() : Pass("techmap", "generic technology mapper") { }
447 virtual void help()
448 {
449 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
450 log("\n");
451 log(" techmap [-map filename] [selection]\n");
452 log("\n");
453 log("This pass implements a very simple technology mapper that replaces cells in\n");
454 log("the design with implementations given in form of a verilog or ilang source\n");
455 log("file.\n");
456 log("\n");
457 log(" -map filename\n");
458 log(" the library of cell implementations to be used.\n");
459 log(" without this parameter a builtin library is used that\n");
460 log(" transforms the internal RTL cells to the internal gate\n");
461 log(" library.\n");
462 log("\n");
463 log(" -share_map filename\n");
464 log(" like -map, but look for the file in the share directory (where the\n");
465 log(" yosys data files are). this is mainly used internally when techmap\n");
466 log(" is called from other commands.\n");
467 log("\n");
468 log(" -max_iter <number>\n");
469 log(" only run the specified number of iterations.\n");
470 log("\n");
471 log(" -D <define>, -I <incdir>\n");
472 log(" this options are passed as-is to the verilog frontend for loading the\n");
473 log(" map file. Note that the verilog frontend is also called with the\n");
474 log(" '-ignore_redef' option set.\n");
475 log("\n");
476 log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
477 log("match cells with a type that match the text value of this attribute. Otherwise\n");
478 log("the module name will be used to match the cell.\n");
479 log("\n");
480 log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
481 log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
482 log("\n");
483 log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
484 log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
485 log("the mapping module to the techmap command. At the moment the following special\n");
486 log("wires are supported:\n");
487 log("\n");
488 log(" _TECHMAP_FAIL_\n");
489 log(" When this wire is set to a non-zero constant value, techmap will not\n");
490 log(" use this module and instead try the next module with a matching\n");
491 log(" 'techmap_celltype' attribute.\n");
492 log("\n");
493 log(" When such a wire exists but does not have a constant value after all\n");
494 log(" _TECHMAP_DO_* commands have been executed, an error is generated.\n");
495 log("\n");
496 log(" _TECHMAP_DO_*\n");
497 log(" This wires are evaluated in alphabetical order. The constant text value\n");
498 log(" of this wire is a yosys command (or sequence of commands) that is run\n");
499 log(" by techmap on the module. A common use case is to run 'proc' on modules\n");
500 log(" that are written using always-statements.\n");
501 log("\n");
502 log(" When such a wire has a non-constant value at the time it is to be\n");
503 log(" evaluated, an error is produced. That means it is possible for such a\n");
504 log(" wire to start out as non-constant and evaluate to a constant value\n");
505 log(" during processing of other _TECHMAP_DO_* commands.\n");
506 log("\n");
507 log("In addition to this special wires, techmap also supports special parameters in\n");
508 log("modules in the map file:\n");
509 log("\n");
510 log(" _TECHMAP_CELLTYPE_\n");
511 log(" When a parameter with this name exists, it will be set to the type name\n");
512 log(" of the cell that matches the module.\n");
513 log("\n");
514 log(" _TECHMAP_CONSTMSK_<port-name>_\n");
515 log(" _TECHMAP_CONSTVAL_<port-name>_\n");
516 log(" When this pair of parameters is available in a module for a port, then\n");
517 log(" former has a 1-bit for each constant input bit and the latter has the\n");
518 log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
519 log("\n");
520 log(" _TECHMAP_BITS_CONNMAP_\n");
521 log(" _TECHMAP_CONNMAP_<port-name>_\n");
522 log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
523 log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n");
524 log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n");
525 log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n");
526 log(" This can be used to detect shorted inputs.\n");
527 log("\n");
528 log("When a module in the map file has a parameter where the according cell in the\n");
529 log("design has a port, the module from the map file is only used if the port in\n");
530 log("the design is connected to a constant value. The parameter is then set to the\n");
531 log("constant value.\n");
532 log("\n");
533 log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
534 log("of the cell that is beeing replaced.\n");
535 log("\n");
536 log("See 'help extract' for a pass that does the opposite thing.\n");
537 log("\n");
538 log("See 'help flatten' for a pass that does flatten the design (which is\n");
539 log("esentially techmap but using the design itself as map library).\n");
540 log("\n");
541 }
542 virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
543 {
544 log_header("Executing TECHMAP pass (map to technology primitives).\n");
545 log_push();
546
547 std::vector<std::string> map_files;
548 std::string verilog_frontend = "verilog -ignore_redef";
549 int max_iter = -1;
550
551 size_t argidx;
552 std::string proc_share_path = proc_share_dirname();
553 for (argidx = 1; argidx < args.size(); argidx++) {
554 if (args[argidx] == "-map" && argidx+1 < args.size()) {
555 map_files.push_back(args[++argidx]);
556 continue;
557 }
558 if (args[argidx] == "-share_map" && argidx+1 < args.size()) {
559 map_files.push_back(proc_share_path + args[++argidx]);
560 continue;
561 }
562 if (args[argidx] == "-max_iter" && argidx+1 < args.size()) {
563 max_iter = atoi(args[++argidx].c_str());
564 continue;
565 }
566 if (args[argidx] == "-D" && argidx+1 < args.size()) {
567 verilog_frontend += " -D " + args[++argidx];
568 continue;
569 }
570 if (args[argidx] == "-I" && argidx+1 < args.size()) {
571 verilog_frontend += " -I " + args[++argidx];
572 continue;
573 }
574 break;
575 }
576 extra_args(args, argidx, design);
577
578 TechmapWorker worker;
579 simplemap_get_mappers(worker.simplemap_mappers);
580
581 RTLIL::Design *map = new RTLIL::Design;
582 if (map_files.empty()) {
583 FILE *f = fmemopen(stdcells_code, strlen(stdcells_code), "rt");
584 Frontend::frontend_call(map, f, "<stdcells.v>", verilog_frontend);
585 fclose(f);
586 } else
587 for (auto &fn : map_files) {
588 FILE *f = fopen(fn.c_str(), "rt");
589 if (f == NULL)
590 log_cmd_error("Can't open map file `%s'\n", fn.c_str());
591 Frontend::frontend_call(map, f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend);
592 fclose(f);
593 }
594
595 std::map<RTLIL::IdString, RTLIL::Module*> modules_new;
596 for (auto &it : map->modules) {
597 if (it.first.substr(0, 2) == "\\$")
598 it.second->name = it.first.substr(1);
599 modules_new[it.second->name] = it.second;
600 }
601 map->modules.swap(modules_new);
602
603 std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
604 for (auto &it : map->modules) {
605 if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) {
606 char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str());
607 for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
608 celltypeMap[RTLIL::escape_id(q)].insert(it.first);
609 free(p);
610 } else
611 celltypeMap[it.first].insert(it.first);
612 }
613
614 bool did_something = true;
615 std::set<RTLIL::Cell*> handled_cells;
616 while (did_something) {
617 did_something = false;
618 for (auto &mod_it : design->modules)
619 if (worker.techmap_module(design, mod_it.second, map, handled_cells, celltypeMap, false))
620 did_something = true;
621 if (did_something)
622 design->check();
623 if (max_iter > 0 && --max_iter == 0)
624 break;
625 }
626
627 log("No more expansions possible.\n");
628 delete map;
629
630 log_pop();
631 }
632 } TechmapPass;
633
634 struct FlattenPass : public Pass {
635 FlattenPass() : Pass("flatten", "flatten design") { }
636 virtual void help()
637 {
638 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
639 log("\n");
640 log(" flatten [selection]\n");
641 log("\n");
642 log("This pass flattens the design by replacing cells by their implementation. This\n");
643 log("pass is very simmilar to the 'techmap' pass. The only difference is that this\n");
644 log("pass is using the current design as mapping library.\n");
645 log("\n");
646 }
647 virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
648 {
649 log_header("Executing FLATTEN pass (flatten design).\n");
650 log_push();
651
652 extra_args(args, 1, design);
653
654 TechmapWorker worker;
655
656 std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
657 for (auto &it : design->modules)
658 celltypeMap[it.first].insert(it.first);
659
660 RTLIL::Module *top_mod = NULL;
661 if (design->full_selection())
662 for (auto &mod_it : design->modules)
663 if (mod_it.second->get_bool_attribute("\\top"))
664 top_mod = mod_it.second;
665
666 bool did_something = true;
667 std::set<RTLIL::Cell*> handled_cells;
668 while (did_something) {
669 did_something = false;
670 if (top_mod != NULL) {
671 if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true))
672 did_something = true;
673 } else {
674 for (auto &mod_it : design->modules)
675 if (worker.techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true))
676 did_something = true;
677 }
678 }
679
680 log("No more expansions possible.\n");
681
682 if (top_mod != NULL) {
683 std::map<RTLIL::IdString, RTLIL::Module*> new_modules;
684 for (auto &mod_it : design->modules)
685 if (mod_it.second == top_mod || mod_it.second->get_bool_attribute("\\blackbox")) {
686 new_modules[mod_it.first] = mod_it.second;
687 } else {
688 log("Deleting now unused module %s.\n", RTLIL::id2cstr(mod_it.first));
689 delete mod_it.second;
690 }
691 design->modules.swap(new_modules);
692 }
693
694 log_pop();
695 }
696 } FlattenPass;
697