2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/utils.h"
22 #include "kernel/sigtools.h"
23 #include "libs/sha1/sha1.h"
29 #include "simplemap.h"
30 #include "passes/techmap/techmap.inc"
35 extern void maccmap(RTLIL::Module
*module
, RTLIL::Cell
*cell
, bool unmap
= false);
40 PRIVATE_NAMESPACE_BEGIN
42 void apply_prefix(IdString prefix
, IdString
&id
)
45 id
= stringf("%s.%s", prefix
.c_str(), id
.c_str()+1);
47 id
= stringf("$techmap%s.%s", prefix
.c_str(), id
.c_str());
50 void apply_prefix(IdString prefix
, RTLIL::SigSpec
&sig
, RTLIL::Module
*module
)
52 vector
<SigChunk
> chunks
= sig
;
53 for (auto &chunk
: chunks
)
54 if (chunk
.wire
!= NULL
) {
55 IdString wire_name
= chunk
.wire
->name
;
56 apply_prefix(prefix
, wire_name
);
57 log_assert(module
->wires_
.count(wire_name
) > 0);
58 chunk
.wire
= module
->wires_
[wire_name
];
65 std::map
<RTLIL::IdString
, void(*)(RTLIL::Module
*, RTLIL::Cell
*)> simplemap_mappers
;
66 std::map
<std::pair
<RTLIL::IdString
, std::map
<RTLIL::IdString
, RTLIL::Const
>>, RTLIL::Module
*> techmap_cache
;
67 std::map
<RTLIL::Module
*, bool> techmap_do_cache
;
68 std::set
<RTLIL::Module
*, RTLIL::IdString::compare_ptr_by_name
<RTLIL::Module
>> module_queue
;
69 dict
<Module
*, SigMap
> sigmaps
;
71 pool
<IdString
> flatten_do_list
;
72 pool
<IdString
> flatten_done_list
;
73 pool
<Cell
*> flatten_keep_list
;
75 pool
<string
> log_msg_cache
;
77 struct TechmapWireData
{
82 typedef std::map
<std::string
, std::vector
<TechmapWireData
>> TechmapWires
;
96 recursive_mode
= false;
97 autoproc_mode
= false;
101 std::string
constmap_tpl_name(SigMap
&sigmap
, RTLIL::Module
*tpl
, RTLIL::Cell
*cell
, bool verbose
)
103 std::string constmap_info
;
104 std::map
<RTLIL::SigBit
, std::pair
<RTLIL::IdString
, int>> connbits_map
;
106 for (auto conn
: cell
->connections())
107 for (int i
= 0; i
< GetSize(conn
.second
); i
++) {
108 RTLIL::SigBit bit
= sigmap(conn
.second
[i
]);
109 if (bit
.wire
== nullptr) {
111 log(" Constant input on bit %d of port %s: %s\n", i
, log_id(conn
.first
), log_signal(bit
));
112 constmap_info
+= stringf("|%s %d %d", log_id(conn
.first
), i
, bit
.data
);
113 } else if (connbits_map
.count(bit
)) {
115 log(" Bit %d of port %s and bit %d of port %s are connected.\n", i
, log_id(conn
.first
),
116 connbits_map
.at(bit
).second
, log_id(connbits_map
.at(bit
).first
));
117 constmap_info
+= stringf("|%s %d %s %d", log_id(conn
.first
), i
,
118 log_id(connbits_map
.at(bit
).first
), connbits_map
.at(bit
).second
);
120 connbits_map
[bit
] = std::pair
<RTLIL::IdString
, int>(conn
.first
, i
);
121 constmap_info
+= stringf("|%s %d", log_id(conn
.first
), i
);
125 return stringf("$paramod$constmap:%s%s", sha1(constmap_info
).c_str(), tpl
->name
.c_str());
128 TechmapWires
techmap_find_special_wires(RTLIL::Module
*module
)
135 for (auto &it
: module
->wires_
) {
136 const char *p
= it
.first
.c_str();
140 const char *q
= strrchr(p
+1, '.');
143 if (!strncmp(p
, "_TECHMAP_", 9)) {
144 TechmapWireData record
;
145 record
.wire
= it
.second
;
146 record
.value
= it
.second
;
147 result
[p
].push_back(record
);
148 it
.second
->attributes
[ID::keep
] = RTLIL::Const(1);
149 it
.second
->attributes
[ID(_techmap_special_
)] = RTLIL::Const(1);
153 if (!result
.empty()) {
154 SigMap
sigmap(module
);
155 for (auto &it1
: result
)
156 for (auto &it2
: it1
.second
)
157 sigmap
.apply(it2
.value
);
163 void techmap_module_worker(RTLIL::Design
*design
, RTLIL::Module
*module
, RTLIL::Cell
*cell
, RTLIL::Module
*tpl
)
165 if (tpl
->processes
.size() != 0) {
166 log("Technology map yielded processes:");
167 for (auto &it
: tpl
->processes
)
168 log(" %s",RTLIL::id2cstr(it
.first
));
171 Pass::call_on_module(tpl
->design
, tpl
, "proc");
172 log_assert(GetSize(tpl
->processes
) == 0);
174 log_error("Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).\n");
177 std::string orig_cell_name
;
178 pool
<string
> extra_src_attrs
= cell
->get_strpool_attribute(ID(src
));
181 for (auto &it
: tpl
->cells_
)
182 if (it
.first
== ID(_TECHMAP_REPLACE_
)) {
183 orig_cell_name
= cell
->name
.str();
184 module
->rename(cell
, stringf("$techmap%d", autoidx
++) + cell
->name
.str());
189 dict
<IdString
, IdString
> memory_renames
;
191 for (auto &it
: tpl
->memories
) {
192 IdString m_name
= it
.first
;
193 apply_prefix(cell
->name
, m_name
);
194 RTLIL::Memory
*m
= new RTLIL::Memory
;
196 m
->width
= it
.second
->width
;
197 m
->start_offset
= it
.second
->start_offset
;
198 m
->size
= it
.second
->size
;
199 m
->attributes
= it
.second
->attributes
;
200 if (m
->attributes
.count(ID(src
)))
201 m
->add_strpool_attribute(ID(src
), extra_src_attrs
);
202 module
->memories
[m
->name
] = m
;
203 memory_renames
[it
.first
] = m
->name
;
204 design
->select(module
, m
);
207 std::map
<RTLIL::IdString
, RTLIL::IdString
> positional_ports
;
208 dict
<Wire
*, IdString
> temp_renamed_wires
;
209 pool
<SigBit
> autopurge_tpl_bits
;
211 for (auto &it
: tpl
->wires_
)
213 if (it
.second
->port_id
> 0)
215 IdString posportname
= stringf("$%d", it
.second
->port_id
);
216 positional_ports
[posportname
] = it
.first
;
218 if (!flatten_mode
&& it
.second
->get_bool_attribute(ID(techmap_autopurge
)) &&
219 (!cell
->hasPort(it
.second
->name
) || !GetSize(cell
->getPort(it
.second
->name
))) &&
220 (!cell
->hasPort(posportname
) || !GetSize(cell
->getPort(posportname
))))
222 if (sigmaps
.count(tpl
) == 0)
223 sigmaps
[tpl
].set(tpl
);
225 for (auto bit
: sigmaps
.at(tpl
)(it
.second
))
226 if (bit
.wire
!= nullptr)
227 autopurge_tpl_bits
.insert(bit
);
230 IdString w_name
= it
.second
->name
;
231 apply_prefix(cell
->name
, w_name
);
232 RTLIL::Wire
*w
= module
->wire(w_name
);
234 if (!flatten_mode
|| !w
->get_bool_attribute(ID(hierconn
))) {
235 temp_renamed_wires
[w
] = w
->name
;
236 module
->rename(w
, NEW_ID
);
239 w
->attributes
.erase(ID(hierconn
));
240 if (GetSize(w
) < GetSize(it
.second
)) {
241 log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module
), log_id(w
),
242 log_id(tpl
), log_id(it
.second
), log_id(module
), log_id(cell
));
243 w
->width
= GetSize(it
.second
);
248 w
= module
->addWire(w_name
, it
.second
);
249 w
->port_input
= false;
250 w
->port_output
= false;
253 w
->attributes
.erase(ID(techmap_autopurge
));
254 if (it
.second
->get_bool_attribute(ID(_techmap_special_
)))
255 w
->attributes
.clear();
256 if (w
->attributes
.count(ID(src
)))
257 w
->add_strpool_attribute(ID(src
), extra_src_attrs
);
259 design
->select(module
, w
);
262 SigMap
tpl_sigmap(tpl
);
263 pool
<SigBit
> tpl_written_bits
;
265 for (auto &it1
: tpl
->cells_
)
266 for (auto &it2
: it1
.second
->connections_
)
267 if (it1
.second
->output(it2
.first
))
268 for (auto bit
: tpl_sigmap(it2
.second
))
269 tpl_written_bits
.insert(bit
);
270 for (auto &it1
: tpl
->connections_
)
271 for (auto bit
: tpl_sigmap(it1
.first
))
272 tpl_written_bits
.insert(bit
);
274 SigMap port_signal_map
;
275 SigSig port_signal_assign
;
277 for (auto &it
: cell
->connections())
279 RTLIL::IdString portname
= it
.first
;
280 if (positional_ports
.count(portname
) > 0)
281 portname
= positional_ports
.at(portname
);
282 if (tpl
->wires_
.count(portname
) == 0 || tpl
->wires_
.at(portname
)->port_id
== 0) {
283 if (portname
.begins_with("$"))
284 log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname
.c_str(), cell
->name
.c_str(), tpl
->name
.c_str());
288 if (GetSize(it
.second
) == 0)
291 RTLIL::Wire
*w
= tpl
->wires_
.at(portname
);
292 RTLIL::SigSig c
, extra_connect
;
294 if (w
->port_output
&& !w
->port_input
) {
296 c
.second
= RTLIL::SigSpec(w
);
297 apply_prefix(cell
->name
, c
.second
, module
);
298 extra_connect
.first
= c
.second
;
299 extra_connect
.second
= c
.first
;
300 } else if (!w
->port_output
&& w
->port_input
) {
301 c
.first
= RTLIL::SigSpec(w
);
302 c
.second
= it
.second
;
303 apply_prefix(cell
->name
, c
.first
, module
);
304 extra_connect
.first
= c
.first
;
305 extra_connect
.second
= c
.second
;
307 SigSpec sig_tpl
= w
, sig_tpl_pf
= w
, sig_mod
= it
.second
;
308 apply_prefix(cell
->name
, sig_tpl_pf
, module
);
309 for (int i
= 0; i
< GetSize(sig_tpl
) && i
< GetSize(sig_mod
); i
++) {
310 if (tpl_written_bits
.count(tpl_sigmap(sig_tpl
[i
]))) {
311 c
.first
.append(sig_mod
[i
]);
312 c
.second
.append(sig_tpl_pf
[i
]);
314 c
.first
.append(sig_tpl_pf
[i
]);
315 c
.second
.append(sig_mod
[i
]);
318 extra_connect
.first
= sig_tpl_pf
;
319 extra_connect
.second
= sig_mod
;
322 if (c
.second
.size() > c
.first
.size())
323 c
.second
.remove(c
.first
.size(), c
.second
.size() - c
.first
.size());
325 if (c
.second
.size() < c
.first
.size())
326 c
.second
.append(RTLIL::SigSpec(RTLIL::State::S0
, c
.first
.size() - c
.second
.size()));
328 log_assert(c
.first
.size() == c
.second
.size());
332 // more conservative approach:
333 // connect internal and external wires
335 if (sigmaps
.count(module
) == 0)
336 sigmaps
[module
].set(module
);
338 if (sigmaps
.at(module
)(c
.first
).has_const())
339 log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
340 log_id(module
), log_id(cell
), log_id(it
.first
), log_signal(c
.first
), log_signal(c
.second
));
346 // approach that yields nicer outputs:
347 // replace internal wires that are connected to external wires
349 if (w
->port_output
&& !w
->port_input
) {
350 port_signal_map
.add(c
.second
, c
.first
);
352 if (!w
->port_output
&& w
->port_input
) {
353 port_signal_map
.add(c
.first
, c
.second
);
356 extra_connect
= SigSig();
359 for (auto &attr
: w
->attributes
) {
360 if (attr
.first
== ID(src
))
362 module
->connect(extra_connect
);
368 for (auto &it
: tpl
->cells_
)
370 IdString c_name
= it
.second
->name
.str();
371 bool techmap_replace_cell
= (!flatten_mode
) && (c_name
== ID(_TECHMAP_REPLACE_
));
373 if (techmap_replace_cell
)
374 c_name
= orig_cell_name
;
376 apply_prefix(cell
->name
, c_name
);
378 RTLIL::Cell
*c
= module
->addCell(c_name
, it
.second
);
379 design
->select(module
, c
);
381 if (!flatten_mode
&& c
->type
.begins_with("\\$"))
382 c
->type
= c
->type
.substr(1);
384 vector
<IdString
> autopurge_ports
;
386 for (auto &it2
: c
->connections_
)
388 bool autopurge
= false;
389 if (!autopurge_tpl_bits
.empty()) {
390 autopurge
= GetSize(it2
.second
) != 0;
391 for (auto &bit
: sigmaps
.at(tpl
)(it2
.second
))
392 if (!autopurge_tpl_bits
.count(bit
)) {
399 autopurge_ports
.push_back(it2
.first
);
401 apply_prefix(cell
->name
, it2
.second
, module
);
402 port_signal_map
.apply(it2
.second
);
406 for (auto &it2
: autopurge_ports
)
409 if (c
->type
.in(ID($memrd
), ID($memwr
), ID($meminit
))) {
410 IdString memid
= c
->getParam(ID(MEMID
)).decode_string();
411 log_assert(memory_renames
.count(memid
) != 0);
412 c
->setParam(ID(MEMID
), Const(memory_renames
[memid
].str()));
415 if (c
->type
== ID($mem
)) {
416 IdString memid
= c
->getParam(ID(MEMID
)).decode_string();
417 apply_prefix(cell
->name
, memid
);
418 c
->setParam(ID(MEMID
), Const(memid
.c_str()));
421 if (c
->attributes
.count(ID(src
)))
422 c
->add_strpool_attribute(ID(src
), extra_src_attrs
);
424 if (techmap_replace_cell
)
425 for (auto attr
: cell
->attributes
)
426 if (!c
->attributes
.count(attr
.first
))
427 c
->attributes
[attr
.first
] = attr
.second
;
430 for (auto &it
: tpl
->connections()) {
431 RTLIL::SigSig c
= it
;
432 apply_prefix(cell
->name
.str(), c
.first
, module
);
433 apply_prefix(cell
->name
.str(), c
.second
, module
);
434 port_signal_map
.apply(c
.first
);
435 port_signal_map
.apply(c
.second
);
439 module
->remove(cell
);
441 for (auto &it
: temp_renamed_wires
)
444 IdString name
= it
.second
;
445 IdString altname
= module
->uniquify(name
);
446 Wire
*other_w
= module
->wire(name
);
447 module
->rename(other_w
, altname
);
448 module
->rename(w
, name
);
452 bool techmap_module(RTLIL::Design
*design
, RTLIL::Module
*module
, RTLIL::Design
*map
, std::set
<RTLIL::Cell
*> &handled_cells
,
453 const std::map
<RTLIL::IdString
, std::set
<RTLIL::IdString
, RTLIL::sort_by_id_str
>> &celltypeMap
, bool in_recursion
)
455 std::string mapmsg_prefix
= in_recursion
? "Recursively mapping" : "Mapping";
457 if (!design
->selected(module
) || module
->get_blackbox_attribute(ignore_wb
))
460 bool log_continue
= false;
461 bool did_something
= false;
462 LogMakeDebugHdl mkdebug
;
464 SigMap
sigmap(module
);
466 dict
<SigBit
, State
> init_bits
;
467 pool
<SigBit
> remove_init_bits
;
469 for (auto wire
: module
->wires()) {
470 if (wire
->attributes
.count("\\init")) {
471 Const value
= wire
->attributes
.at("\\init");
472 for (int i
= 0; i
< min(GetSize(value
), GetSize(wire
)); i
++)
473 if (value
[i
] != State::Sx
)
474 init_bits
[sigmap(SigBit(wire
, i
))] = value
[i
];
478 TopoSort
<RTLIL::Cell
*, RTLIL::IdString::compare_ptr_by_name
<RTLIL::Cell
>> cells
;
479 std::map
<RTLIL::Cell
*, std::set
<RTLIL::SigBit
>> cell_to_inbit
;
480 std::map
<RTLIL::SigBit
, std::set
<RTLIL::Cell
*>> outbit_to_cell
;
482 for (auto cell
: module
->cells())
484 if (!design
->selected(module
, cell
) || handled_cells
.count(cell
) > 0)
487 std::string cell_type
= cell
->type
.str();
488 if (in_recursion
&& cell
->type
.begins_with("\\$"))
489 cell_type
= cell_type
.substr(1);
491 if (celltypeMap
.count(cell_type
) == 0) {
492 if (assert_mode
&& cell_type
.back() != '_')
493 log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type
));
498 bool keepit
= cell
->get_bool_attribute(ID(keep_hierarchy
));
499 for (auto &tpl_name
: celltypeMap
.at(cell_type
))
500 if (map
->modules_
[tpl_name
]->get_bool_attribute(ID(keep_hierarchy
)))
503 if (!flatten_keep_list
[cell
]) {
504 log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module
), log_id(cell
));
505 flatten_keep_list
.insert(cell
);
507 if (!flatten_done_list
[cell
->type
])
508 flatten_do_list
.insert(cell
->type
);
513 for (auto &conn
: cell
->connections())
515 RTLIL::SigSpec sig
= sigmap(conn
.second
);
518 if (GetSize(sig
) == 0)
521 for (auto &tpl_name
: celltypeMap
.at(cell_type
)) {
522 RTLIL::Module
*tpl
= map
->modules_
[tpl_name
];
523 RTLIL::Wire
*port
= tpl
->wire(conn
.first
);
524 if (port
&& port
->port_input
)
525 cell_to_inbit
[cell
].insert(sig
.begin(), sig
.end());
526 if (port
&& port
->port_output
)
527 for (auto &bit
: sig
)
528 outbit_to_cell
[bit
].insert(cell
);
535 for (auto &it_right
: cell_to_inbit
)
536 for (auto &it_sigbit
: it_right
.second
)
537 for (auto &it_left
: outbit_to_cell
[it_sigbit
])
538 cells
.edge(it_left
, it_right
.first
);
542 for (auto cell
: cells
.sorted
)
544 log_assert(handled_cells
.count(cell
) == 0);
545 log_assert(cell
== module
->cell(cell
->name
));
546 bool mapped_cell
= false;
548 std::string cell_type
= cell
->type
.str();
550 if (in_recursion
&& cell
->type
.begins_with("\\$"))
551 cell_type
= cell_type
.substr(1);
553 for (auto &tpl_name
: celltypeMap
.at(cell_type
))
555 RTLIL::IdString derived_name
= tpl_name
;
556 RTLIL::Module
*tpl
= map
->modules_
[tpl_name
];
557 std::map
<RTLIL::IdString
, RTLIL::Const
> parameters(cell
->parameters
.begin(), cell
->parameters
.end());
559 if (tpl
->get_blackbox_attribute(ignore_wb
))
564 std::string extmapper_name
;
566 if (tpl
->get_bool_attribute(ID(techmap_simplemap
)))
567 extmapper_name
= "simplemap";
569 if (tpl
->get_bool_attribute(ID(techmap_maccmap
)))
570 extmapper_name
= "maccmap";
572 if (tpl
->attributes
.count(ID(techmap_wrap
)))
573 extmapper_name
= "wrap";
575 if (!extmapper_name
.empty())
577 cell
->type
= cell_type
;
579 if ((extern_mode
&& !in_recursion
) || extmapper_name
== "wrap")
581 std::string m_name
= stringf("$extern:%s:%s", extmapper_name
.c_str(), log_id(cell
->type
));
583 for (auto &c
: cell
->parameters
)
584 m_name
+= stringf(":%s=%s", log_id(c
.first
), log_signal(c
.second
));
586 if (extmapper_name
== "wrap")
587 m_name
+= ":" + sha1(tpl
->attributes
.at(ID(techmap_wrap
)).decode_string());
589 RTLIL::Design
*extmapper_design
= extern_mode
&& !in_recursion
? design
: tpl
->design
;
590 RTLIL::Module
*extmapper_module
= extmapper_design
->module(m_name
);
592 if (extmapper_module
== nullptr)
594 extmapper_module
= extmapper_design
->addModule(m_name
);
595 RTLIL::Cell
*extmapper_cell
= extmapper_module
->addCell(cell
->type
, cell
);
597 extmapper_cell
->set_src_attribute(cell
->get_src_attribute());
599 int port_counter
= 1;
600 for (auto &c
: extmapper_cell
->connections_
) {
601 RTLIL::Wire
*w
= extmapper_module
->addWire(c
.first
, GetSize(c
.second
));
602 if (w
->name
.in(ID::Y
, ID(Q
)))
603 w
->port_output
= true;
605 w
->port_input
= true;
606 w
->port_id
= port_counter
++;
610 extmapper_module
->fixup_ports();
611 extmapper_module
->check();
613 if (extmapper_name
== "simplemap") {
614 log("Creating %s with simplemap.\n", log_id(extmapper_module
));
615 if (simplemap_mappers
.count(extmapper_cell
->type
) == 0)
616 log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell
->type
));
617 simplemap_mappers
.at(extmapper_cell
->type
)(extmapper_module
, extmapper_cell
);
618 extmapper_module
->remove(extmapper_cell
);
621 if (extmapper_name
== "maccmap") {
622 log("Creating %s with maccmap.\n", log_id(extmapper_module
));
623 if (extmapper_cell
->type
!= ID($macc
))
624 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell
->type
));
625 maccmap(extmapper_module
, extmapper_cell
);
626 extmapper_module
->remove(extmapper_cell
);
629 if (extmapper_name
== "wrap") {
630 std::string cmd_string
= tpl
->attributes
.at(ID(techmap_wrap
)).decode_string();
631 log("Running \"%s\" on wrapper %s.\n", cmd_string
.c_str(), log_id(extmapper_module
));
633 Pass::call_on_module(extmapper_design
, extmapper_module
, cmd_string
);
638 cell
->type
= extmapper_module
->name
;
639 cell
->parameters
.clear();
641 if (!extern_mode
|| in_recursion
) {
642 tpl
= extmapper_module
;
643 goto use_wrapper_tpl
;
646 auto msg
= stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module
), log_id(cell
->type
));
647 if (!log_msg_cache
.count(msg
)) {
648 log_msg_cache
.insert(msg
);
649 log("%s\n", msg
.c_str());
651 log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix
.c_str(), log_id(module
), log_id(cell
), log_id(cell
->type
), log_id(extmapper_module
));
655 auto msg
= stringf("Using extmapper %s for cells of type %s.", extmapper_name
.c_str(), log_id(cell
->type
));
656 if (!log_msg_cache
.count(msg
)) {
657 log_msg_cache
.insert(msg
);
658 log("%s\n", msg
.c_str());
660 log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix
.c_str(), log_id(module
), log_id(cell
), log_id(cell
->type
), extmapper_name
.c_str());
662 if (extmapper_name
== "simplemap") {
663 if (simplemap_mappers
.count(cell
->type
) == 0)
664 log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell
->type
));
665 simplemap_mappers
.at(cell
->type
)(module
, cell
);
668 if (extmapper_name
== "maccmap") {
669 if (cell
->type
!= ID($macc
))
670 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell
->type
));
671 maccmap(module
, cell
);
674 module
->remove(cell
);
678 did_something
= true;
683 for (auto conn
: cell
->connections()) {
684 if (conn
.first
.begins_with("$"))
686 if (tpl
->wires_
.count(conn
.first
) > 0 && tpl
->wires_
.at(conn
.first
)->port_id
> 0)
688 if (!conn
.second
.is_fully_const() || parameters
.count(conn
.first
) > 0 || tpl
->avail_parameters
.count(conn
.first
) == 0)
690 parameters
[conn
.first
] = conn
.second
.as_const();
698 if (tpl
->avail_parameters
.count(ID(_TECHMAP_CELLTYPE_
)) != 0)
699 parameters
[ID(_TECHMAP_CELLTYPE_
)] = RTLIL::unescape_id(cell
->type
);
701 for (auto conn
: cell
->connections()) {
702 if (tpl
->avail_parameters
.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn
.first
))) != 0) {
703 std::vector
<RTLIL::SigBit
> v
= sigmap(conn
.second
).to_sigbit_vector();
705 bit
= RTLIL::SigBit(bit
.wire
== NULL
? RTLIL::State::S1
: RTLIL::State::S0
);
706 parameters
[stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn
.first
))] = RTLIL::SigSpec(v
).as_const();
708 if (tpl
->avail_parameters
.count(stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn
.first
))) != 0) {
709 std::vector
<RTLIL::SigBit
> v
= sigmap(conn
.second
).to_sigbit_vector();
711 if (bit
.wire
!= NULL
)
712 bit
= RTLIL::SigBit(RTLIL::State::Sx
);
713 parameters
[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn
.first
))] = RTLIL::SigSpec(v
).as_const();
715 if (tpl
->avail_parameters
.count(stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn
.first
))) != 0) {
716 auto sig
= sigmap(conn
.second
);
717 RTLIL::Const
value(State::Sx
, sig
.size());
718 for (int i
= 0; i
< sig
.size(); i
++) {
719 auto it
= init_bits
.find(sig
[i
]);
720 if (it
!= init_bits
.end()) {
721 value
[i
] = it
->second
;
724 parameters
[stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn
.first
))] = value
;
728 int unique_bit_id_counter
= 0;
729 std::map
<RTLIL::SigBit
, int> unique_bit_id
;
730 unique_bit_id
[RTLIL::State::S0
] = unique_bit_id_counter
++;
731 unique_bit_id
[RTLIL::State::S1
] = unique_bit_id_counter
++;
732 unique_bit_id
[RTLIL::State::Sx
] = unique_bit_id_counter
++;
733 unique_bit_id
[RTLIL::State::Sz
] = unique_bit_id_counter
++;
735 for (auto conn
: cell
->connections())
736 if (tpl
->avail_parameters
.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn
.first
))) != 0) {
737 for (auto &bit
: sigmap(conn
.second
).to_sigbit_vector())
738 if (unique_bit_id
.count(bit
) == 0)
739 unique_bit_id
[bit
] = unique_bit_id_counter
++;
742 // Find highest bit set
744 for (int i
= 0; i
< 32; i
++)
745 if (((unique_bit_id_counter
-1) & (1 << i
)) != 0)
747 // Increment index by one to get number of bits
749 if (tpl
->avail_parameters
.count(ID(_TECHMAP_BITS_CONNMAP_
)))
750 parameters
[ID(_TECHMAP_BITS_CONNMAP_
)] = bits
;
752 for (auto conn
: cell
->connections())
753 if (tpl
->avail_parameters
.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn
.first
))) != 0) {
755 for (auto &bit
: sigmap(conn
.second
).to_sigbit_vector()) {
756 RTLIL::Const
chunk(unique_bit_id
.at(bit
), bits
);
757 value
.bits
.insert(value
.bits
.end(), chunk
.bits
.begin(), chunk
.bits
.end());
759 parameters
[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn
.first
))] = value
;
765 // do not register techmap_wrap modules with techmap_cache
767 std::pair
<RTLIL::IdString
, std::map
<RTLIL::IdString
, RTLIL::Const
>> key(tpl_name
, parameters
);
768 if (techmap_cache
.count(key
) > 0) {
769 tpl
= techmap_cache
[key
];
771 if (parameters
.size() != 0) {
773 derived_name
= tpl
->derive(map
, dict
<RTLIL::IdString
, RTLIL::Const
>(parameters
.begin(), parameters
.end()));
774 tpl
= map
->module(derived_name
);
777 techmap_cache
[key
] = tpl
;
782 techmap_do_cache
[tpl
] = true;
784 RTLIL::Module
*constmapped_tpl
= map
->module(constmap_tpl_name(sigmap
, tpl
, cell
, false));
785 if (constmapped_tpl
!= nullptr)
786 tpl
= constmapped_tpl
;
789 if (techmap_do_cache
.count(tpl
) == 0)
791 bool keep_running
= true;
792 techmap_do_cache
[tpl
] = true;
794 std::set
<std::string
> techmap_wire_names
;
798 TechmapWires twd
= techmap_find_special_wires(tpl
);
799 keep_running
= false;
802 techmap_wire_names
.insert(it
.first
);
804 for (auto &it
: twd
["_TECHMAP_FAIL_"]) {
805 RTLIL::SigSpec value
= it
.value
;
806 if (value
.is_fully_const() && value
.as_bool()) {
807 log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
808 derived_name
.c_str(), RTLIL::id2cstr(it
.wire
->name
), log_signal(value
));
809 techmap_do_cache
[tpl
] = false;
813 if (!techmap_do_cache
[tpl
])
818 if (it
.first
.compare(0, 12, "_TECHMAP_DO_") != 0 || it
.second
.empty())
821 auto &data
= it
.second
.front();
823 if (!data
.value
.is_fully_const())
824 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data
.wire
->name
), log_signal(data
.value
));
826 techmap_wire_names
.erase(it
.first
);
828 const char *p
= data
.wire
->name
.c_str();
829 const char *q
= strrchr(p
+1, '.');
832 std::string cmd_string
= data
.value
.as_const().decode_string();
834 restart_eval_cmd_string
:
835 if (cmd_string
.rfind("CONSTMAP; ", 0) == 0)
837 cmd_string
= cmd_string
.substr(strlen("CONSTMAP; "));
839 log("Analyzing pattern of constant bits for this cell:\n");
840 RTLIL::IdString new_tpl_name
= constmap_tpl_name(sigmap
, tpl
, cell
, true);
841 log("Creating constmapped module `%s'.\n", log_id(new_tpl_name
));
842 log_assert(map
->module(new_tpl_name
) == nullptr);
844 RTLIL::Module
*new_tpl
= map
->addModule(new_tpl_name
);
845 tpl
->cloneInto(new_tpl
);
847 techmap_do_cache
.erase(tpl
);
848 techmap_do_cache
[new_tpl
] = true;
851 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> port_new2old_map
;
852 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> port_connmap
;
853 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> cellbits_to_tplbits
;
855 for (auto wire
: tpl
->wires().to_vector())
857 if (!wire
->port_input
|| wire
->port_output
)
860 RTLIL::IdString port_name
= wire
->name
;
861 tpl
->rename(wire
, NEW_ID
);
863 RTLIL::Wire
*new_wire
= tpl
->addWire(port_name
, wire
);
864 wire
->port_input
= false;
867 for (int i
= 0; i
< wire
->width
; i
++) {
868 port_new2old_map
[RTLIL::SigBit(new_wire
, i
)] = RTLIL::SigBit(wire
, i
);
869 port_connmap
[RTLIL::SigBit(wire
, i
)] = RTLIL::SigBit(new_wire
, i
);
873 for (auto conn
: cell
->connections())
874 for (int i
= 0; i
< GetSize(conn
.second
); i
++)
876 RTLIL::SigBit bit
= sigmap(conn
.second
[i
]);
877 RTLIL::SigBit
tplbit(tpl
->wire(conn
.first
), i
);
879 if (bit
.wire
== nullptr)
881 RTLIL::SigBit oldbit
= port_new2old_map
.at(tplbit
);
882 port_connmap
.at(oldbit
) = bit
;
884 else if (cellbits_to_tplbits
.count(bit
))
886 RTLIL::SigBit oldbit
= port_new2old_map
.at(tplbit
);
887 port_connmap
.at(oldbit
) = cellbits_to_tplbits
[bit
];
890 cellbits_to_tplbits
[bit
] = tplbit
;
893 RTLIL::SigSig port_conn
;
894 for (auto &it
: port_connmap
) {
895 port_conn
.first
.append_bit(it
.first
);
896 port_conn
.second
.append_bit(it
.second
);
898 tpl
->connect(port_conn
);
901 goto restart_eval_cmd_string
;
904 if (cmd_string
.rfind("RECURSION; ", 0) == 0)
906 cmd_string
= cmd_string
.substr(strlen("RECURSION; "));
907 while (techmap_module(map
, tpl
, map
, handled_cells
, celltypeMap
, true)) { }
908 goto restart_eval_cmd_string
;
911 Pass::call_on_module(map
, tpl
, cmd_string
);
913 log_assert(!strncmp(q
, "_TECHMAP_DO_", 12));
914 std::string new_name
= data
.wire
->name
.substr(0, q
-p
) + "_TECHMAP_DONE_" + data
.wire
->name
.substr(q
-p
+12);
915 while (tpl
->wires_
.count(new_name
))
917 tpl
->rename(data
.wire
->name
, new_name
);
924 TechmapWires twd
= techmap_find_special_wires(tpl
);
925 for (auto &it
: twd
) {
926 if (it
.first
!= "_TECHMAP_FAIL_" && (it
.first
.substr(0, 20) != "_TECHMAP_REMOVEINIT_" || it
.first
[it
.first
.size()-1] != '_') && it
.first
.substr(0, 12) != "_TECHMAP_DO_" && it
.first
.substr(0, 14) != "_TECHMAP_DONE_")
927 log_error("Techmap yielded unknown config wire %s.\n", it
.first
.c_str());
928 if (techmap_do_cache
[tpl
])
929 for (auto &it2
: it
.second
)
930 if (!it2
.value
.is_fully_const())
931 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2
.wire
->name
), log_signal(it2
.value
));
932 if (it
.first
.substr(0, 20) == "_TECHMAP_REMOVEINIT_" && techmap_do_cache
[tpl
]) {
933 for (auto &it2
: it
.second
) {
934 auto val
= it2
.value
.as_const();
935 auto wirename
= RTLIL::escape_id(it
.first
.substr(20, it
.first
.size() - 20 - 1));
936 auto it
= cell
->connections().find(wirename
);
937 if (it
!= cell
->connections().end()) {
938 auto sig
= sigmap(it
->second
);
939 for (int i
= 0; i
< sig
.size(); i
++)
940 if (val
[i
] == State::S1
)
941 remove_init_bits
.insert(sig
[i
]);
945 techmap_wire_names
.erase(it
.first
);
948 for (auto &it
: techmap_wire_names
)
949 log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it
));
951 if (recursive_mode
) {
953 log_header(design
, "Continuing TECHMAP pass.\n");
954 log_continue
= false;
957 while (techmap_module(map
, tpl
, map
, handled_cells
, celltypeMap
, true)) { }
961 if (techmap_do_cache
.at(tpl
) == false)
965 log_header(design
, "Continuing TECHMAP pass.\n");
966 log_continue
= false;
970 if (extern_mode
&& !in_recursion
)
972 std::string m_name
= stringf("$extern:%s", log_id(tpl
));
974 if (!design
->module(m_name
))
976 RTLIL::Module
*m
= design
->addModule(m_name
);
979 for (auto cell
: m
->cells()) {
980 if (cell
->type
.begins_with("\\$"))
981 cell
->type
= cell
->type
.substr(1);
984 module_queue
.insert(m
);
987 log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix
.c_str(), log_id(module
), log_id(cell
), log_id(m_name
));
989 cell
->parameters
.clear();
993 auto msg
= stringf("Using template %s for cells of type %s.", log_id(tpl
), log_id(cell
->type
));
994 if (!log_msg_cache
.count(msg
)) {
995 log_msg_cache
.insert(msg
);
996 log("%s\n", msg
.c_str());
998 log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix
.c_str(), log_id(module
), log_id(cell
), log_id(cell
->type
), log_id(tpl
));
999 techmap_module_worker(design
, module
, cell
, tpl
);
1002 did_something
= true;
1007 if (assert_mode
&& !mapped_cell
)
1008 log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", log_id(module
), log_id(cell
), log_id(cell
->type
));
1010 handled_cells
.insert(cell
);
1013 if (!remove_init_bits
.empty()) {
1014 for (auto wire
: module
->wires())
1015 if (wire
->attributes
.count("\\init")) {
1016 Const
&value
= wire
->attributes
.at("\\init");
1017 bool do_cleanup
= true;
1018 for (int i
= 0; i
< min(GetSize(value
), GetSize(wire
)); i
++) {
1019 SigBit bit
= sigmap(SigBit(wire
, i
));
1020 if (remove_init_bits
.count(bit
))
1021 value
[i
] = State::Sx
;
1022 else if (value
[i
] != State::Sx
)
1026 log("Removing init attribute from wire %s.%s.\n", log_id(module
), log_id(wire
));
1027 wire
->attributes
.erase("\\init");
1033 log_header(design
, "Continuing TECHMAP pass.\n");
1034 log_continue
= false;
1038 return did_something
;
1042 struct TechmapPass
: public Pass
{
1043 TechmapPass() : Pass("techmap", "generic technology mapper") { }
1044 void help() YS_OVERRIDE
1046 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1048 log(" techmap [-map filename] [selection]\n");
1050 log("This pass implements a very simple technology mapper that replaces cells in\n");
1051 log("the design with implementations given in form of a Verilog or ilang source\n");
1054 log(" -map filename\n");
1055 log(" the library of cell implementations to be used.\n");
1056 log(" without this parameter a builtin library is used that\n");
1057 log(" transforms the internal RTL cells to the internal gate\n");
1060 log(" -map %%<design-name>\n");
1061 log(" like -map above, but with an in-memory design instead of a file.\n");
1064 log(" load the cell implementations as separate modules into the design\n");
1065 log(" instead of inlining them.\n");
1067 log(" -max_iter <number>\n");
1068 log(" only run the specified number of iterations on each module.\n");
1069 log(" default: unlimited\n");
1071 log(" -recursive\n");
1072 log(" instead of the iterative breadth-first algorithm use a recursive\n");
1073 log(" depth-first algorithm. both methods should yield equivalent results,\n");
1074 log(" but may differ in performance.\n");
1076 log(" -autoproc\n");
1077 log(" Automatically call \"proc\" on implementations that contain processes.\n");
1080 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
1083 log(" this option will cause techmap to exit with an error if it can't map\n");
1084 log(" a selected cell. only cell types that end on an underscore are accepted\n");
1085 log(" as final cell types by this mode.\n");
1087 log(" -D <define>, -I <incdir>\n");
1088 log(" this options are passed as-is to the Verilog frontend for loading the\n");
1089 log(" map file. Note that the Verilog frontend is also called with the\n");
1090 log(" '-nooverwrite' option set.\n");
1092 log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
1093 log("match cells with a type that match the text value of this attribute. Otherwise\n");
1094 log("the module name will be used to match the cell.\n");
1096 log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
1097 log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
1099 log("When a module in the map file has the 'techmap_maccmap' attribute set, techmap\n");
1100 log("will use 'maccmap' (see 'help maccmap') to map cells matching the module.\n");
1102 log("When a module in the map file has the 'techmap_wrap' attribute set, techmap\n");
1103 log("will create a wrapper for the cell and then run the command string that the\n");
1104 log("attribute is set to on the wrapper module.\n");
1106 log("When a port on a module in the map file has the 'techmap_autopurge' attribute\n");
1107 log("set, and that port is not connected in the instantiation that is mapped, then\n");
1108 log("then a cell port connected only to such wires will be omitted in the mapped\n");
1109 log("version of the circuit.\n");
1111 log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
1112 log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
1113 log("the mapping module to the techmap command. At the moment the following special\n");
1114 log("wires are supported:\n");
1116 log(" _TECHMAP_FAIL_\n");
1117 log(" When this wire is set to a non-zero constant value, techmap will not\n");
1118 log(" use this module and instead try the next module with a matching\n");
1119 log(" 'techmap_celltype' attribute.\n");
1121 log(" When such a wire exists but does not have a constant value after all\n");
1122 log(" _TECHMAP_DO_* commands have been executed, an error is generated.\n");
1124 log(" _TECHMAP_DO_*\n");
1125 log(" This wires are evaluated in alphabetical order. The constant text value\n");
1126 log(" of this wire is a yosys command (or sequence of commands) that is run\n");
1127 log(" by techmap on the module. A common use case is to run 'proc' on modules\n");
1128 log(" that are written using always-statements.\n");
1130 log(" When such a wire has a non-constant value at the time it is to be\n");
1131 log(" evaluated, an error is produced. That means it is possible for such a\n");
1132 log(" wire to start out as non-constant and evaluate to a constant value\n");
1133 log(" during processing of other _TECHMAP_DO_* commands.\n");
1135 log(" A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.\n");
1136 log(" in this case techmap will create a copy for each distinct configuration\n");
1137 log(" of constant inputs and shorted inputs at this point and import the\n");
1138 log(" constant and connected bits into the map module. All further commands\n");
1139 log(" are executed in this copy. This is a very convenient way of creating\n");
1140 log(" optimized specializations of techmap modules without using the special\n");
1141 log(" parameters described below.\n");
1143 log(" A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.\n");
1144 log(" then techmap will recursively replace the cells in the module with their\n");
1145 log(" implementation. This is not affected by the -max_iter option.\n");
1147 log(" It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n");
1149 log(" _TECHMAP_REMOVEINIT_<port-name>_\n");
1150 log(" When this wire is set to a constant value, the init attribute of the wire(s)\n");
1151 log(" connected to this port will be consumed. This wire must have the same\n");
1152 log(" width as the given port, and for every bit that is set to 1 in the value,\n");
1153 log(" the corresponding init attribute bit will be changed to 1'bx. If all\n");
1154 log(" bits of an init attribute are left as x, it will be removed.\n");
1156 log("In addition to this special wires, techmap also supports special parameters in\n");
1157 log("modules in the map file:\n");
1159 log(" _TECHMAP_CELLTYPE_\n");
1160 log(" When a parameter with this name exists, it will be set to the type name\n");
1161 log(" of the cell that matches the module.\n");
1163 log(" _TECHMAP_CONSTMSK_<port-name>_\n");
1164 log(" _TECHMAP_CONSTVAL_<port-name>_\n");
1165 log(" When this pair of parameters is available in a module for a port, then\n");
1166 log(" former has a 1-bit for each constant input bit and the latter has the\n");
1167 log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
1169 log(" _TECHMAP_WIREINIT_<port-name>_\n");
1170 log(" When a parameter with this name exists, it will be set to the initial\n");
1171 log(" value of the wire(s) connected to the given port, as specified by the init\n");
1172 log(" attribute. If the attribute doesn't exist, x will be filled for the\n");
1173 log(" missing bits. To remove the init attribute bits used, use the\n");
1174 log(" _TECHMAP_REMOVEINIT_*_ wires.\n");
1176 log(" _TECHMAP_BITS_CONNMAP_\n");
1177 log(" _TECHMAP_CONNMAP_<port-name>_\n");
1178 log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
1179 log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n");
1180 log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n");
1181 log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n");
1182 log(" This can be used to detect shorted inputs.\n");
1184 log("When a module in the map file has a parameter where the according cell in the\n");
1185 log("design has a port, the module from the map file is only used if the port in\n");
1186 log("the design is connected to a constant value. The parameter is then set to the\n");
1187 log("constant value.\n");
1189 log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
1190 log("and attributes of the cell that is being replaced.\n");
1192 log("See 'help extract' for a pass that does the opposite thing.\n");
1194 log("See 'help flatten' for a pass that does flatten the design (which is\n");
1195 log("essentially techmap but using the design itself as map library).\n");
1198 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1200 log_header(design
, "Executing TECHMAP pass (map to technology primitives).\n");
1203 TechmapWorker worker
;
1204 simplemap_get_mappers(worker
.simplemap_mappers
);
1206 std::vector
<std::string
> map_files
;
1207 std::string verilog_frontend
= "verilog -nooverwrite -noblackbox";
1211 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
1212 if (args
[argidx
] == "-map" && argidx
+1 < args
.size()) {
1213 map_files
.push_back(args
[++argidx
]);
1216 if (args
[argidx
] == "-max_iter" && argidx
+1 < args
.size()) {
1217 max_iter
= atoi(args
[++argidx
].c_str());
1220 if (args
[argidx
] == "-D" && argidx
+1 < args
.size()) {
1221 verilog_frontend
+= " -D " + args
[++argidx
];
1224 if (args
[argidx
] == "-I" && argidx
+1 < args
.size()) {
1225 verilog_frontend
+= " -I " + args
[++argidx
];
1228 if (args
[argidx
] == "-assert") {
1229 worker
.assert_mode
= true;
1232 if (args
[argidx
] == "-extern") {
1233 worker
.extern_mode
= true;
1236 if (args
[argidx
] == "-recursive") {
1237 worker
.recursive_mode
= true;
1240 if (args
[argidx
] == "-autoproc") {
1241 worker
.autoproc_mode
= true;
1244 if (args
[argidx
] == "-wb") {
1245 worker
.ignore_wb
= true;
1250 extra_args(args
, argidx
, design
);
1252 RTLIL::Design
*map
= new RTLIL::Design
;
1253 if (map_files
.empty()) {
1254 std::istringstream
f(stdcells_code
);
1255 Frontend::frontend_call(map
, &f
, "<techmap.v>", verilog_frontend
);
1257 for (auto &fn
: map_files
)
1258 if (fn
.compare(0, 1, "%") == 0) {
1259 if (!saved_designs
.count(fn
.substr(1))) {
1261 log_cmd_error("Can't saved design `%s'.\n", fn
.c_str()+1);
1263 for (auto mod
: saved_designs
.at(fn
.substr(1))->modules())
1264 if (!map
->has(mod
->name
))
1265 map
->add(mod
->clone());
1268 rewrite_filename(fn
);
1270 yosys_input_files
.insert(fn
);
1272 log_cmd_error("Can't open map file `%s'\n", fn
.c_str());
1273 Frontend::frontend_call(map
, &f
, fn
, (fn
.size() > 3 && fn
.compare(fn
.size()-3, std::string::npos
, ".il") == 0 ? "ilang" : verilog_frontend
));
1277 log_header(design
, "Continuing TECHMAP pass.\n");
1279 std::map
<RTLIL::IdString
, std::set
<RTLIL::IdString
, RTLIL::sort_by_id_str
>> celltypeMap
;
1280 for (auto &it
: map
->modules_
) {
1281 if (it
.second
->attributes
.count(ID(techmap_celltype
)) && !it
.second
->attributes
.at(ID(techmap_celltype
)).bits
.empty()) {
1282 char *p
= strdup(it
.second
->attributes
.at(ID(techmap_celltype
)).decode_string().c_str());
1283 for (char *q
= strtok(p
, " \t\r\n"); q
; q
= strtok(NULL
, " \t\r\n"))
1284 celltypeMap
[RTLIL::escape_id(q
)].insert(it
.first
);
1287 string module_name
= it
.first
.str();
1288 if (it
.first
.begins_with("\\$"))
1289 module_name
= module_name
.substr(1);
1290 celltypeMap
[module_name
].insert(it
.first
);
1294 for (auto module
: design
->modules())
1295 worker
.module_queue
.insert(module
);
1297 while (!worker
.module_queue
.empty())
1299 RTLIL::Module
*module
= *worker
.module_queue
.begin();
1300 worker
.module_queue
.erase(module
);
1302 int module_max_iter
= max_iter
;
1303 bool did_something
= true;
1304 std::set
<RTLIL::Cell
*> handled_cells
;
1305 while (did_something
) {
1306 did_something
= false;
1307 if (worker
.techmap_module(design
, module
, map
, handled_cells
, celltypeMap
, false))
1308 did_something
= true;
1311 if (module_max_iter
> 0 && --module_max_iter
== 0)
1316 log("No more expansions possible.\n");
1323 struct FlattenPass
: public Pass
{
1324 FlattenPass() : Pass("flatten", "flatten design") { }
1325 void help() YS_OVERRIDE
1327 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1329 log(" flatten [options] [selection]\n");
1331 log("This pass flattens the design by replacing cells by their implementation. This\n");
1332 log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
1333 log("pass is using the current design as mapping library.\n");
1335 log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
1336 log("flattened by this command.\n");
1339 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
1342 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1344 log_header(design
, "Executing FLATTEN pass (flatten design).\n");
1347 TechmapWorker worker
;
1348 worker
.flatten_mode
= true;
1351 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
1352 if (args
[argidx
] == "-wb") {
1353 worker
.ignore_wb
= true;
1358 extra_args(args
, argidx
, design
);
1361 std::map
<RTLIL::IdString
, std::set
<RTLIL::IdString
, RTLIL::sort_by_id_str
>> celltypeMap
;
1362 for (auto module
: design
->modules())
1363 celltypeMap
[module
->name
].insert(module
->name
);
1365 RTLIL::Module
*top_mod
= NULL
;
1366 if (design
->full_selection())
1367 for (auto mod
: design
->modules())
1368 if (mod
->get_bool_attribute(ID(top
)))
1371 std::set
<RTLIL::Cell
*> handled_cells
;
1372 if (top_mod
!= NULL
) {
1373 worker
.flatten_do_list
.insert(top_mod
->name
);
1374 while (!worker
.flatten_do_list
.empty()) {
1375 auto mod
= design
->module(*worker
.flatten_do_list
.begin());
1376 while (worker
.techmap_module(design
, mod
, design
, handled_cells
, celltypeMap
, false)) { }
1377 worker
.flatten_done_list
.insert(mod
->name
);
1378 worker
.flatten_do_list
.erase(mod
->name
);
1381 for (auto mod
: vector
<Module
*>(design
->modules())) {
1382 while (worker
.techmap_module(design
, mod
, design
, handled_cells
, celltypeMap
, false)) { }
1387 log("No more expansions possible.\n");
1389 if (top_mod
!= NULL
)
1391 pool
<RTLIL::IdString
> used_modules
, new_used_modules
;
1392 new_used_modules
.insert(top_mod
->name
);
1393 while (!new_used_modules
.empty()) {
1394 pool
<RTLIL::IdString
> queue
;
1395 queue
.swap(new_used_modules
);
1396 for (auto modname
: queue
)
1397 used_modules
.insert(modname
);
1398 for (auto modname
: queue
)
1399 for (auto cell
: design
->module(modname
)->cells())
1400 if (design
->module(cell
->type
) && !used_modules
[cell
->type
])
1401 new_used_modules
.insert(cell
->type
);
1404 dict
<RTLIL::IdString
, RTLIL::Module
*> new_modules
;
1405 for (auto mod
: vector
<Module
*>(design
->modules()))
1406 if (used_modules
[mod
->name
] || mod
->get_blackbox_attribute(worker
.ignore_wb
)) {
1407 new_modules
[mod
->name
] = mod
;
1409 log("Deleting now unused module %s.\n", log_id(mod
));
1412 design
->modules_
.swap(new_modules
);
1419 PRIVATE_NAMESPACE_END